Lakshmi Narain College of Technology Excellence, Bhopal

Department of Computer Science and Engineering

Experiment No. 1

AIM: Study Of Multiplexer And Demultiplexer.

THEORY: 74153 is a dual 4 line-to-1 line multiplexer. It has the schematic representation shown in
Fig 1. Selection lines A and B select the particular input to be multiplexed and applied to the output
IY{1 = 1, 2}.Each of the strobe signals IG {I = 1, 2} acts as an enable signal for the corresponding
multiplexer.Figure 2(a) & 2(b) shows the multiplex function of 74153 in terms of select lines. Note that
each of the on-chip multiplexers act independently from the other, while sharing the same select lines
A and B.

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Strobe Select Lines Select lines outputs

1G A B 1Y
1 x x 0
0 0 0 1C0

0 0 1 1C1
0 1 0 1C2
0 1 1 1C3

Strobe Select Lines Select Lines Outputs

2G A B 2Y
1 x x 0
0 0 0 2C0
0 0 1 2C1
0 1 0 2C2
0 1 1 2C3

Figure 2(b) x:don't care state

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The above circuit diagram shows the detail gate level structure of 74153(Dual 4 line to 1 line
Multiplexer)

74157 is a quad 2 line-to-1 line multiplexer. It has the schematic representation shown in Fig 3. Select
line select the particular input to be multiplexed and applied to the output IY{1 = 1, 2, 3, 4}. Strobe
signal acts as an enable signal for each of the four multiplexers. Figure 4(a) & 4(b) & 4(c) & 4(d)
shows the multiplex function of 74157 in terms of select lines. Note that each of the on-chip
multiplexers act independently from the other, while sharing the same select line.

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Figure 3(74157)

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Department of Computer Science and Engineering

Experiment No. 2

AIM: To Study & Verify Half and Full Subtractor.

THEORY : Subtractor circuits take two binary numbers as input and subtract one binary number input
from the other binary number input. Similar to adders, it gives out two outputs, difference and borrow
(carry-in the case of Adder)

There are two types of Subtractor:

1. Half Subtractor
2. Full Subtractor

1) Half Subtractor

The half-subtractor is a combinational circuit which is used to perform subtraction of two bits. It has
two inputs, A (minuend) and B (subtrahend) and two outputs Difference and Borrow. The logic symbol
and truth table are shown below.

Figure-1:Logic Symbol of Half subtractor

Figure-2:Truth Table of Half subtractor

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Figure-3:Circuit Diagram of Half subtractor

From the above truth table we can find the boolean expression.

Difference = A ⊕ B
Borrow = A' B

From the equation we can draw the half-subtractor circuit as shown in the figure 3.

2) Full Subtractor

A full subtractor is a combinational circuit that performs subtraction involving three bits, namely A
(minuend), B (subtrahend), and Bin (borrow-in) . It accepts three inputs: A (minuend), B (subtrahend)
and a Bin (borrow bit) and it produces two outputs: D (difference) and Bout (borrow out). The logic
symbol and truth table are shown below.

Figure-4:Logic Symbol of Full subtractor

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Figure-5:Truth Table of Full subtractor

From the above truth table we can find the boolean expression.

D = A ⊕ B ⊕ Bin
Bout = A' Bin + A' B + B Bin

From the equation we can draw the Full-subtractor circuit as shown in the figure 6.

Figure-6:Circuit Diagram of Full subtractor

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Department of Computer Science and Engineering

Experiment No. 3

AIM: To Study & Verify Half and Full Adder

THEORY: To implement Half and full adder by using basic and universal gates.

Adders

Digital computers perform a variety of information processing tasks. Among the basic tasks
encountered are the various arithmatic operartions. The most basic arithmatic operation is the additon
of two binary digits.

A combinational circuit that performs the addition of two bits is called a half adder. Again the
combinational circuit that performs addition of three bits (Two significant bits and a previous carry) is
called Full adder.

Half Adder

A half adder is a combinational circuit with two binary inputs (augend and addend bits) and two binary
outputs (sum and carry bits). It adds two inputs (A and B) and produces the sum (S) and the carry (C)
bits. It is an arithmatic circuit used to perform the arithmatic operaton of addition of two single bit
words.

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Inputs Inputs Outputs Outputs

A B C S
0 0 0 0

0 1 0 1
1 0 0 1

1 1 1 0

The characteristic equation of a Half Adder is expressed as:

Sum = AB̅ + A̅B = A⨁B

Cout = AB

When any of the inputs A and B is equal to 1, the Sum is 1. Otherwise, it is 0. Carry Cout is 1 only
when both the inputs are 1.

Full Adder

The combinational circuit that performs addition of three bits (Two significant bits and a previous
carry) is called Full adder.

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Truth Table

Inputs Inputs Inputs Outputs Outputs

A B Cin Cout S
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1

The characteristic equation of a Full Adder is expressed as:

Sum = A̅B̅Cin+A̅BCin+AB̅C̅in+ABCin = (AB̅+A̅B)C̅in+(AB+A̅B̅)Cin = (A⨁B)C̅in+(¯(A⨁B))Cin =

A⨁B⨁Cin

Cout = A̅BCin+AB̅Cin+ABC̅in+ABCin = AB+(A ⨁B)Cin = AB+ACin+BCin

The Sum is High i.e. 1 only when odd number of the inputs are High. Carry Cout is High i.e. 1 only
when more than one input are High.

Sum = A̅B̅Cin+A̅BCin+AB̅C̅in+ABCin = (AB̅+A̅B)C̅in+(AB+A̅B̅)Cin = (A⨁B)C̅in+(¯(A⨁B))Cin =

A⨁B⨁Cin

Cout = A̅BCin+AB̅Cin+ABC̅in+ABCin = AB+(A⨁B)Cin = AB+ACin+BCin

The Sum is High i.e. 1 only when odd number of the inputs are High. Carry Cout is High i.e. 1 only
when more than one input are High.

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Department of Computer Science and Engineering

Experiment No. 4

AIM: Write a program in assembly language to enter two values in register and perform
addition

TOOLS REQUIRED: PC with debug utility or 8086 Emulator

ALGORITHM:
1. Initialize G.P. register
2. Transfer data 03 in AX register
3. Transfer data 02 in BX register
4. Add the data
5. Stop
FLOWCHART

START

Initialize G.P. register

Move to AX
Move BX to AX

Move to AX

Add AX to BX

STOP

Snap shot of the Code:

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 Lakshmi Narain College of Technology Excellence, Bhopal

Department of Computer Science and Engineering

Snap shot of the Input:

Snap shot of the Result:

OBSERVATION TABLE:-

S.No Memory Hex Code Mnemonics Comments/Flags

Location
1 0B1D:0100 B80220 MOV AX,03 NV UP EI PL NZ NA
PO NC
2 0B1D:0103 BB0220 MOV BX,02 NV UP EI PL NZ NA
PO NC
3 0B1D:0106 01D8 ADD AX,BX NV UP EI PL NZ NA
PO NC
4 0B1D:0108 F4 HLT NV UP EI PL NZ NA
PE NC

Conclusion:
Hence the program was successfully executed.

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 Lakshmi Narain College of Technology Excellence, Bhopal

Department of Computer Science and Engineering

Experiment No. 5

AIM: Write a program in assembly language to enter two values in register and perform
subtraction.

TOOLS REQUIRED: PC with debug utility or 8086 Emulator.

ALGORITHM:
1. Initialize G.P. register
2. Transfer data 05 in AX
3. Transfer data in 04 BX
4. subtract the data
5. Stop

FLOWCHART

START

Initialize g.p.register

Move data in AX
Move data in BX

SUB AX FROM BX

STOP

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Snap shot of the Code:

Snap shot of the Input:

Snap shot of the Result:

OBSERVATION TABLE:-

S.No Memory Hex Code Mnemonics Comments/Flags

Location
1 0B1D:0100 B80400 MOV AX,05 NV UP EI PL NZ NA
PO NC
2 0B1D:0103 BB0400 MOV BX,04 NV UP EI PL NZ NA
PO NC
3 0B1D:0106 29D8 SUB AX,BX NV UP EI PL NZ NA
PO NC
4 0B1D:0108 F4 HLT NV UP EI PL NZ NA
PO NC
Conclusion:

Hence the program was successfully executed.

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 Lakshmi Narain College of Technology Excellence, Bhopal

Department of Computer Science and Engineering

Experiment No. 6

AIM: write a program in assembly language to enter two values in register and perform
multiplication.

TOOLS REQUIRED: PC with debug utility or 8086 Emulator.

ALGORITHM:
1. Initialize AX register
2. Initialize BX register
3. multiply the data
4. Stop

FLOWCHART

START

Initialize g.p. register

Move 05 in AX

Move 02 in BX
A

Multiplication of AX and BX

STOP

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Snap shot of the Code:

Snap shot of the Input:

Snap shot of the Result:

OBSERVATION TABLE:-

S.No Memory Hex Code Mnemonics Comments/Flags

Location
1 0B1D:0100 B80200 MOV AX,05 NV UP EI PL NZ NA
PO NC
2 0B1D:0103 BB0200 MOV BX,02 NV UP EI PL NZ NA
PO NC
3 0B1D:0106 F7E3 ADD AX,BX NV UP EI PL NZ NA
PO NC
4 0B1D:0108 F4 HLT NV UP EI PL NZ NA
PE NC

Conclusion:
Hence the program was successfully executed.

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 Lakshmi Narain College of Technology Excellence, Bhopal

Department of Computer Science and Engineering

Experiment No. 7

AIM: write a program in assembly language to enter two values in register and perform
division.

TOOLS REQUIRED: PC with debug utility or 8086 Emulator.

ALGORITHM:
1. Initialize AX register
2. Initialize BX register
3. divide the data AX from BX register
4. Stop
FLOWCHART

START

Initialize G.P. register

Move to AX

Move to BX
A

DIV AX AND BX

STOP

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 Lakshmi Narain College of Technology Excellence, Bhopal

Department of Computer Science and Engineering

Snap shot of the Code:

Snap shot of the Input:

Snap shot of the Result:

OBSERVATION TABLE:-

S.No Memory Hex Code Mnemonics Comments/Flags

Location
1 0B1D:0100 B80200 MOV AX,08 NV UP EI PL NZ NA
PO NC
2 0B1D:0103 BB0200 MOV BX,02 NV UP EI PL NZ NA
PO NC
3 0B1D:0106 F7E3 ADD AX,BX NV UP EI PL NZ NA
PO NC
4 0B1D:0108 F4 HLT NV UP EI PL NZ NA
PE NC

Conclusion:

Hence the program was successfully executed.

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 Lakshmi Narain College of Technology Excellence, Bhopal

Department of Computer Science and Engineering

Experiment No. 8

AIM: Write a program to add a data byte located at offset 0500H in 2000H segment to
another data byte available at 0600H in same segment and store the resulting 0700H in same
segment.

TOOLS REQUIRED: PC with debug utility or 8086 Emulator.

ALGORITHM:
1) Initialise segment register
2) Get contain in 0500H in G.P. register
3) Perform addition
4) store result in 0700H

FLOWCHART

START

Initialise segment register

Get content of 0500H in G.P.

Register

Perform Addition

Store result in 0700H

STOP

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Snap shot of the Code:

Snap shot of the Input:

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 Lakshmi Narain College of Technology Excellence, Bhopal

Department of Computer Science and Engineering

Snap shot of the Result:

OBSERVATION TABLE:-

S.No Memory Hex Code Mnemonics Comments/Flags

Location
1 0B27:0100 B80020 MOV AX,2000 NV UP EI PL NZ NA
PO NC
2 0B27:0103 8ED8 MOV DS,AX NV UP EI PL NZ NA
PO NC
3 0B27:0105 A10005 MOV NV UP EI PL NZ NA
PO NC
AX,[0500]
4 0B27:0108 03060006 ADD NV UP EI PL NZ NA
PO NC
AX,[0600]
5 0B27:010C A30007 MOV NV UP EI PL NZ AC
PE NC
[0700],AX
6 0B27:010F F4 HLT NV UP EI PL NZ NA
PE NC

Conclusion:
Hence the program was successfully executed.

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 Lakshmi Narain College of Technology Excellence, Bhopal

Department of Computer Science and Engineering

Experiment No. 9

AIM: Write a program to find out the largest number from an unordered array of sixteen 8-
bit numbers stored sequentially in the memory location starting at offset 0500H in the
segment 2000H.

TOOLS REQUIRED: PC with debug utility or 8086 Emulator.

ALGORITHM:
1) Initialize counter for number of iterations.
2) Intialize data segment
3) Initialize source index
4) Take first number in AX
5) Increment source index
6) Compare next number with previous
7) If the next number is larger
8) Replace the previous one with the next
9) Repeat the procedure 5 times.
FLOWCHART
START

Initialise the counter and data pointer

First number in AX register

Compare the next with the first

No Next
no.>1

yes
Replace the first number by the next number

Update index and loop back (counter times)

STOP

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Snap shot of the Code:

Snap shot of the Input:

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 Lakshmi Narain College of Technology Excellence, Bhopal

Department of Computer Science and Engineering

Snap shot of the Result:

OBSERVATION TABLE:-

S.No Memory Hex Code Mnemonics Comments/Flags

Location
1 0B27:0100 B90500 MOV CX,05 NV UP EI PL NZ NA
PO NC
2 0B27:0103 B80020 MOV AX,2000 NV UP EI PL NZ NA
PO NC
3 0B27:0106 8ED8 MOV DS,AX NV UP EI PL NZ NA
PO NC
4 0B27:0108 BE0005 MOV SI,0500 NV UP EI PL NZ NA
PO NC
5 0B27:010B 8B04 MOV AX,[SI] NV UP EI PL NZ NA
PO NC
6 0B27:010D 46 INC SI NV UP EI PL NZ NA
PO NC
7 0B27:010E 3B04 CMP AX ,[SI] NV UP EI PL NZ NA

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PO NC
8 0B27:0110 7302 JNC NV UP EI PL NZ AC
PE NC
0B27:0114
9 0B27:0112 8B04 MOV AX,[SI] NV UP EI PL NZ AC
PE NC
10 0B27:0114 E2F7 LOOP NV UP EI PL NZ AC
PE NC
0B27:010D
11 0B27:0116 F4 HLT NV UP EI PL NZ NA
PE NC

Conclusion:
Hence the program was successfully executed.

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 Lakshmi Narain College of Technology Excellence, Bhopal

Department of Computer Science and Engineering

Experiment No. 10

AIM: Write a program to move a byte string, 16 bytes long, from the offset 0200H to
0300H in the segment 7000H.

TOOLS REQUIRED: PC with debug utility or 8086 Emulator.

ALGORITHM:
1) Data segment initialization
2) Initialize source pointer
3) Initialize destination pointer
4) Initialize counter for number of iteration
5) Take a source byte in AX
6) Move it to destination
7) Increment source pointer
8) Increment destination pointer
9) Decrement counter by 1
10) Continue if count is not 0
11) Stop if the count is 0
FLOWCHART
START

Initialisation of segment register, counters and pointer

Move a byte from from source to destination

Update pointer,decrement counter

NO
Counter=0
?
yes

STOP

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Snap shot of the Code:

Snap shot of the Input:

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 Lakshmi Narain College of Technology Excellence, Bhopal

Department of Computer Science and Engineering

CS-404 Computer Org. & Architecture

Student Sign:…………………………… Teacher’s Sign:………………………

 Lakshmi Narain College of Technology Excellence, Bhopal

Department of Computer Science and Engineering

CS-404 Computer Org. & Architecture

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 Lakshmi Narain College of Technology Excellence, Bhopal

Department of Computer Science and Engineering

CS-404 Computer Org. & Architecture

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 Lakshmi Narain College of Technology Excellence, Bhopal

Department of Computer Science and Engineering

Snap shot of the Result:

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 Lakshmi Narain College of Technology Excellence, Bhopal

Department of Computer Science and Engineering

OBSERVATION TABLE:-

S.No Memory Hex Code Mnemonics Comments/Flags

Location
1 0B27:0100 B80070 MOV NV UP EI PL NZ NA
PO NC
AX,7000
2 0B27:0103 8ED8 MOV DS,AX NV UP EI PL NZ NA
PO NC
3 0B27:0105 BE0002 MOV SI,0200 NV UP EI PL NZ NA
PO NC
4 0B27:0108 BF0003 MOV NV UP EI PL NZ NA
PO NC
DI,0300
5 0B27:010B B90500 MOV CX,05 NV UP EI PL NZ NA
PO NC
6 0B27:010E 8B04 MOV NV UP EI PL NZ NA
PO NC
AX,[SI]
7 0B27:0110 8905 MOV NV UP EI PL NZ NA
PO NC
[DI],AX
8 0B27:0112 46 INC SI NV UP EI PL NZ NA
PO NC
9 0B27:0113 47 INC DI NV UP EI PL NZ NA
PO NC
10 0B27:0114 49 DEC CX NV UP EI PL NZ NA
PO NC
11 0B27:0115 75F7 JNZ NV UP EI PL NZ NA
PO NC
0B27:010E
12 0B27:0117 F4 HLT NV UP EI PL ZR NA
PE NC

Conclusion:
Hence the program was successfully executed.

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