Department of Electronics and Telecommunication Engineering

International Institute of Information Technology Bhubaneswar

Bhubaneswar-751003, Odisha, India.

Supervisor's Certificate

This is to certify that the work in the report enitled Implementation of Sobel Edge
Detection Algorithm using Xlinx Vivado" by Ankush Kumar Nigam (B220009), Sumit
Kumar (B220062) and Aman Avinash Pradhan (B320006) is a record of an original
project work carried out by them under my supervision and guidance in partial
fulfillment of the requirements for the award of the degree of Bachelor of Technology in
Electronics and Telecommunication Engineering. Neither this report nor any part of it has
been submitted for any degree or academic award elsewhere.

Date:
Place: Bhubaneswar

Dr. PradyùtKumar Biswal

Professor
Department of Electronics and Telecommunication Engineering
Intenational lustiute of lntormation Techuology Bhubaneswar
Bhubaneswar, Odisha, India
 Department of Electronics and Telccommunication Engincering
InternationalInstitute of Information Technology Bhubaneswar
eee Bhubaneswar-751003, Odisha, India.

Certificate of Examination

Roll B220009, B2200062, B320006

Name: Ankush Kumar Nigam, Sumit Kumar, Aman Avinash Pradhan

Title of Report : Implementation of Sobel Edge Detection Algorithm using Xilinx Vivado

We the below signed, after checking the report mentioned above and the official record
book(s) of the student(s), hereby state our approval of the report submitted in partial
fulfillment of the requirements of the degree of Bachelor of Technology in Electronics
and Telecommunication Engineering at International Institute of Information Technology.
Bhubaneswar. We are satisfied with the volume, quality, correctness, and originality of
the work.

olos2024

Dr. Pradyut Kumar Biswal Dr. Sanjeev Kumar Mishra

Project Supervisor Project Coordinator

24

20
0s

Dr. Rajat Kumar Giri

HoD Electronics & Telecommunication
 Departmcnt of Electronics and Telecommunication Engincering
International Institute of Information Technology Bhubaneswar
Bhubaneswar-751003, Odisha, India.

Declaration of Originality
We, Ankush Kumar Nigam (B220009), Sumit Kumar (B220062), and Aman Avinash Pradhan
(B320006), hereby declare that this report entitled "Implementation of Sobel Edge
Detection Algorithm using Xilinx Vivado", present Our original work carried out as
bachelor student(s) of International Institute of Information Technology, Bhubaneswar, and
to the best of our knowledge, contains no material previously published or written by
another person, nor any material presented by us for the award of any degree or diploma
of International Institute of Information Technology, Bhubaneswar or any other institution. Any
contribution made to this work by others, with whom we have worked at International
Institute of Information Technology, Bhubaneswar or elsewhere, is explicitly acknowledged in
the report. Works of other authors cited in this dissertation have been duly acknowledged
under the sections "Reference" or "Bibliography. We have also submitted our original work
records to the scrutiny committee for evaluation of our report.
We are fully aware that in case of any non-compliance detected in future, the
Senate of International Institute of Information Technology, Bhubaneswar may withdraw the
degree(s) awarded to us on the basis of the present dissertation.
Date:
Place: Bhubaneswar

Ankah Nign
Ankush Kumar Nigam Sumit Kumar Aman Avinash Pradhan
(B220009) (B220062) (B320006)

Department of Electronics and Telecommunication Engineering

International Instiute of Iformation Technology Bhubaneswar, Odisha, India
V
 Acknowledgement
We have made cfforts towards the accomplishment of this project. However, from the beginning
till the end. this project has advanced from the contributions and suggestions of numerous
people. We would like to extend our gratitude to everyone who has contributed, directly or
indirectly, towards the compilation of this project.

First and foremost, we would like to thank Prof. Dr. Ashish Ghosh, Director, IIT Bhubaneswar
and the Department of Electronics and Telecommunication Engineering, IIT Bhubaneswar for
providing us with allthe necessary infrastructure and resources for completion of this project.
We express our profound sense of gratitude and obligation to our project supervisor and guide
Dr. Pradyut Kumar Biswal for his valuable guidance, stimulating suggestions, expertise and
dedicated supervision, which helped us in accomplishing our project and compiling our work
into this report.

We are also grateful to all the professors of Electronics & Telecommunication Department, IIT
Bhubaneswar for their active guidance and support. Their contributions have greatly enhanced
the quality and depth of our work.
gave timely
Last but not least, many thanks go to co-scholars of IIT Bhubaneswar who
was indeed a
suggestions and helped in the implementation of the project. Working with them
for their constant
pleasure. We are deeply indebted to our family, friends and well-wishers
Their belief in
ençouragement, understanding, and unwavering support throughout this journey.
us has been our driving force.

Aoahialen
Sumit Kumar Aman Avinash Pradhan
Ankush Kumar Nigam
(B220062) (B320006)
(B220009)
 Chapter 1

Introduction
An Overview of Image Processing
Fundamental Steps in Image Processing
Edge Detection & Techniques
Literature Review
Motivation & Objectives

1
Chapter 1: Introduction
1.1 An Overview of Image Processing
An image is a two-dimensional representation of visual information, usually recorded as
a grid of picture elements or pixels. Pixel values store information such as color
intensity (for color pictures) or grayscale intensity (for grayscale images), which
determines how the image appears on a screen or when printed.

In terms of x and y coordinates, an image is a two-dimensional array of pixel values,

with each pixel uniquely recognized by its position in the x-y coordinate system. The x
and y coordinates describe the spatial position of each pixel in the image. Each pixel in
the image is assigned a unique x and y coordinate, allowing it to be represented as a grid
or matrix of pixel values. The coordinate system's origin is commonly located in the
image's upper left corner, with the x-axis extending horizontally to the right and the
y-axis extending vertically downward. By addressing the pixels in an image using their x
and y coordinates, image processing algorithms can access and manipulate individual
pixels or regions of the image to perform tasks such as filtering, enhancement,
segmentation, or feature extraction.

Image processing refers to the manipulation and analysis of digital images using
computational algorithms. It involves transforming or enhancing images to extract
meaningful information or to improve their visual quality.

Image processing techniques can range from simple operations like resizing and
sharpening to more complex tasks such as pattern recognition, object detection, and
image segmentation.

These techniques find applications in various fields including medical imaging, remote
sensing, robotics, surveillance, and digital media.

2
1.2 Fundamental Steps in Image Processing
Image processing consists of numerous important steps: acquisition, preprocessing,
segmentation, feature extraction, representation, analysis, enhancement, restoration,
compression, and comprehension. Images are captured and then processed to improve
quality, segment objects, extract characteristics, assess information, and compress them
for storage or transmission. Noise reduction, object recognition, and picture
compression are used repeatedly to produce the required results, allowing for activities
such as medical diagnosis, surveillance, and multimedia communication.

The fundamental steps of image processing typically include:

a) Image Acquisition: Obtaining a digital image from a physical source, such as a

camera, scanner, or satellite sensor.
b) Preprocessing: This step involves cleaning up and preparing the image for further
analysis. It may include operations like noise reduction, contrast enhancement, and
color correction.
c) Image Enhancement: Enhancing the quality or improving the visual appearance of
the image. This could involve techniques like sharpening, smoothing, or adjusting
brightness and contrast.
d) Image Restoration: Restoring the image to its original form , free of any blurs and
noise.
e) Image Processing: This step includes processing the image using algorithms. These
are generally of 4 types: Colour image processing, Morphological Image
Processing, Compression based image processing, Wavelet based processing.
f) Image Segmentation: Partitioning the image into meaningful regions or segments
based on certain criteria, such as color, intensity, or texture. Segmentation is often a
precursor to object detection and recognition.
g) Feature Extraction: Identifying and extracting relevant features or patterns from the
image data. These features could include edges, corners, textures, or other
characteristics useful for subsequent analysis.

3
 h) Image Representation and Description: Representing the image and its features in a
suitable form for further processing or analysis. This could involve techniques like
histograms, feature vectors, or descriptors.
i) Image Analysis: Analyzing the image content to extract useful information or make
decisions. This may involve tasks such as object detection, classification, or
recognition.
j) Image Interpretation: Interpreting the results of the analysis in the context of the
application domain. This step often involves human judgment or domain-specific
knowledge to understand the significance of the processed image data.

These steps are often iterative, and the specific techniques and algorithms used can vary
depending on the goals of the image processing task and the characteristics of the
images being analyzed.

1.3 Edge Detection

An edge refers to an area or region where the image intensity changes rapidly or
abruptly within an image. Edges are specifically rapid variations in intensity values of
pixels in an image, which highlights the boundary of an entity present inside the image.
Edges may appear in images due to a variety of reasons, including changes in surface
orientation, reflectance, texture, lighting conditions, and obstruction or shadows. When
a surface rapidly changes, such as at the boundary of two items or along an object's
outlines or its contour, it causes a discontinuity in intensity, resulting in the formation of
an edge.

Edge detection methods play an important role in recognizing and localizing these
boundaries, allowing various applications across various fields, including object
detection, feature extraction, gesture detection, medical imaging and so on. There are
several edge detection techniques, such as Sobel, Canny, Prewitt, Robert,
Marr-Hildreth, Sobel-Feldman etc.

Edge detection using FPGA makes use of the parallel processing and reconfigurability
of FPGAs to efficiently implement edge detection techniques. Sobel, Prewitt, and

4
 Canny algorithms are encoded in hardware with HDLs. This method facilitates
real-time processing, high throughput, and scalability, making it ideal for applications
in fields involving automation and medical imaging.

FPGA-based systems maximize resource efficiency by lowering power consumptions

while retaining excellent performance. Overall, FPGA-based edge detection is a fast,
customizable, and an efficient way to achieve a variety of image processing objectives.

1.4 Edge Detection Techniques

Edge detection methods are essential in image processing because they recognize and
locate boundaries inside images. These borders, or edges, show major changes in
intensity or color and are critical for several tasks, including object detection,
segmentation, and feature extraction. Here are some generally used edge detection
algorithms:

i. Sobel Edge Detection- It is a popular edge detection technique that computes the
gradient of picture intensity via convolution with a pair of 3x3 kernels. These
kernels approximate the image's horizontal and vertical derivatives, highlighting
edges based on intensity variations in these directions.
● Advantages: The Sobel operator is computationally efficient as it involves simple
convolution operations, making it faster to compute, compared to more complex
algorithms like Canny edge detector.
● Disadvantages: Sobel has high susceptibility to noise and may produce edge
artifacts or false edges in noisy images due to its sensitivity to variations in pixel
intensity.

ii. Prewitt Edge Detection- Similar to the Sobel operator, It detects edges by
convolving the image with a set of 3x3 kernels and computing the gradient of image
intensity in both horizontal and vertical directions.
● Advantages: Similar to Sobel but with slightly different kernel weights. It's
computationally simpler.

5
 ● Disadvantages: May produce thicker edges compared to Sobel due to less precise
gradient estimation.

iii. Canny Edge Detection- It is a multi-stage algorithm designed to detect many edges
while minimizing false positives. It entails smoothing the image with a Gaussian
filter, determining the gradient magnitude and direction, applying non-maximum
suppression, and edge tracking using hysteresis thresholding.
● Advantages: Superior in noise reduction and localization of edges. It performs
edge thinning to accurately detect edges.
● Disadvantages: Computationally more expensive compared to Sobel due to
additional steps like edge tracing and hysteresis thresholding.

iv. Laplacian of Gaussian Edge Detection- Here, edge detection is achieved by

combining Gaussian smoothing with the Laplacian operator. It uses Gaussian
smoothing to minimize noise in the picture before computing the Laplacian to
emphasize areas of fast intensity shift.
● Advantages: Detects edges based on both gradient and intensity changes, which
can capture finer details.
● Disadvantages: More sensitive to noise compared to Sobel. Requires tuning of
parameters like Gaussian kernel size and threshold.

v. Marr-Hildreth Edge Detection- It combines Gaussian smoothing with the

Laplacian operator to detect edges. It detects edges by identifying zero-crossings in
the Laplacian of the smoothed image.
● Advantages: Effective in detecting edges at multiple scales using Gaussian
smoothing and Laplacian filtering.
● Disadvantages: Computationally intensive due to the need for multiple
convolutions and parameter tuning.

Sobel edge detector is a widely used algorithm for edge detection, offering a balance
between simplicity and effectiveness. While it efficiently detects edges by computing
gradients, it may lack the precision of more complex methods like Canny edge detector.
Compared to Prewitt and Robert's Cross, Sobel provides better edge localization.

6
 However, it's less robust to noise compared to algorithms like Laplacian of Gaussian.
Overall, Sobel is favored for its computational efficiency and satisfactory edge
detection performance in many real-time applications.

1.5 Literature Review

Edge detection methods are essential in image processing because they recognize and
locate boundaries inside images. These borders, or edges, show major changes in
intensity or color and are critical for several tasks, including object detection,
segmentation, and feature extraction.

Pranjal Sharma's Paper, "Design and Verification of Generic FIFO using Layered Test
bench and Assertion Technique"(2022) [1] outlines a research process focused on
developing and verifying a FIFO (First-In, First-Out) design using Verilog. The aim is
to ensure a high-quality product at a low cost by employing verification techniques such
as layered test benches and assertion methods. Key parameters of the FIFO design
include full, empty, last, and second last first. The verification process utilizes layered
test benches and assertion techniques to detect bugs effectively. The complexity of the
design lies in determining read data and managing system aspects through positive and
negative edge transitions.

“Implementation of an RTL synthesizable asynchronous FIFO for conveying data by

avoiding actual data movement via FIFO” [2] by Shruti Sharma in 2015 presents an
innovative approach to integrating asynchronous design principles into synchronous
flow design, offering solutions to critical timing issues and power consumption control.
By leveraging Verilog models and asynchronous features, the study demonstrates
improved performance and efficiency in FIFO structures.

Lam, S. K., Jiang, G., Wu, M., & Cao, B. (2019), [3] Area time efficient streaming
architecture for FAST and BRIEF detectors presents an innovative approach to
FAST-BRIEF feature detection, focusing on optimizing architecture for reduced
complexity and improved performance. By leveraging optimized adder trees and
efficient sampling schemes, the proposed architecture demonstrates superior efficiency

7
and throughput compared to baseline designs, making it a promising solution for
real-time image processing applications.

“A FPGA based Implementation of Sobel Edge Detection” (2017) [4] by Nazma

Nausheen, Ayan Seal, Pritee Khanna, Santanu Haldar presents an architecture tailored
for Sobel edge detection on FPGA boards, emphasizing computational efficiency and
robustness against noise. Through a comparative study, the proposed architecture
demonstrates superior performance in terms of reduced logic gate count and space
complexity

N. Shylashree's paper, "Design and Implementation of Image Edge Detection

Algorithm on FPGA"(2021) [5] presents a novel hybrid edge recognition method
designed to mitigate the computational complexity associated with traditional edge
detection algorithms. By leveraging hardware optimizations and innovative techniques,
the proposed method demonstrates enhanced performance and efficiency

Dr. R. Meneka, Dr. R. Janarthan, & Dr. K. Deeba (2020), “FPGA implementation of
low power and high-speed image edge detection algorithm”, [6] presents an
FPGA-based architecture for efficient Sobel edge detection. The authors propose an
8-bit architecture that optimizes the retrieval of pixel addresses for the convolution
process, reducing time and space complexity compared to previous designs. The
architecture utilizes direct indexing of pixels, eliminating redundant storage, and
operates at a high frequency, significantly decreasing image processing time.

“An Improved Sobel Edge Algorithm and FPGA Implementation” by Kun Zhang et al.
(2018),[7] identifies the limitations of the classic Sobel algorithm, particularly its slow
processing speed and less accurate edge detection in complex images due to the use of
smaller gradient templates and time-consuming multiplication operations. To address
these issues, the authors propose an improved Sobel edge detection algorithm that
increases the gradient template to include additional directions (45° and 135°), which
allows for more accurate edge detection. The improved algorithm also changes the
gradient calculation method to avoid direct multiplication, thus enhancing speed and
accuracy.

8
Table 1.1 : Literature Review

Literature Review Title Technical Learning

"Design and Verification of Development and verification of a FIFO design

Generic FIFO using Layered using Verilog, employing verification techniques
Test bench and Assertion such as layered test benches and assertion methods.
Technique" Key parameters include full, empty, last, and second
(Pranjal Sharma, 2022) [1] last first. Utilizes layered test benches and assertion
techniques for bug detection, managing read data,
and system aspects through positive and negative
edge transitions.

"Implementation of an RTL Integrating asynchronous design principles into

synthesizable asynchronous synchronous flow design, addressing critical timing
FIFO for conveying data by issues and power consumption control in FIFO
avoiding actual data structures. Leveraging Verilog models and
movement via FIFO" asynchronous features for improved performance
(Shruti Sharma, 2015)[2] and efficiency.

"Area time efficient Optimization of architecture for FAST-BRIEF

streaming architecture for feature detection,
FAST and BRIEF detectors" focusing on reduced complexity and improved
(Lam, S. K., Jiang, G., Wu, performance. Utilizes optimized adder trees and
M., & Cao, B., 2019) [3] efficient sampling schemes for superior efficiency
and throughput in real-time image processing
applications.

"A FPGA based Tailored architecture for Sobel edge detection on

Implementation of Sobel FPGA boards, emphasizing computational
Edge Detection" efficiency and robustness against noise.
(Nazma Nausheen, Ayan Superior performance demonstrated through
Seal, Pritee Khanna, Santanu reduced logic gate count and space complexity,
Haldar, 2017) [4] suitable for real-world image processing
applications.

"Design and Implementation Hybrid edge recognition method to mitigate

of Image Edge Detection computational complexity in traditional edge
Algorithm on FPGA" detection algorithms. Utilizes hardware
(N. Shylashree, 2021) [5] optimizations and innovative techniques for
enhanced performance and efficiency in real-time
image processing applications.

9
 Literature Review Title Technical Learning

"FPGA implementation of FPGA-based architecture for efficient Sobel edge

low power and high-speed detection, optimizing retrieval of pixel addresses
image edge detection and reducing time and space complexity. Utilizes
algorithm" direct indexing of pixels, eliminating redundant
(Dr. R. Meneka, Dr. R. storage, and operates at a high frequency for
Janarthan, & Dr. K. Deeba, decreased image processing time.
2020) [6]

"An Improved Sobel Edge Addressing limitations of classic Sobel algorithm,

Algorithm and FPGA proposing an improved algorithm for more accurate
Implementation" edge detection in complex images. Increased
(Kun Zhang et al., 2018) gradient template directions (45° and 135°) enhance
[7] accuracy, while changing gradient calculation
method
improves speed by avoiding direct multiplication.

1.6 Motivation and Objectives

The development of edge detection utilizing FPGA (Field Programmable Gate Array)
technology has been motivated by FPGAs' unique ability to improve the efficiency and
performance of edge detection algorithms. FPGAs provide parallel processing, allowing
processes to be executed concurrently for computationally complex applications such as
edge detection. They provide real-time computing, fulfilling tight timing constraints in
applications like driverless cars and surveillance systems. FPGA-based edge detection
algorithms may be customized and optimized to meet unique application requirements,
which results in improved resource economy and performance. FPGAs provide high
throughput, low latency, and scalability, making them ideal for processing huge
amounts of picture data effectively. Some of the objectives behind implementation of
edge detection using FPGA are listed below:

● Parallel Processing: FPGAs are fundamentally parallel devices made up of a large

number of programmable logic blocks coupled by adjustable routing resources. This
parallel design allows for the simultaneous execution of numerous operations,

10
 making FPGAs ideal for computationally heavy applications such as edge detection,
which requires convolutions and filtering operations on big picture datasets.

● Real-Time Processing: Edge detection frequently requires image processing in real

time, particularly in applications such as autonomous cars, robots, and surveillance
systems. FPGAs have high-speed processing capabilities, enabling edge detection
algorithms to be implemented in real-time or near real-time, fulfilling the rigorous
timing requirements of these applications.

● Customization and Optimization: FPGAs provide for an excellent level of

customization and versatility in hardware design. Edge detection methods may be
enhanced and adapted to specific application needs by incorporating dedicated
hardware accelerators into the FPGA. This level of customization enables optimal
resource use and performance optimization, resulting in quicker and more effective
edge detection.

● Resource Efficiency: FPGA-based edge detection techniques are more resource

efficient than software-based equivalents on conventional CPUs. FPGAs can conduct
edge detection with lower power consumption and a smaller hardware layout due to
dedicated hardware resources and parallel processing, making them ideal for
embedded systems and portable devices.

● High Throughput: FPGAs provide high throughput and low latency, allowing edge
detection algorithms to analyze enormous amounts of visual data quickly. This high
throughput is especially useful in applications that need quick processing of picture
streams, such as medical imaging, industrial inspection, and video surveillance.

● Scalability: FPGAs provide scalability of processing resources and performance.

Complex edge detection algorithms may be implemented on FPGAs with more
logic resources and faster clock rates, allowing for greater scalability to meet the
needs of changing applications and bigger image datasets.

Overall, the development of edge detection using FPGA technology offers significant
advantages in terms of parallel processing, real-time performance, customization,

11
resource efficiency, high throughput, and scalability. These advantages make
FPGA-based edge detection systems well-suited for a wide range of applications in
computer vision, image processing, and embedded systems.

12
 Chapter 2

FPGA for
Sobel Edge Detection

An Overview of FPGA
Introduction to Verilog
Sobel Edge Detection Technique
Overview on Sobel Edge Detection algorithm’s FPGA Implementation

13
Chapter 2 :
Sobel Edge Detection Algorithm
2.1 An Overview of FPGA
VLSI (Very Large Scale Integration) is the method of designing integrated circuits (ICs)
by merging millions of transistors on a single chip. It includes the design,
manufacturing, and testing of these sophisticated semiconductor devices. VLSI
technology enables the design of modern electronic systems with high performance, low
power consumption, and minuscule form factors.

VLSI is used in a variety of applications, including designing of microprocessors,

memory chips, digital signal processors, and application-specific integrated circuits.

A FPGA (Field Programmable Gate Array ) is a type of programmable logic device

(PLD) that includes an array of configurable logic blocks (CLBs), programmable
interconnects, and other specialized hardware resources. FPGAs may be programmed
and reconfigured to implement a variety of digital circuits and systems, such as logic
gates, arithmetic units, memory blocks, and advanced digital signal processing (DSP)
systems. Unlike ASICs, FPGAs provide flexibility and rapid prototyping capabilities,
allowing designers to iterate on ideas more rapidly and easily.

FPGAs are widely employed in a variety of applications, including embedded systems,

telecommunications, automotive, aerospace, and high-performance computing.

They are programmed using hardware description languages like Verilog or VHDL and
configured using specialized development tools provided by various FPGA
manufacturers such as Xilinx, Intel (formerly Altera), and Lattice Semiconductor.

14
 Figure 2.1 : Block Diagram of ZYNQ 7000 SoC [10]

2.2 Introduction to Verilog

Verilog is a hardware description language (HDL) for designing and simulating digital
systems. It is commonly used for the design and verification of digital circuits and
systems, such as VLSI circuits, FPGAs, and ASICs. Verilog enables designers to
describe the behavior and construction of digital circuits in a simple and expressive
manner. It facilitates both behavioral and structural modeling.

Here are some insights on Verilog:

1. Behavioral Modeling: Using structures like tasks, functions, and procedural

blocks, Verilog enables designers to characterize the behavior of digital circuits.

15
 With behavioral modeling, the intended circuit functioning may be simulated
without revealing the underlying structure.
2. Structural Modeling: Verilog facilitates structural modeling, in which digital
circuits are represented as a network of interconnected modules. Designs that
are hierarchical can be produced by instantiating and connecting modules. This
method makes it possible to construct complicated systems in a modular fashion
and reuse individual components.
3. Data Types: To describe digital signals and variables, Verilog offers a variety of
data types, such as scalar (bit, reg), vector (wire, logic), and user-defined (e.g.:
“enum”, “struct”). It is possible to express various bit widths and signal
characteristics using these data types.
4. Language Features: Verilog has a variety of language features, such as looping
constructs (for, while), conditional statements (if, case), procedural blocks
(always, initial), and system tasks/functions (e.g., $display, $random).
5. Concurrent Execution: Multiple statements inside a module are performed
concurrently since Verilog is a concurrent language by nature. So, Verilog may
be used to simulate hardware behavior in scenarios where several events might
happen at once. This enables for the parallel execution of operations.
6. Simulation & Synthesis: Verilog is a tool that may be used for both synthesis
and simulation. Using software-based simulations, simulation enables designers
to confirm the functionality of their ideas, whereas synthesis turns the Verilog
description into a netlist of hardware parts that can be implemented on an FPGA
or ASIC.
7. Testbench Development: Digital circuit behavior is simulated and accuracy is
confirmed using Verilog testbenches. Testbenches, which are written in Verilog,
stimulate the design under test (DUT) and check the outputs for accuracy.
8. Verification: Assertion-based verification is supported by Verilog, allowing
designers the ability to define attributes and restrictions that need to stay true
during simulation. Assertions support early error detection in the design process
and help guarantee the accuracy of the design.

16
 All things considered, Verilog is an effective language for digital system modeling and
design that provides a wide range of capabilities for structural and behavioral
description, simulation, synthesis, and verification.

2.3 Sobel Edge Detection Technique

In image processing and computer vision, the Sobel operator, also known as the Sobel
filter, is utilized in edge detection algorithms to emphasize edges in the picture. The
Stanford Artificial Intelligence Laboratory (SAIL) colleagues Irwin Sobel and Gary M.
Feldman are honored in the name of the system. During a 1968 discussion at SAIL,
Sobel and Feldman introduced the concept of an "Isotropic 3 × 3 Image Gradient
Operator".

Edges in images can be detected using specific techniques, one of which involves
convolving the image with a kernel to extract edge information in a particular direction
or angle. The Sobel operator is a commonly used technique, which is applied in two
directions: horizontal (x) and vertical (y). This method involves taking the first-order
derivative with respect to x and y to capture edge details. While Sobel is typically
performed in two directions, it can also be implemented in multiple directions, ranging
from two to eight directions, as demonstrated in this project. The kernels GX and GY

correspond to the horizontal and vertical directions, respectively, with GY being the

transpose of GX. While Sobel edge detection is commonly applied to grayscale images,
it can also be implemented on color images. However, doing so increases complexity
and may lead to inefficiency.

2.3.a Mathematical Background of Sobel Edge Detection

The Sobel filter employs two 3x3 kernels to detect edges in images. One kernel
emphasizes horizontal edges, while the other highlights vertical edges. The kernels are
the Horizontal Mask (HM) and Vertical Mask (VM), as shown below.

17
By convolving the 3x3 subwindow of image I with these kernels, denoted as Gx and Gy,
the filter computes approximations of edges in the horizontal and vertical directions,
respectively,

Where * denotes the 2-dimensional signal processing convolution operation, and I is

the 3x3 sub-window of the image.
It is understood that Sobel kernels can be expressed as the result of multiplying an
averaging kernel with a differential kernel. This enables the computation of gradients
while simultaneously smoothing the image.
The x-coordinate is oriented to increase in the "right" direction, while the y-coordinate
increases in the "down" direction.
At every pixel in the image, the gradient approximations obtained can be merged to
determine the gradient magnitude, according to the following formula:
G = sqrt (( GX )^2 + (GY )^2 )
or
G = | GX | + | GY |
The specific pixel whose gradient is calculated is only treated as an edge when G is
greater than threshold (T) and is denoted by value 1, else it is treated as non-edge pixel
and is denoted by value 0.
The gradient’s direction can also be calculated by:
Θ = arctan2(GY , GX )
Where Θ represents the direction of gradient.
A 3 x 3 subwindow of Image I :

P0 P1 P2

P3 P4 P5

P6 P7 P8

Table 2.1 : 3x3 subwindow of image

18
 Let the above sub-window be convolved with the horizontal and vertical mask
separately. Equations 1 and 2 represent the horizontal gradient Gx and vertical gradient
Gy of the sub-window's center pixel (P4).
Gx = F1 - F2 --- (eq. 1)
where F1 = (P6 + 2 x P7 + P8) & F2 = (P0 + 2 x P1 + P2)
Gy = F3 - F4 --- (eq. 2)
where F3 = (P2 + 2 x P5 + P8) & F4 = (P0 + 2 x P3 + P6)

2.3.b Simplification of Traditional Sobel Edge Detection Algorithm

Due to the usage of an 8-bit architecture for hardware implementation, the typical Sobel
edge detection technique requires minor alterations. In [4], S. Halder et al. simplified the
standard method. S.Halder et al. [4] suggested a simpler method, which has undergone
revisions. Equation 1 states that the greatest values of F1 and F2 occur when each
sub-window's contributing pixels have the highest intensity values (255). The same
applies to F3 and F4 in equation 2. The highest value for F1, F2, F3, and F4 is 4 × 255,
requiring a 10-bit architecture for implementation. To address this issue, the values of
F1, F2, F3, and F4 are set to one-fourth of their original values. To determine the values
of F1, F2, F3, and F4,we divide each contributing pixel by 4 (equations 3–6). Also to
obtain the new equation for G for the 8 bit architecture, we divide both Gx and Gy by 2,
as shown in equation 7.
F1 = (P6 + 2 x P7 + P8) / 4 --- (eq. 3)

F2 = (P0 + 2 x P1 + P2) / 4 --- (eq. 4)

F3 = (P2 + 2 x P5 + P8) / 4 --- (eq. 5)

F4 = (P0 + 2 x P3 + P6) / 4 --- (eq. 6)

G = ½ |Gx | + ½ | Gy | --- (eq. 7)

So, equation 1 & 2 can be re-written as:

Gx = F1 - F2 --- (eq. 8)
where F1 = ⅛ (P6 + 2 x P7 + P8) & F2 = ⅛ (P0 + 2 x P1 + P2)

19
 Gy = F3 - F4 --- (eq. 9)
where F3 = ⅛ (P2 + 2 x P5 + P8) & F4 = ⅛ (P0 + 2 x P3 + P6)

Since we are taking the absolute values of Gx and Gy for calculation G, the following
four cases can be considered.
Case 1: If both Gx and Gy are positive.
G1 = (F1 - F2) + (F3 - F4) = ¼ (P5 + P7 + P8) - ¼ (P0 + P1 + P3) = F5 - F6 --- (eq. 10)

Case 1: If Gx is positive and Gy is negative .

G2 = (F1 - F2) + (F4 - F3) = ¼ (P3 + P6 + P7) - ¼ (P1 + P2 + P5) = F7 - F8 --- (eq.11)

Case 1: If Gx is negative and Gy is positive.

G3 = (F2 - F1) + (F3 - F4) = ¼ (P1 + P2 + P5) - ¼ (P3 + P6 + P7) = F8 - F7 --- (eq. 12)

Case 1: If both Gx and Gy are positive.

G4 = (F2 - F1) + (F4 - F3) = ¼ (P0 + P1 + P3) - ¼ (P5 + P7 + P8) = F6 - F5 --- (eq. 13)

At any given time, one out of the four cases will be true, while the other three will be
false. Assuming case 1, F1 and F3 will be larger than or equal to F2 and F4, respectively.
G1 is the resulting gradient of the center pixel (P4) in the 3 x 3 sub-window of the
image. These four situations are independent of one another. The value of G is the
maximum of four potential values, which is given in equation 14.
G = max(G1, G2, G3, G4) = max(| F5 − F6 |, | F7 − F8 |) = max ( F9 , F10) --- (eq. 14)
Where, F9 is the absolute value of F5 - F6 ; & F10 is the absolute value of F7 - F8.
So, with this simplification an 8-bit architecture can be designed for implementing Sobel
edge detection algorithm on FPGA. To determine an image's edge pixel, do subtraction,
addition, division, absolute value, and comparison as shown above. For subtraction and
addition, an 8-bit adder-subtractor composite block is utilized. Convolution requires
dividing each intensity value by four, which is accomplished effectively using right shift
operators rather than dividers. A 2:1 multiplexer measures the absolute difference
between consecutive intensity levels. To get absolute values, subtraction is performed in
two ways, with the resultant carry bit serving as the multiplexer selector line. After
obtaining the absolute values of F9 and F10, they are compared to a threshold using two
subtractors and a NAND gate rather than a comparator, which simplifies the procedure.

20
 If both absolute values are above the threshold, the pixel is termed an edge pixel.
Otherwise, it's not, according to the NAND gate's truth table.
Thus the modified architecture as described by [4] “A FPGA based Implementation of
Sobel Edge Detection” (2017) by Nazma Nausheen, Ayan Seal, Pritee Khanna, Santanu
Haldar, is shown in the below figure.

Figure 2.2 :Simplified Architecture for Sobel Edge Detector by S. Haldar et al.[4]

2.3.c Flowchart of Sobel Edge Detection Algorithm

This flowchart represents a standard approach to edge detection using the Sobel filter,
commonly used in image processing and computer vision applications.

21
Figure 2.3 : Flowchart for Sobel Edge Detection Algorithm

22
2.3.d Comparison of Sobel edge detection algorithm
Table 2.2 : Comparison between software & hardware implementation of Sobel edge
detection algorithm

Software Hardware
Aspect Implementation Implementation

Typically slower due to Generally faster due to

Performance
sequential execution parallel processing

More flexible, easier to Less flexible, fixed

Flexibility
modify and debug functionality

Low power
Resource High CPU and memory consumption,
Consumption usage optimized for edge
detection

Limited by CPU Scalable, can handle

Scalability performance and higher resolutions and
memory frame rates

Shorter development
Development Longer development
time due to
Time time due to coding
pre-designed circuits

Easily portable across Less portable,

Portability
different platforms hardware-dependent

Lower initial cost for Higher initial cost for

Cost
software development hardware design

Real-time Challenging for Well-suited for

Processing real-time applications real-time applications

Exploits parallelism
Limited parallelism in
Parallelism effectively in dedicated
multi-core processors
hardware

23
2.4 FPGA for Sobel Edge Detection algorithm’s Implementation
Implementing the Sobel Edge Detection algorithm on an FPGA (Field-Programmable
Gate Array) offers significant advantages in terms of speed, efficiency, and flexibility
compared to traditional software implementations on CPUs or GPUs.

● Algorithm Overview: The Sobel Edge Detection algorithm is a popular method

for detecting edges in digital images. It involves convolving the image with a
pair of 3x3 convolution kernels (one for horizontal changes and the other for
vertical changes) to compute the gradient magnitude. The gradient magnitude is
then used to identify regions of significant intensity change, which are
considered as edges.

● Implementation Steps:
1. Hardware Description Language (HDL): The algorithm is typically
implemented using HDL such as Verilog or VHDL, which describe the
behavior of digital circuits. These languages allow designers to specify
the functionality of the FPGA at a low level.
2. Parallelism Exploitation: FPGAs allow parallelism to be exploited
efficiently. Each pixel of the image can be processed concurrently,
leading to significant speedups compared to sequential processing.
3. Memory Access Optimization: FPGAs have on-chip memory resources
that can be utilized to store image data efficiently, reducing the need for
off-chip memory accesses and enhancing performance.
4. Pipeline Optimization: Pipelining can be employed to improve
throughput by breaking down the computation into stages and
overlapping them. This reduces the overall latency of the algorithm.

● Resource Utilization: FPGAs offer a variety of resources such as Look-Up

Tables (LUTs), Block RAMs (BRAMs), and Digital Signal Processing (DSP)
slices. The Sobel Edge Detection algorithm requires relatively few resources
compared to more complex algorithms, making it well-suited for
implementation on FPGAs with modest resource constraints.

24
 ● Integration with Image Processing Pipeline: FPGAs can be integrated into
image processing pipelines alongside other processing elements such as
cameras, sensors, or even CPUs/GPUs. Real-time processing can be achieved by
streaming image data directly into the FPGA, processing it in real-time, and
streaming the results out.
● Performance Evaluation: Performance of the FPGA implementation can be
evaluated in terms of throughput (frames per second), latency (time taken to
process each frame), and resource utilization. Compared to software
implementations on CPUs or GPUs, FPGA implementations often offer superior
performance in terms of speed and efficiency
● Development Tools: FPGA development tools such as Xilinx Vivado provide
the necessary software environment for designing, simulating, synthesizing, and
deploying FPGA designs offer superior performance in terms of speed and
efficiency, especially for real-time applications.

Implementing the Sobel Edge Detection technique on an FPGA improves speed,

economy, and flexibility over typical CPU or GPU implementations. The approach
convolves the picture using 3x3 kernels to calculate gradient magnitude for edge
detection. Designers use HDL, such as Verilog/VHDL, to describe FPGA functionality,
leveraging parallelism for concurrent pixel processing and optimizing memory access
and pipelining for performance. FPGAs provide resources such as LUTs, BRAMs, and
DSP slices, which are appropriate for Sobel's limited resource requirements.
Integration with image processing pipelines provides real-time processing, as
measured by throughput, latency, and resource utilization.

2.5 Conclusion
In this chapter, we explored the Sobel edge detection algorithm and its FPGA
implementation using Xilinx Vivado. We detailed the Sobel operator's mathematical
foundations and practical application in edge detection, including image conversion to
grayscale and hex formats for FPGA processing. The implementation overview
covered the simplification of the Sobel algorithm for an 8-bit architecture, optimizing
it for FPGA hardware. We highlighted the benefits of FPGA implementation, such as

25
enhanced performance, scalability, and real-time processing capabilities. Overall, the
chapter provides a concise roadmap for leveraging FPGA power to achieve efficient
and robust edge detection in digital images.

26
 Chapter 3

Architecture for
Sobel Edge Detector

An Overview of Xilinx Vivado

Architecture for Sobel Edge Detector

27
Chapter 3 :
Architecture for Sobel Edge Detector

3.1 An Overview of Xilinx Vivado

Xilinx Vivado is a complete software package for designing FPGAs and SoCs. It
supports a variety of design entry techniques, including schematic capture, HDLs, and
high-level abstraction tools. The synthesis tool optimizes RTL designs for the target
FPGA, while the implementation tools manage placement and routing, ensuring that
FPGA resources are used efficiently. time analysis tools ensure that the design satisfies
time restrictions. Vivado also includes powerful debugging and verification tools, such
as IP Integrator for IP block integration and High-Level Synthesis for
C/C++/SystemC-based hardware design. Power analysis tools assist monitor power
usage, and the suite is compatible with a wide range of Xilinx devices. Vivado interfaces
with other tools in the Xilinx ecosystem to provide a unified development environment.

3.2 Architecture for Sobel Edge Detector:

The architecture is designed using Xilinx Vivado and is based on the ZYNQ-7 ZC702
Evaluation Board, to take a 256x256 pixels resolution image’s HEX file as input and
detect the edges of various entities in the image by implementing Sobel edge detection
algorithm, and generate the HEX file of edge-detected output image. The input image’s
HEX file is generated and the output image’s HEX file is visualized using a
user-designed MATLAB GUI application.

The architecture begins with the design of the block memory submodule , which
corresponds to the available BRAM on the FPGA board. Then design of the file
reading submodule is done which reads the input image’s Hex file data stored on the
local computer storage and generates the address, data, and write enable signals to
write the data into the designed block memory submodule . After this the 3x3 line

28
 buffer submodule is designed consisting of the controller unit and three FIFO storages
to read the input image’s pixel data from the block memory. Then the Sobel edge
detector submodule is designed which consists of 1-bit & 2-bit shifters, half adders,
full-adders, 8-bit ripple carry adders, half subtractors, full-subtractors, 8-bit ripple
borrow subtractors, 2:1 Multiplexers. The Sobel edge detector submodule takes input
data as read by the line buffer submodule and processes the pixel data to give the
edge-data as output. Then we design the Data Flip-Flops which take the edge data and
give it to the designed output image recorder submodule, which in turn stores the
output data of the edge-detected image into the block memory submodule. Then the
file writing sub-module is designed, which writes the data of the edge-detected image
stored in the block memory submodule to a file on the local computer.

3.2.a Sub-Modules:

3.2.a.1 Block Memory:

This submodule stores the input image’s HEX file data read from the local computer for
simulation, and the processed or edge-detected output image data during the duration of
simulation. This module consists of the Xilinx LogiCORE Block Memory Generator IP.
This module corresponds to the memory unit present on the FPGA board.

Figure 3.1 : Block Memory

29
 Input Pins:
● clk : Clock signal (a single bit).
● wr_enb : Write enable signal (a single bit).
● rd_addr[15:0] : Address bus to point at an address while data is read (16 bits).
● wr_addr[15:0] : Address bus to point at an address while data is written (16 bits).
● wr_data[7:0] : Data bus to write data into block memory, as per the address
pointed by the wr_addr address bus (8 bits).
Output Pins:
● rd_data[7:0] : Data bus to read out data from block memory (8 bits).

3.2.a.2 File Reader:

This submodule is designed to read the input image’s HEX file data from the local
computer and store it into the designed Block memory submodule. It consists of
numerous registers, multiplexers, and other logic modules for reading the data from the
HEX file.

Figure 3.2 : File Reader

Input Pins:
● clk : Clock signal (a single bit).

30
 ● reset : Reset signal (a single bit).
Output Pins:
● img_wr_enb : Write enable signal (a single bit).
● start : Start signal (a single bit).
● img_write_addr[15:0] : Address bus to point at an address while image data is
written (16 bits).
● img_write_data[7:0] : Data bus to write image data into block memory, as per
the address pointed by the img_write_addr address
bus when the img_wr_enb signal is high (8 bits).

3.2.a.3 Sobel Edge Detector Machine:

This submodule is designed to implement the Sobel edge detection algorithm after
reading the pixel data from the designed block memory using the 3x3 line buffer
sub-module and it gives the edge detected output image as final output to the block
memory via the Data Flip Flop and output image recorder submodules.

.
Figure 3.3 : Sobel Edge Detector Machine

31
 Input Pins:
● clk : Clock signal (a single bit).
● reset : Reset signal (a single bit).
● start : Start signal (a single bit).
● image_data[7:0] : Data bus to input image data from block memory (8 bits).
Output Pins:
● wr_enb : Write enable signal (a single bit).
● done : Done signal (a single bit)
● rd_addr[15:0] : Address bus to point at an address while data is read (16 bits).
● wr_addr[15:0] : Address bus to point at an address while data is written (16 bits).
● wr_data[7:0] : Data bus to write data into block memory (8 bits).
3.2.a.3.i Line buffer:
This submodule consisting of 3 FIFOs and an Image controller is used to input pixel
values of input image from the block memory. FIFOs manage data flow, ensuring
seamless input and output transitions.

Figure 3.4 : 3 x 3 Line Buffer

32
 Input Pins:
● clk : Clock signal (a single bit).
● reset : Reset signal (a single bit).
● start : Start signal (a single bit).
● image_data[7:0]: Data bus to input image data from block memory(8 bits).

Output Pins:
● hysnc : Sync signal for horizontal position of pixel(a single bit).
● vsync : Sync signal for vertical position of pixel(a single bit).
● px_enb : Pixel write enable signal (a single bit).
● pixel_data1[7:0]: Data bus to read-out pixel data from line buffer (8 bits).
● pixel_data2[7:0]: Data bus to read-out pixel data from line buffer (8 bits).
● pixel_data3[7:0]: Data bus to read-out pixel data from line buffer (8 bits).
● rd_addr[15:0]: Address bus pointing at address while data is read (16 bits).

3.2.a.3.ii Image Controller:

This submodule consisting of multiplexers, registers, and various logic submodules

orchestrates operations, synchronizing data movement and processing stages. Its
main purpose is to segregate the concatenated pixel data captured by the FIFOs and
give out the nine individual pixels from 3x3 subwindow of input image at a time.

Figure 3.5 : Image Controller

33
 Input Pins:
● clk : Clock signal (a single bit).
● reset : Reset signal (a single bit).
● hysnc : Sync signal for horizontal position of pixel(a single bit).
● px_enb : Pixel read enable signal (a single bit).
● pixel_data1[7:0]: Data bus to read-in pixel data from line buffer (8 bits).
● pixel_data2[7:0]: Data bus to read-in pixel data from line buffer (8 bits).
● pixel_data3[7:0]: Data bus to read-in pixel data from line buffer (8 bits).

Output Pins:
● se_enb : Pixel read-out enable signal (a single bit).
● p0[7:0] : Data bus to read-out pixel data from line buffer (8 bits).
● p1[7:0] : Data bus to read-out pixel data from line buffer (8 bits).
● p2[7:0] : Data bus to read-out pixel data from line buffer (8 bits).
● p3[7:0] : Data bus to read-out pixel data from line buffer (8 bits).
● p4[7:0] : Data bus to read-out pixel data from line buffer (8 bits).
● p5[7:0] : Data bus to read-out pixel data from line buffer (8 bits).
● p6[7:0] : Data bus to read-out pixel data from line buffer (8 bits).
● p7[7:0] : Data bus to read-out pixel data from line buffer (8 bits).
● p8[7:0] : Data bus to read-out pixel data from line buffer (8 bits).

3.2.a.3.iii Sobel Edge Detector:

This submodule is the vital part responsible for performing the convolution and
implementing the sobel edge detection algorithm in the pixel data of the input
image to give out the edge-detection output data.

It consists of half adders, full adders, ripple carry adders, half subtractors, full
subtractors, ripple borrow subtractors, shifters, Multiplexers, which are responsible
to implement the sobel edge detection algorithm.

34
 Figure 3.6 : Sobel Edge Detector

Input Pins:
● Threshold[7:0] : Threshold signal (8 bits).
● p0[7:0] : Data bus to read-out pixel data from line buffer (8 bits).
● p1[7:0] : Data bus to read-out pixel data from line buffer (8 bits).
● p2[7:0] : Data bus to read-out pixel data from line buffer (8 bits).
● p3[7:0] : Data bus to read-out pixel data from line buffer (8 bits).
● p4[7:0] : Data bus to read-out pixel data from line buffer (8 bits).
● p5[7:0] : Data bus to read-out pixel data from line buffer (8 bits).
● p6[7:0] : Data bus to read-out pixel data from line buffer (8 bits).
● p7[7:0] : Data bus to read-out pixel data from line buffer (8 bits).
● p8[7:0] : Data bus to read-out pixel data from line buffer (8 bits).

Output Pins:
● Edge_Data[7:0] : Data bus to read-out edge data (8 bits).

35
3.2.a.3.iv Output Image Recorder:
This submodule is used to record the edge-detected output image’s pixel data, and
readout these to the memory block submodule.

Figure 3.7 : Output Image Recorder

Input Pins:
● clk : Clock signal (a single bit).
● reset : Reset signal (a single bit).
● data_enb : Data read enable signal (a single bit).
● vsync : Sync signal for vertical position of pixel(a single bit).
● image_data[7:0]: Data bus to input edge-detected image pixel data(8 bits).

Output Pins:
● wr_enb : Write enable signal (a single bit).
● done : Done signal (a single bit)
● wr_addr[15:0] : Address bus pointing at address (16 bits).
● wr_data[7:0] : Data bus to write data into block memory (8 bits).

36
3.2.a.4 File Writer:

This submodule is designed to write the edge-detected output image’s HEX file data from
designed Block memory and store it into the local computer. It consists of numerous
registers, multiplexers, and other logic modules for writing the data from the block
memory into the local computer as output images’ HEX file.

Figure 3.8 : File Writer

Input Pins:
● clk : Clock signal (a single bit).
● reset : Reset signal (a single bit).
● done : Done signal (a single bit)
● qpo_rd_data[7:0] : Data bus to read output image data from block memory (8
bits).

Output Pins:
● qpo_rd_addr[15:0] : Address bus to point at an address while writing output
image data (16 bits).

37
3.2.b Overall Architecture:

Figure 3.9 : Overall Architecture of Sobel Edge Detector

3.2.c Schematic of the Architecture:

Figure 3.10 : Schematic of the Architecture for Sobel Edge Detector

38
3.3 Conclusion
In conclusion, the implementation of the Sobel edge detector on an FPGA using Xilinx
Vivado offers a robust and efficient solution for real-time image processing tasks.
Leveraging the capabilities of the ZYNQ-7 ZC702 Evaluation Board, we designed a
comprehensive architecture comprising various submodules such as block memory,
file reader, line buffer, Sobel edge detector, and file writer. Each submodule was
meticulously crafted to optimize resource utilization and processing speed, ensuring
seamless integration and operation. The detailed steps, from reading the input image’s
HEX file to storing the edge-detected output, demonstrate the effectiveness of
FPGA-based systems in handling high-performance image processing applications.
This architecture not only enhances processing speed but also provides scalability and
adaptability for future developments in digital image processing.

39
 Chapter 4

Simulation of
Sobel Edge Detector Architecture
in Xilinx Vivado

Implementation Overview
Workflow and Simulation Procedure
Result Analysis and Discussion

40
Chapter 4 :
Sobel Edge Detection Architecture: Simulation in
Xilinx Vivado

4.1 Implementation Overview

In this chapter, we provide a comprehensive overview of the implementation process of
the Sobel Edge Detector Architecture in Xilinx Vivado. Our journey begins with an
exploration of the architecture's design choices, where we discuss the selection of data
path width, clock frequency, and memory organization to optimize performance and
resource utilization. Subsequently, we delve into the integration of the Sobel edge
detection algorithm, detailing the translation of algorithmic concepts into hardware
description language (HDL) for implementation in Vivado.

Further, we describe the setup of the simulation environment, including the creation of
testbenches and the generation of stimuli to validate the functionality and accuracy of
the architecture. Throughout this chapter, we aim to provide readers with a
comprehensive understanding of the steps involved in realizing the Sobel Edge Detector
Architecture in Xilinx Vivado, laying the foundation for subsequent analysis and
discussion

4.2 Workflow and Simulation Procedure

4.2.1 Introduction:

In this chapter, we outline the workflow and simulation procedure for implementing the
Sobel edge detection architecture in Xilinx Vivado. The process involves several steps,
including image preprocessing, simulation setup, and execution. By following this
workflow, we ensure the efficient simulation of the Sobel edge detector and obtain
meaningful results for analysis.

41
4.2.2 Workflow Overview & Simulation Setup:

The workflow begins with the acquisition of a grayscale image, which is stored locally
on the computer. If the image is in RGB format, it is converted to grayscale using
MATLAB. Subsequently, the image is converted into a hexadecimal (hex) file, a format
required for transmission of image data to the Sobel edge detection architecture. This
conversion is achieved through MATLAB scripting, enabling seamless integration with
Vivado.

Once the hex file is generated, it is stored in the simulation directory of Xilinx Vivado.
The Vivado project file is then opened, and the simulation environment is accessed.
Within Vivado, the project directory structure facilitates efficient organization of
simulation files. By navigating to the designated simulation directory, users can access
the necessary files for simulation setup.

4.2.3 Execution Procedure:

To initiate the simulation, users click on the "Run Simulation" button in the Vivado GUI,
located within the left panel under the "Simulation" box. The simulation runs based on
the provided testbench in Verilog code, ensuring comprehensive behavioral analysis of
the Sobel edge detection architecture. It is imperative to set the simulation timing to 5
milli-seconds. This optimization ensures efficient simulation execution and accurate
representation of hardware performance. After simulation is run for 5ms, one can
observe the waveforms, which indicate the data flow with each clock cycle, as discussed
below.

In the below waveform, Figure 4.1, the waveform signals represent the functioning of a
Sobel edge detection system. The clock (clk) signal synchronizes all processes, but the
reset signal, when high, initializes or stops the system completely. The start signal
initiates picture processing. The image write signals are img_write_addr,
img_write_data, and img_wr_enb, with the enable signal signifying a brief write
operation at the start. Synchronization signals (hsync and vsync) guarantee that picture
data is correctly aligned. The read signals rd_addr and rd_data represent data fetching,

42
with addresses and data changing throughout processing. The write signals wr_addr,
wr_data, and wr_enb are used to write processed data, while the enable signal indicates
active writes. The done signal indicates the end of the edge detection operation. QPO
read signals include qpo_rd_addr and qpo_rd_data, which are used to read output data.

Figure 4.1 : Waveform in Vivado Simulator for Sobel Edge Detector Simulation for 5ms

Analyzing the waveform in Vivado for Sobel edge detection involves examining the
signal transitions and their time relationships. From the above waveform following
observations are made:

Initially, the reset signal is high, ensuring all components are reset. Once reset goes low,
the start signal goes high, beginning the Sobel edge detection. Image data is written to
memory, indicated by changes in img_write_addr, img_write_data, and img_wr_enb.

The system reads image data (rd_addr and rd_data) and processes it. Processed data is
written back to memory (wr_addr, wr_data, and wr_enb). The done signal goes high,
indicating the completion of the process. The waveform shows the sequence of reading,
processing, and writing data, corresponding to these steps.

43
 By examining the timing relationships and transitions of these signals, one can
understand the flow of the Sobel edge detection process and verify its correctness.

Then the simulation can now be closed and the output edge-detected image hex file can
be visualized using the MATLAB GUI.

4.3 Result Analysis and Discussion

Following simulation execution, the converted hex data image is further processed to
generate a visually interpretable Sobel edge-detected image.

MATLAB scripts facilitate the conversion of hex data back into PNG or JPG format,
enabling qualitative assessment of edge detection performance. The resulting image is
stored in the designated project directory, ready for further analysis and validation.

Some of the sample input images of resolution 265 x 256 pixels and output
edge-detected images, obtained from the MATLAB GUI after simulation of the Sobel
Edge Detector Algorithm in Xilinx Vivado, are discussed in the below table.

Table 4.1 : Input and Edge-Detected Output images after simulation of Sobel Edge
Detector in Xilinx Vivado

Sl. Input Image Output Image

No.

44
2

45
 Thus, we successfully implemented the algorithm on Vivado, and got the desired
outputs. Since this architecture is of low resolution, i.e., 256x256 pixels resolution, so
there are false edge detections and noise is also present in the output images which can
be removed in future course of action, with more robust architecture for high resolution.

4.4 Resources and Power Utilization

Table 4.2 Post Synthesis Resource Utilization of Sobel Edge Detector on Xilinx Vivado

Resources Estimation Available Utilization %

LUT 186 53200 0.35

FF 207 106400 0.19

BRAMs 33.50 140 23.92

Table 4.3 Post-Implementation Resource Utilization of Sobel Edge Detector on Xilinx

Vivado

Resources Utilization Available Utilization %

LUT 15 53200 0.03

FF 15 106400 0.01

Table 4.4 Power Utilization of Sobel Edge Detector on Xilinx Vivado:

Total On-Chip Power 0.103W

Junction Temperature: 26.2 °C

Thermal Margin 58.8 °C(4.9 W)

Effective δJA 0W

46
4.5 Limitations
Fixed Image Size: The architecture may be limited to processing images of a fixed size,
such as 256x256 pixels. This limitation restricts its applicability to images of varying
resolutions and dimensions, potentially reducing its versatility in real-world
applications.

Limited Edge Detection Accuracy: The Sobel edge detection algorithm, while
effective in detecting edges, may produce suboptimal results in certain scenarios. It may
struggle with noisy images or complex backgrounds, leading to false positives or missed
edges. This limitation could affect the reliability of the architecture in edge detection
tasks where high accuracy is crucial.

Resource Utilization: Implementing the Sobel edge detection algorithm on an FPGA

requires significant hardware resources, including logic elements, memory, and
processing units. The architecture's resource utilization may limit its scalability and
compatibility with FPGA platforms of varying capacities.

Dependency on MATLAB Scripts: The workflow for image preprocessing and hex file
generation relies on MATLAB scripts, introducing a dependency on external tools and
libraries. Changes to MATLAB versions or scripting environments may impact the
reproducibility and compatibility of the workflow across different systems.

4.6 Conclusion
In this chapter, we successfully implemented the Sobel Edge Detector architecture on
an FPGA using Xilinx Vivado, providing a detailed overview of the design and
simulation process. By selecting appropriate design parameters, integrating the Sobel
algorithm into hardware, and setting up a robust simulation environment, we
demonstrated the effective conversion of algorithmic concepts into a functional
hardware implementation. The workflow, from image preprocessing to the generation
and visualization of edge-detected images, was meticulously outlined. Simulation
results validated the correct operation of the edge detection process, with waveforms
illustrating the data flow and signal transitions. Despite achieving the desired outputs,

47
the low-resolution architecture led to some false edge detections and noise, indicating
potential areas for future optimization. Resource and power utilization metrics
confirmed the efficiency of the design, with minimal usage of available FPGA
resources and low power consumption, showcasing the feasibility and effectiveness of
the FPGA-based Sobel Edge Detector for real-time image processing applications.

48
 Chapter 5

Conclusion and Future Work

Conclusion
Future Work

49
Chapter 5 :
Conclusion and Future Work
5.1 Conclusion
This project has successfully demonstrated the implementation of the Sobel edge detection
algorithm on an FPGA using the Xilinx Vivado environment. From the initial architectural
design to the final simulation and verification, each step was carefully executed to ensure
optimal performance and resource efficiency. The project leveraged the capabilities of the
ZYNQ-7 ZC702 Evaluation Board to process 256x256 pixel images, highlighting the
effectiveness of FPGAs for real-time image processing tasks. The detailed design choices,
including data path width, clock frequency, and memory organization, were instrumental in
achieving the desired performance metrics.

Throughout the implementation, we translated the Sobel algorithm into hardware description
language (HDL), meticulously integrating it into the FPGA architecture. The use of MATLAB
for preprocessing and post-processing of images facilitated seamless interaction with Vivado,
ensuring a smooth workflow from image conversion to edge detection output. The simulation
environment was rigorously set up to validate the architecture's functionality, with waveform
analysis confirming the correct operation of the edge detection process. The results showed
successful edge detection, though the presence of noise and false edges in low-resolution
images pointed to areas for future improvement.

In terms of resource utilization, the project demonstrated the efficiency of the design, with
minimal use of lookup tables (LUTs), flip-flops (FFs), and block RAMs (BRAMs). The low
power consumption further underscored the suitability of FPGAs for energy-efficient computing
applications. While the current architecture effectively showcased the Sobel edge detection
algorithm's implementation, future work could focus on enhancing the resolution and robustness

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of the design to reduce noise and improve edge accuracy. Overall, this project provides a solid
foundation for further exploration and optimization of FPGA-based image processing solutions.

5.2 Future Work

This work can be extended for integration into real-time edge detection systems in fields of
medical imaging, satellite imagery, lane detection, gesture recognition and so on. The following
scope can be looked into during the future course of action for improvement of this system.

Real-Time Processing Optimization: Investigate techniques to optimize the architecture for

real-time processing of high-resolution images or video streams. This could involve exploring
parallel processing strategies, hardware acceleration techniques, or algorithmic optimizations to
improve processing speed and efficiency.

Adaptive Thresholding Algorithms: Research and implement adaptive thresholding algorithms

that dynamically adjust threshold values based on local image characteristics. Adaptive
thresholding can enhance edge detection accuracy in varying lighting conditions and complex
backgrounds, improving the robustness of the architecture in practical applications.

Multi-Scale Edge Detection: Extend the architecture to support multi-scale edge detection
algorithms, such as the Canny edge detector, which can detect edges at different levels of detail.
Integrating multi-scale edge detection capabilities could enhance the architecture's ability to
capture edges of varying widths and gradients.

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