B V Raju Institute of Technology

(UGC-AUTONOMOUS)
Vishnupur - Narsapur – Medak.

Degree Bachelor of Technology Branch ECE

Academic year 2024- 2025 Mid I Sem III
Course Title VLSI physical Design
Course code A66D3
Date & Session 08.03.2025 FN
Duration 120 minutes Maximum Marks 30
PART– A (Objective)
(Answer all questions)10 x1 = 10 Marks
I. Answer All questions
1. What is the purpose of design constraints in C) The propagation delay decreases
logic synthesis? [ ] D) The hold time also increases
A) Define the chip’s physical dimensions 5. Switch logic is based on_______ [ ]
B) Specify timing, power, and area a) Pass Transistors
requirements for synthesis b) Transmission gates
C) Describe the chemical composition of silicon c) Pass Transistors & Transmission gates
wafers d) Design rules
D) Generate test vectors for verification
2. At which design level does logic synthesis II Fill in the Blanks (5 marks)
primarily operate? [ ] 6. ASIC (Application-Specific Integrated Circuit)
A) Physical design level design flow consists of steps such as
B) Gate-level abstraction specification, synthesis, ____________, and
C) Transistor-level abstraction verification.
D) System-level abstraction 7. The process of converting a high-level
3) What is the primary purpose of Static Timing hardware description into a gate-level
Analysis (STA)? [ ] representation is called ____________.
A) To verify the logical correctness of the design 8. Design constraints include parameters such
B) To simulate the dynamic behavior of the as timing, ____________, and power
circuit limitations.
C) To ensure that all timing constraints are met 9. Optimization techniques in logic synthesis
without requiring simulation focus on improving performance, power, and
D) To determine power consumption ____________.
4. What happens if the setup time requirement
of a flip-flop is violated? [ ] 10. The final output of the synthesis process is a
A) The clock frequency increases ____________ level representation of the
B) The output becomes unpredictable or circuit.
metastable
 PART - B (Descriptive)
(Answer any 4 questions) 4x5=20 marks
Q. Questions
BL COs Marks
No
a. Explain the ASIC design flow with a detailed description of each step.
b. What are the different levels of design abstraction in VLSI? Explain with L2
11 CO1 5 [2.5+2.5]
examples.
L3
a. Describe the key steps involved in logic synthesis and the role of constraints
in synthesis. L2
12 CO1 5 [2.5+2.5]
b. Differentiate between Specification, Design Description, and Logic Circuit in L2
logic synthesis.
a. Define Setup and Hold time. Explain how violations occur and
how they can be resolved. L2
13 CO1 5 [2.5+2.5]
b. What are timing paths in STA? Describe different types of
timing paths with examples. L3
a. Explain interconnect delay models and their impact on circuit
performance.
L2
14 b. What are wire load models in STA? How do they influence CO2 5 [2.5+2.5]
L3
timing analysis?

a. Explain the basic steps of VLSI physical design and their

importance. L2
15 CO2 5 [2.5+2.5]
b. What are standard cells and how are they used in VLSI L3
design?.
a. Discuss the importance of Pad Placement and Power
Planning in chip design.
16 L3 CO3 5 [2.5+2.5]
b. What is Macro Placement and how does it affect chip
performance?

** Objective questions should be answered in answer booklet only.