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The project involves designing a fast-settling operational amplifier (op amp) for a pipelined ADC, focusing on minimizing power dissipation while meeting specified performance criteria. Key specifications include a closed-loop gain of 2, a settling time of 20 ns, and a supply voltage of 2.5 V, with a detailed report required to outline design choices, calculations, and simulation results. Students must work in pairs and submit a joint report, including a complete SPICE deck for verification.

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2 views

project

The project involves designing a fast-settling operational amplifier (op amp) for a pipelined ADC, focusing on minimizing power dissipation while meeting specified performance criteria. Key specifications include a closed-loop gain of 2, a settling time of 20 ns, and a supply voltage of 2.5 V, with a detailed report required to outline design choices, calculations, and simulation results. Students must work in pairs and submit a joint report, including a complete SPICE deck for verification.

Uploaded by

pranay kamal kamal
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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UNIVERSITY OF TEXAS AT DALLAS

Erik Jonsson School of Electrical Engineering and Computer Science

Prof. Y. Chiu A High-Gain, High-Speed Op Amp Fall 2022


EECT 6326 Assigned 11/3, due 12/9 noon Term Project

In this project, you will design a fast-settling op amp to be used in a pipelined analog-to-digital
converter (ADC). Figure 1 shows the block diagram of the circuit. The list below summarizes the
design specifications. The key design objective is to minimize the power dissipation while
meeting all design specs. Use the 0.25-μm CMOS technology file posted on the course website to
model your design.

2G
1G
1pF

2pF
Vi 1V Vi Vo 2V
A Vo

1pF
VDD/2
0.1ns

Figure 1. The op amp to be used in a pipelined ADC

Specifications
Design Parameters Target Value Your Result
Closed-loop gain 2
Input voltage range (peak-peak) 1V
Output voltage range (peak-peak) 2V
Supply voltage 2.5 V
Load capacitance 1 pF
Settling error –75 dB
Settling time 20 ns
Operating temperature 0–75C

Project Guideline
Your choice of architecture is free. The most likely choice is a two-stage Miller-compensated op
amp. You will likely need to cascode the first stage to achieve the large DC gain. Alternatively,
you may pick a single-stage active-cascode topology.
You may assume that one 100-μA ideal master current source is available but need to design the
rest of your bias network. The bias of the op-amp positive input terminal and the quiescent
operating point of the output (VOQ) must be VDD/2. Thus, the input bias (VIQ) is also set to VDD/2.
Note that the large resistors are used here for your convenience to provide DC bias to the negative
input of the op-amp.

1
Report Guideline
Write a concise report, not exceeding 10 pages. Explain your architecture choice and demonstrate
how your design meets all requirements. It is very important that you show your design clearly
and convincingly. Please typewrite your report with simulation results/figures attached. Follow
the guidelines below for your report.
(≤ 1 page) Outline of your design, justification of key design decisions.
(≤ 2 pages) Calculation of key design parameters, including relevant transconductances, bias
currents, and transistor sizes to meet the specs.
(≤ 2 pages) Schematics and tables with all device sizes, Vov, gm, ID, and gm/ID of your final design.
Also report in a separate table, over three temperature corners, the major simulation results (DC
gain, settling time, etc.) and the power consumption of your amplifier.
(≤ 4 pages) HSPICE plots of key simulation results.
(≤ 1 page) Conclusion.
HSPICE Deck
You need to submit your complete SPICE deck in a sub-circuit in the following format to be
verified by your TA. Pls email your TA a plain text file.
.subckt OPAMP vip vin vo (design parameters if any)
YOUR DESIGN
.ends
Please leave supply voltage, input voltage source, any feedback resistors or capacitors and load
capacitor out of your sub-circuit.

Notes on Simulation and Results


Gain: plot the s.s. gain vs. the output voltage between 0.2–2.3 V.
Settling time: output transitions from 0.25→2.25 V and 2.25→0.25 V in response to an input step
similar to that shown in Fig. 1.
Robustness: repeat your simulation for temperatures 0C, 25C, and 75C. Show similar results at
various temperatures on the same plot for easy comparison.
Annotate your plots and draw lines/bounding boxes indicating target specs.

Lastly, you are required to work in a group of two (and no more than two) and submit a joint
report/design. Discussion with others in class is encouraged. However, please submit a genuine
design. No exchange of SPICE decks or schematics.

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