Chapter 5: Sequential Circuits

Objectives of this chapter:

1. Understand the difference between combinational
and sequential circuits.
2. Examine the different sequential circuits such as;
• Flip flops
• Registers
• Counters extra
3. Explain how we design sequential networks.
 SEQUENTIAL LOGIC & COMPUTER CIRCUITS
 In sequential circuits, the output depends on the current
input as well as past output/outputs (current state).
 Whereas in combinational circuits the output depends only
on the present values of the input, at any instant of time.
 Sequential circuit can be considered as combinational circuit
with feedback circuit.
 Sequential circuit uses a memory element as feedback
circuit in order to store past values.
 The information stored in sequential circuits represents
current state of the circuit.
 The current state and current input will define output and the
next state of the circuit.
SEQUENTIAL LOGIC & COMPUTER CIRCUITS
1. Combinatorial circuits

2. Sequential circuits
 SEQUENTIAL LOGIC & COMPUTER CIRCUITS
 Combinational circuits cannot be used for storage
because:
 They have no memory
 They do not contain feedbacks
 They are time independent.
 Their outputs solely depend on their current
inputs.
 They have no intrinsic timing control.

 Sequential circuits have internal states that can be

used to store information and modify their inputs.
 SEQUENTIAL LOGIC & COMPUTER CIRCUITS
• Examples
 A Counting Device: Generally, we come across many
counters in our daily life to count the number of objects.
For example to count the number of audience entering
or leaving an auditorium or to count number of vehicles
in parking. In this when any person enters in to
auditorium the counter increments its value depending
on its present value. Similarly, it decrements its value
depending on its previous and present value. So
Counter retains the current state of the counter to do
next operation.
 A memory circuit; the input causes the contents of
memory to be applied to the outputs.
 SEQUENTIAL LOGIC & COMPUTER CIRCUITS
 Time in a sequential circuit takes on a significant
role.
 A sequential network is defined according to its
inputs and outputs over a period of time.
 In sequential networks, a truth table is not enough
to show input/output relationships because it
ignores time.
 The aid used in examining the time dependent
aspect of a sequential network is called a timing
diagram
 A Timing Diagram
A
B

Increasing time
 The higher value on the vertical state corresponds to state 1 and lower value
corresponds to state 0.
 A begins in state 0, B and X begin in state 1.
 Transition of A to 1 does not change X.
 Transition of B from 1 to 0 causes X to change to 0.
 Transition of A from 1 to 0 does not affect X but the following transition of A causes
X to change to 1.
 Output Y is shown to change states 25 µs after a change in X.
 Timing Diagrams
• Sequential networks are synchronized by a time standard
called a clock.
• A clock is a signal that oscillates between 1 and 0 state
and is used to coordinate actions of a digital circuit.
• A clock generates an evenly spaced train of pulses.
• Time between consecutive pulses is called a period. The
number of periods per second is called a frequency.

Period
• Elementary sequential circuits fall into a class of binary
electronic circuits known as multivibrators which may be
astable, monostable or bistable
 Multivibrators
Multivibrators are sequential logic circuits that operate
continuously between two distinct states of HIGH(1) and
LOW(0).
 Astable multivibrators
They cannot maintain a fixed state but they keep on
switching back and forth between their states.

 Monostable multivibrators
They can take on two states but are stable in only one of
them. They can only temporarily stay in the unstable state.

 Bistable
They are stable in either of the 2 states and can therefore
maintain either state indefinetely.
 FLIP FLOPS
 Flip flops are basic components used in registers and counters to store
data. They are bistable devices that are used in sequential networks.
 The most common flip-flops are the R-S, J-K, T, and the D flip flop.

THE R-S FLIP FLOP

S Q

Q
R
S R Q+ Q+ S Q
0 0 Q- Q- C FF
0 1 0 1 R Q
1 0 1 0
1 1 - -
 THE R-S FLIP -FLOP
• It has 3 inputs S(Set), R (Reset) and C (a clock input) which
synchronises the action of the flip-flop with its surrounding

• The two outputs (Q and Q) are always in opposite states from each
other.
• Most significant changes occur when there is a clock transition.
• If the clock input is constant, the outputs will follow the changes in the
inputs at all times.
• When the clock is in 0 state Both R and S inputs have no effect on the
state of the flip-flop. The network is then stable.
In this state, if Q = 1, Q is = 0 and Q is maintained at 1. If Q is 1, Q = 0
and Q is maintained at 1.
• If the clock is raised to 1 the network will not change if R = S = 0

• The subscripts Q- and Q- indicate outputs just before the clock

becomes 1 and the subscripts Q+ and Q+ show outputs just after the
clock becomes 1
 Flip Flops
• All clocked flip flops that react to their inputs anytime C = 1
are called latches.
• The R-S flip-flop is called a latch because it uses the clock
inputs to determine whether or not the inputs will be
recognised.
• If a flip-flop changes only at the very beginning (or the very
end) of a clock pulse it is called an edge triggered
flipflop. They change state only when there is a 0 to 1
transition at C (+ve edge triggered) or a 1 to 0 transition at
C (-ve edge triggered).
• A change from 0 to 1 is a +ve transition and the +ve
transition of a clock pulse is called the leading edge.
• A change from 1 to 0 is a negative transition and the
negative transition of a clock is called a trailing edge.
 Example

Q +ve edge triggered

 The J-K Flip Flop
• It is an R-S flip flop that has been modified by
feeding the outputs back and ANDYING them
with the inputs.

• It has the same behaviour like the R-S flip flop

except that the C = J = K = 1 combination is
meaningful and the results in the output states is
reversed.

• The J-K flip –flop is constructed from an edge

triggered R-S flip-flop otherwise the C=J=K=1
state would be unstable.
 J-K Flip Flop

J S Q
C
C R Q
K

J Q
C FF
K Q
J K Q+ Q+
0 0 Q- Q-
0 1 0 1
1 0 1 0
1 1 Q- Q-
 T Flip-Flop
•
S FF Q T FF Q
T C Q
R Q
T Q+ Q+
0 Q- Q-
1 Q- Q-
• It has only one input.
• Its output states are reversed each time the input is
pulsed.
• It is used in the design of counters.
• A T flip flop can be obtained from a J-K flip flop by
permanently applying 1’s to the J and K inputs. The R-S
flip flop must be edge triggered, otherwise the network
would be unstable.
 D FLIP FLOP
D
D S FF FF
Q C
C C
Q D Q+ Q+
R 0 0 1
1 1 0
• It has 2 inputs, a clock input and an input labelled D such that
the Q output is equal to the D input whenever the clock input is
set to 1; otherwise it is not affected by the D input.

• It is used in constructing registers . It is easily constructed from

the R-S flip flop by letting the D input be S input and
connecting R to D through an inverter.
 EXAMPLE

Q
Latch
Q
Positive edge triggered

Q
Negative edge triggered
 Clear and Preset Inputs
• Flip flops can clear or set the Q output irrespective of the
state of the other inputs. The clear input clears Q and the
Preset input sets Q

D J Preset
FF
C
C
K
clear clear
 Try this out!!!
1. The Timing diagrams below show inputs for the J-K flip-flop.
Give corresponding Q outputs assuming that it is:
(i)An Ordinary Flip-flop (a latch)
(ii) A positively edge triggered flip-flop
(iii) A negatively edge triggered flip-flop
•Assume in all cases that the initial state of Q is 0.
 REGISTERS
• A number of flipflops placed in parallel to form several
bits of storage. Each flip flop is capable of storing 1 bit of
information. Registers are used anywhere in the computer
where it is necessary to store a number of bits.

e.g. a 4 bit register constructed from four D flipflops

D3 D2 D1 D0

D Q D Q D Q D Q

C Q C Q C Q C Q

Load
Read

Q3 Q2 Q1 Q0
 Registers
The common clock load permits new
information to be loaded.

The common Read line and associated AND

gates provide a controlled Read out
mechanism.

If n flip flops are used, the register is said to

have a length of width n.
 Registers
The currently stored data are the current
states of the flip flops and can be monitored at
the Q outputs.

Transfer of new information into the register is

known as loading the register.

If all bits of the register are loaded at the same

time we say that the loading is done in
parallel.
 Shift registers
• Shift registers are classified according to input and
output which maybe either serial or parallel.
• They are used in converters to translate parallel
data to serial data.
• A serial input is one for which the input arrives 1 bit
at a time, and each time a bit arrives the register is
shifted by one to accommodate the new bit.
• A parallel input is one for which the inputs are all
loaded at the same time.
• If the left most bit is brought around and put in the
right bit during a left shift, or the right most bit is put
in the left bit during a right shift the operation is
called a rotation.
 Shift registers
• The Shift Register is another type of sequential
logic circuit that can be used for the storage or the
transfer of binary data.
• They are capable of shifting their bits either to the
left or to the right. They have a tendency of
rearranging their contents.
• If an 8 bit register contains 0 1 1 0 0 1 0 1
and a left shift operation is performed, the new
contents of the register will be
1 1 0 0 1 0 1 0.
• A 1 bit right shift would result into
0 0 1 1 0 0 1 0
 Shifting and Rotation
RLC (Rotate Left)
0 0 0 0 0 1 1 1

The content of the accumulator is rotated left one position.

The low order bit and the carry flag are both set to the
value shifted out of the high order bit position.

RRC (Rotate Right)

0 0 0 0 1 1 1 1
The content of the accumulator is rotated right one
position. The high order bit and the carry flag are both set
to the value shifted out of the low order bit position.
 Shifting and Rotation
RAL (Rotate Left through carry)
0 0 0 1 0 1 1 1
The content of the accumulator is rotated left one position
through the carry flag. The low order bit is set equal to the
carry flag and the carry flag is set to the value shifted out
of the high order bit position.

RAR (Rotate Right through carry)

0 0 0 1 1 1 1 1
The content of the accumulator is rotated right one
position through the carry flag. The high order bit is set
equal to the carry flag and the carry flag is set to the value
shifted out of the low order bit position.
 Example
Consider initially A = 01101001 and the carry flag (c) = 1
RLC
11010010
RRC
10110100
RAL
11010011
RAR
10110100
 Data Transmission
Shift registers are used most importantly in
converting different types of data
communications.

If n bits are transmitted simultaneously over n

signal paths. This is called parallel data
transmission.

If one bit is sent one after the other over 1

signal path, this is called Serial Data
transmission.
 Data Transmission
In parallel transmission, some extra
control lines are used by the transmitting
device to signal to the receiving device
when data is ready to be read and the
receiving device to signal to the
transmitting device that the data has been
read.

The passing back and forth of signals on

the control lines during transmission is
called handshaking.
 Data Transmission
If one of the control lines transmits clock
signals and the timing of all the other
signals is controlled by these pulses the
data transmission is said to be
synchronous.

A transmission that is not controlled by a

common clock signal is said to be
asynchoronous.
 Data Transmission
Serial transmission is made over a single
pair of lines and the beginning and end of
transmission are marked by special bits
called a start bit, a stop bit and parity bits.

A character transmitted in the asynchronous

serial mode consists of the following 4 parts:
A start bit
Five to 8 data bits
An optional even / odd parity bit
1 or 2 stop bits.
 Data Transmission
A timing diagram to transmit an ASCII character E = 45
with 1 start bit and 1 stop bit

0 1 0 1 0 0 0 1 0
Start bit Stop bit

At the end of each character the signal always goes to

a logical 1 for the stop bit. It remains 1 until the start of
the next character which begins with a start bit at
logical 0.

The logical 1 and logical 0 are respectively knows as

the mark and space.
 Data Transmission
Parallel Transmission
Advantages
Higher information transfer rate can be attained.

Disadvantages
More wires (or communication channels) are needed.

Whenever distance is a factor serial transmission is

chosen.
If the transfer rate must be high parallel communication
may be required.
Because a computer system includes both types of data
communications, it must also include means of
converting from one type to another.
 Serial To Parallel Converter
Parallel Output

D0 D1 D2 D3
Serial
Input D Q D Q D Q D Q

Clock
C Q C Q C Q C Q
Clear Clear Clear Clear

Reset

• Each clock pulse loads a data bit until the register is full. After
the 4 bit character is loaded it can be read from the parallel
output lines D0 – D3
 Parallel To serial Converter

• Once data is made available at PA – PD it can be

loaded into the shift register by load signal.
• The 4 clock pulses are used to cause the 4 bit
character to appear sequentially at the output
 A Binary Counter
It is a circuit used to count and store the
number of pulses arriving at its input.

A counter that follows the binary number

sequence is called a binary counter.

An n bit binary counter is a register of n flip

flops and associated gates that follows a
sequence of states according to the binary
count of n bits from 0 to 2n – 1
 Binary Counters
A4 bit counter capable of counting from 0000 through 1111
FF Q FF Q FF Q FF Q

Enable T T T T
Input
Clear Q Clear Q Clear Q Clear Q

Reset
Q0 (20) Q1 (21) Q2 (22 ) Q3 (23)

The enable input provides a means of turning the counting

process on and off without removing the clock signal from the flip
flop and the reset input clears the counter.
 Binary Counter
Going through a sequence of binary numbers e.g.
0000 0001, 0010 etc, the lower order bit is
complemented after every count and every other bit
is complemented from one count to the next if all its
lower bits are equal to 1.

A sixteenth pulse has the same effect as the Reset

input for it clears all the 4 bits.

A counter circuit employs flip flops with

complementing capabilities like a J-K flip flop when
C = J = K = 1 or a T flip flop.
 Sequential Network Design
 The behaviour of a sequential circuit is
determined from the inputs, the outputs
and the state of the flip flops.

 A state is determined by a 0 & 1

combination of the outputs of the flip
flops of the network.

 If a network contains n flip flops, the

possible number of states would be 2n.
 Sequential Network Design
 The actual number of states that the
network can be in may be less because
the construction of the network may not
allow some input combinations to occur.

 If m is the number of states that can

occur and n is the number of flip flops
used, then 2n >= m.
 Sequential Network Design
A sequential circuit is specified by:
1. A State Table that relates the next state as a
function of the inputs and the present state.

2. Output Table: gives the outputs as a

function of the current state.

Information in the state table and output tables

can be combined into a state diagram where
circles represent the states and outputs and the
arrows represent the transition between states.
 Sequential Network Design

Example:

Assume 2 inputs A and B, five states S0 –S4 and

three outputs X, Y, Z.
 Sequential Network Design
State table
Inputs
00 01 11 10
S0 S1 S1 S0 S0
Current S1 S0 S4 S3 S3
State S2 S2 S0 S1 S0
S3 S1 S2 S1 S3
S4 S4 S4 S4 S4
 Sequential Network Design
Output Table

Outputs
X Y Z
S0 0 0 1
new S1 0 1 0
State S2 0 1 1
S3 1 0 0
S4 1 1 1
 Sequential Network Design
10, 11
S0 00, 01 S1 01
0 0 1 00 0 1 0 00,01,11,10

01,10 11 10,11 00, 01 S4

1 1 1
00 S2 01 S3 10
0 1 1 1,0 0
 Sequential Network Design
Example
The state table, output table and state diagram of a
network consisting of only one J-K flip flop

State table Output Table

JK
00 01 11 10 X
S0 S0 S0 S1 S1 S0 0
S1 S1 S0 S0 S1 S1 1

S0 corresponds to Q = 0 S1 to Q = 1
10,11
00,01 S0 S1 00,10
0 01,11 1