A. CSC1104 Computer Organization and Architecture End of Semester I 2020-2021 Examination
A. CSC1104 Computer Organization and Architecture End of Semester I 2020-2021 Examination
EXAMINATION INSTRUCTIONS
1. ATTEMPT ALL QUESTIONS (100 MARKS). All questions carry EQUAL marks.
2. Write your answers on ruled papers and make sure you upload your answer
scripts before 6pm.
3. You can use a phone or a scanner to scan your answer scripts then upload them
on Muele. Make sure to upload your solutions in PDF format.
5. Answers which are simply copied or quoted from reference material won’t
receive any credit.
Question 1:
(a) Given the Boolean function F = ABC’+ A’BC +AB’C’ + A’BC’
(i) Formulate a truth table for the function (3 Marks)
(ii) Draw a logic diagram using the original Boolean expression (2 Marks)
(iii) Simplify the algebraic expression using Boolean algebra or otherwise
(3 marks)
(iv) Draw a logic diagram corresponding to the simplified expression
(2 Marks)
(b) Write Boolean expressions for the SOPs from which the following Karnaugh maps
are derived assuming that the output is X.
(i) (2 Marks)
AB 00 01 11 10
C 0 1 1 0 0
1 0 1 1 0
(ii) (3 marks)
AB 00 01 11 10
CD 00 1 1 0 1
01 1 1 0 1
11 0 1 0 0
10 0 1 0 0
(iii) Simplify the expressions obtained in part (b) above using a Karnaugh Map method.
(5 Marks)
Question 2:
(a) Using the concept of decoder and encoder construction, design a Programmed Logic
Array (PLA) that implements the outputs X, Y and Z given below. (14 marks)
AB
00 01 11 10
00 0 0 0 0
CD 01 0 1 1 0
11 0 1 1 0
10 0 0 0 0
X
2
AB
00 01 11 10
00 0 0 0 0
CD 01 1 1 1 1
11 0 0 1 0
10 0 0 0 0
Y
AB
00 01 11 10
00 0 0 0 0
CD 01 1 0 0 1
11 0 1 1 0
10 1 0 0 1
Z
(b) The truth table shown here is for a 4-line to 16-line binary decoder circuit:
For each of the sixteen output lines, there is a Boolean SOP expression describing its
function. Write the Boolean expressions for output lines 5, 8, and 13. (6 marks)
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Question 3:
(a) Adders are digital circuits in electronics that implement addition of binary numbers.
Given two numbers A= 01111100 and B = 01011010, use the concept of ripple carry
adders to find A+B. Using an illustration, explain in detail how the full adders are joined
together to carry out the addition of these 8-bit numbers. (10 marks)
(b) Given the network shown below, find Boolean expressions for the outputs, simplify
these expressions, and draw an equivalent network using the simplified expressions.
(10 marks)
Question 4:
(a) The Timing diagrams below show inputs for the R-S flip-flop. Give corresponding Q
outputs assuming that it is:
(i) An Ordinary Flip-flop (a latch) (3 marks)
(ii) A positively edge triggered flip-flop (3 marks)
(iii) A negatively edge triggered flip-flop (3 marks)
R
S
(d) Assume the following inputs for the T flip flop and give the corresponding Q outputs.
(Initial State of Q is 0)
T 0 1 1 1 0 0 1 1 1 0
(2 marks)
(e) Character M (M = 4D) is to be transmitted in serial using one start, and one stop bit.
Show how this transmission will appear on the timing diagram. (5 marks)
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(f) An 8-bit register is loaded as shown below. Determine its contents when each of the
following actions is carried out.
0 1 1 0 1 1 1 0
Question 5
(a) Assume that the numbers A= 88CC3000 and B = 84EA0000 are Typical IBM 32-bit
Floating-Point Format numbers:
(i) Find A + B (3 marks)
(ii) Find A / B (3 marks)
(iii) Convert A to the IEEE Single Precision Floating Format (2 marks)
(iv) Convert B to the Double Precision IEEE floating point Format. (2 marks)
(b) Assume that each alphanumeric ASCII character is represented by 7 bits, decipher the
following code: 100101011011111010001101110 (5 marks)
(c) Extend the ASCII code to 8 bits by adding a 0 to the left of each character and find the
bit combinations needed to store the character strings given below. Give your answers in
hexadecimal notation. (Caution: Do not overlook the spaces, periods, carriage returns,
line feeds extra.)
a. CSC 1104
b. Comp_Arch (5 marks)
END
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Appendix