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Lab Manual for Power Electronics

The document outlines general laboratory safety rules emphasizing the importance of following instructions, wearing appropriate clothing, and checking circuits to prevent accidents. It also details the operation of power supply circuits, including components like transformers, rectifiers, and regulators, and provides a procedure for measuring AC and DC voltages. Safety precautions are highlighted throughout to ensure the well-being of individuals working with electrical equipment.

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0% found this document useful (0 votes)

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Lab Manual for Power Electronics

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aqibnazir0603

Available Formats

Download as DOCX, PDF, TXT or read online on Scribd

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GENERAL LABORATRY SAFETY

RULES
Low voltage electric and electronic are dangerous seldom by themselves, but any work a
laboratory offers many opportunities for injury and damage to instruments. The following rules
should have to be established as a guide to safety and comfort, other rules as determined by the
instructors may also be in effect. At all times, you will be expected to use common sense to
avoid endangering yourself or your partners. You are responsible for damage to any circuits or
instrument.

1) Follow all your lab instructions from your lab instructor.

2) No smoking, food or drinks are allowed in the lab.
3) Wear comfortable clothing. Avoiding long sleeves and ties, synthetic fabrics, and
silk garments (these are severe static discharge hazards).
4) Remove rings and the metal jewelry that could contact the circuit. This may save
your life.
5) Check all test circuits before applying power. Look for short circuits, components
installed backwards, or underrated components. Circuits built on Prototyping
boards are especially prone to errors due to many opportunities for the
components to cross each other.
6) Use safety features whenever they are available.
7) Always “smoke test” the circuits before attaching instruments. Check the current
drawn from the power supply to make sure it is reasonable.
8) Never attach instruments probes to a circuit before the probes are attached to
instrument and the instrument is powered up, otherwise you will damage the
instruments.
9) Most instruments have an active or hot lead and a ground lead (for example, an
oscilloscope has a probe tip and a ground clip). Make sure that you don’t form a
short between two or more distinct nodes of your circuit by connecting
instruments ground leads to different nodes. This may damage your instruments
as well as change the circuit you are trying to measure.
10) When using line voltage or other sources of potentially lethal electrical power,
always disconnect leads (plugs) from the high voltage end first. Never hold high
voltage leads in both hands, keep one hand behind your back when working on
the circuit that is energized at dangerous potential.
11) Even low voltage Dc supplies are very dangerous. This is especially true when
your skin is wet or if probes or wires penetrates in your skin.

1
12) Most Instruments are provided with a grounded plug for use in three-hole
grounded socket. The ground provides Protection in case a fault occurs in the
instrument or lethal voltage is otherwise applied to the instrument case.
EXPERIMENT#1
Power Supplies
OBJECTIVE:
1. Understanding the operation of power supply circuits
2. Measuring AC voltages.
3. Measuring AC voltages.

DISCUSSION:
All of electronic circuits require certain constant dc supply voltages to supply
the required operating voltages. There are many types of power supply. Most are designed to
convert high voltage AC mains electricity to a suitable low voltage supply for electronic circuits
and other devices. A power supply can by broken down into a series of blocks, each of which
performs a particular function.
For example, a 5V regulated supply:

 Transformer - steps down high voltage AC mains to low voltage AC.

 Rectifier - converts AC to DC, but the DC output is varying.
 Smoothing or filter - smoothed the DC from varying greatly to a small ripple.
 Regulator - eliminates ripple by setting DC output to a fixed voltage.
Power supplies made from these blocks are described below with a circuit diagram and a graph
of their output:
 Transformer only
 Transformer + Rectifier
 Transformer + Rectifier + Smoothing
 Transformer + Rectifier + Smoothing + Regulator

Dual Supplies
Some electronic circuits require a power supply with positive and negative outputs as well as
zero volts (0V). This is called a 'dual supply' because it is like two ordinary supplies connected
together as shown in the diagram.

2
Transformer only

The low voltage AC output is suitable for lamps, heaters and special AC motors. It is not suitable
for electronic circuits unless they include a rectifier and a smoothing capacitor.

Transformer + Rectifier

The varying DC output is suitable for lamps, heaters and standard motors. It is not suitable for
electronic circuits unless they include a smoothing capacitor.

Transformer + Rectifier + Smoothing

The smooth DC output has a small ripple. It is suitable for most electronic circuits.

3
Transformer + Rectifier + Smoothing + Regulator

The regulated DC output is very smooth with no ripple. It is suitable for all electronic circuits.

Transformer

Transformer
circuit symbol
Transformers convert AC electricity from one voltage to another with little loss of power.
Transformers work only with AC and this is one of the reasons why mains electricity is AC.
Step-up transformers increase voltage, step-down transformers reduce voltage. Most power
supplies use a step-down transformer to reduce the dangerously high mains voltage (230V in
UK) to a safer low voltage. The input coil is called the primary and the output coil is called the
secondary. There is no electrical connection between the two coils, instead they are linked by an
alternating magnetic field created in the soft-iron core of the transformer. The two lines in the
middle of the circuit symbol represent the core. Transformers waste very little power so the
power out is (almost) equal to the power in. Note that as voltage is stepped down current is
stepped up. The ratio of the number of turns on each coil, called the turns ratio, determines the
ratio of the voltages. A step-down transformer has a large number of turns on its primary (input)
coil which is connected to the high voltage mains supply, and a small number of turns on its
secondary (output) coil to give a low output voltage.

Vp Np power out = power in

turns ratio = = and
Vs Ns Vs × Is = Vp × Ip

Vs = secondary (output) voltage

Vp=primary(input)voltage Ns = number of turns on secondary coil
Np = number of turns on primary coil Is = secondary (output) current
Ip = primary (input) current

Rectifier

4
There are several ways of connecting diodes to make a rectifier to convert AC to DC. The
bridge rectifier is the most important and it produces full-wave varying DC. A full-wave rectifier
can also be made from just two diodes if a center-tap transformer is used, but this method is
rarely used now that diodes are cheaper. A single diode can be used as a rectifier but it only uses
the positive (+) parts of the AC wave to produce half-wave varying DC.

Bridge rectifier
A bridge rectifier can be made using four individual diodes, but it is also available in special
packages containing the four diodes required. It is called a full-wave rectifier because it uses all
the AC wave (both positive and negative sections). 1.4V is used up in the bridge rectifier because
each diode uses 0.7V when conducting and there are always two diodes conducting, as shown in
the diagram below. Bridge rectifiers are rated by the maximum current they can pass and the
maximum reverse voltage they can withstand (this must be at least three times the supply RMS
voltage so the rectifier can withstand the peak voltages). Please see the Diodes page for more
details, including pictures of bridge rectifiers.

Single diode rectifier

A single diode can be used as a rectifier but this produces half-wave varying DC which has gaps
when the AC is negative. It is hard to smooth this sufficiently well to supply electronic circuits
unless they require a very small current so the smoothing capacitor does not significantly
discharge during the gaps. Please see the Diodes page for some examples of rectifier diodes.

Output: half-wave varying DC

Single diode rectifier
(using only half the AC wave)

5
Smoothing or Filter
Smoothing is performed by a large value electrolytic capacitor connected across the DC supply
to act as a reservoir, supplying current to the output when the varying DC voltage from the
rectifier is falling. The diagram shows the unsmoothed varying DC (dotted line) and the
smoothed DC (solid line). The capacitor charges quickly near the peak of the varying DC, and

then
discharges as it supplies current to the output.

Note that smoothing significantly increases the average DC voltage to almost the peak value
(1.4 × RMS value). For example, 6V RMS AC is rectified to full wave DC of about 4.6V RMS
(1.4V is lost in the bridge rectifier), with smoothing this increases to almost the peak value
giving 1.4 × 4.6 = 6.4V smooth DC. Smoothing is not perfect due to the capacitor voltage falling
a little as it discharges, giving a small ripple voltage. For many circuits a ripple which is 10% of
the supply voltage is satisfactory and the equation below gives the required value for the
smoothing capacitor. A larger capacitor will give less ripple. The capacitor value must be
doubled when smoothing half-wave DC.

5 × Io
Smoothing capacitor for 10% ripple, C =
Vs × f

C = smoothing capacitance in farads (F)

Io = output current from the supply in amps (A)
Vs= supply voltage in volts (V), this is the peak value of the unsmoothed DC
f = frequency of the AC supply in hertz (Hz), 50Hz in the UK

6
Regulator

Voltage regulator ICs are available with fixed (typically 5, 12 and 15V) or variable output
voltages. They are also rated by the maximum current they can pass. Negative voltage regulators
are available, mainly for use in dual supplies. Most regulators include
some automatic protection from excessive current ('overload protection')
and overheating ('thermal
protection').

Voltage regulator ICs are available with fixed

(typically 5, 12 and 15V) or variable
output voltages. They are also rated by
the maximum current they can pass. Negative voltage regulators are
available, mainly for use in dual supplies. Most regulators include some Voltage regulator
automatic protection from excessive current ('overload protection') and
overheating ('thermal protection').
Many of the fixed voltage regulator ICs have 3 leads and look like power transistors, such as the 7805
+5V 1A regulator shown on the right. They include a hole for attaching a heatsink if necessary.
Please see the Electronics in Meccano website for more information about v
tag regulator ICs.

Zener diode regulator

For low current power supplies a simple voltage regulator can be
made with a resistor and a Zener diode connected in reverse as shown
in the diagram. Zener diodes are rated by their breakdown voltage Vz Zener diode
and maximum power Pz (typically 400mW or 1.3W). The resistor a = anode, k = cathode
limits the current (like an LED resistor). The current through the
resistor is constant, so when there is no output current all the current
flows through the Zener diode and its power rating Pz must be large
enough to withstand this. Please see the Diodes page for more
information about Zener diodes. Choosing a Zener diode and resistor:
1. The Zener voltage Vz is the output voltage required
2. The input voltage Vs must be a few volts greater than Vz
(this is to allow for small fluctuations in Vs due to ripple)
3. The maximum current Imax is the output current required plus
10%
4. The zener power Pz is determined by the maximum current:
Pz > Vz × Imax
5. The resistor resistance: R = (Vs - Vz) / Imax
6. The resistor power rating: P > (Vs - Vz) × Imax
Example: output voltage required is 5V, output current required is
60mA.
1. Vz = 4.7V (nearest value available)
2. Vs = 8V (it must be a few volts greater than Vz)
3. Imax = 66mA (output current plus 10%)

7
4. Pz > 4.7V × 66mA = 310mW, choose Pz = 400mW
5. R = (8V - 4.7V) / 66mA = 0.05k = 50 , choose R = 47
6. Resistor power rating P > (8V - 4.7V) × 66mA = 218mW, choose P = 0.5W

Experiment circuit

8
EQUIPMENT REQIUIRED:
1- Power Supply Unit KL-51001
1-Isolation Transformer KL-58002
1-Meter Unit KL-58001

9
PROCEDURE:
1. Correct AC LINE INPT of power supply Unit KL-58002 to an AC outlet using the supplied
power cord.
2. Connect the voltmeter (0-110V scale) across the ac output terminals labeled AC18V AND 0 with
test leads.
3. Turn on the power. Measure and record the ac output voltage as indicated by the ac voltmeter.

Vac= ___________________ V

4. Turn off the power. Exchange test leads and repeat step 3

Vac= ___________________ V

Is there god agreement between steps 3 and 4?

Turn off the power.

5. Connect the ac voltmeter (0-110V Scale) across the ac output terminals labeled AC 18V

and AC 18 V with test leads.

6. Turn on the power. Measure and record the ac output voltage as indicated by the ac

voltmeter.

Vac=__________________ V

7. Turn off the power. Exchange test leads and repeat step 6.

Vac= _________________V

Is there good agreement between step 6 and 7?

State the relation between steps 7 and 4.

Turn off the power.

8. Connect the ac voltmeter f (0-110V Scale) across the ac output terminals labeled AC 12V and 0
with test leads.
9. Turn on the power. Measure and record the ac output voltage as indicated by the ac voltmeter.

Vac=_____________________V

10. Turn off the power. Exchange test leads and repeat step 9.

Vac=_____________________V

Is there good agreement between step 9 and 10?

Turn off the power.

10
11. Connect the ac voltmeter (0-110V Scale) across the ac output terminal labeled AC 12 V and AC
12 V with test leads.

12. Turn on the power. Measure and record the ac output voltage as indicated by the ac voltmeter.

Vac=_____________________V

13. Turn off the power. Exchange test leads and repeat step 12

Vac=_______________________V

Is there good agreement between step 12 and 13?

State the relation between steps 10 and 13.

Turn off the power.

B.DC Voltage Measurement

14. Connect the dc voltmeter (0- 20V Scale) across the dc output terminals labeled DC 12 V and
GND with test leads. For the proper polarity connections, the terminal DC 12 V (the positive)
should be connected to the terminal 20 V (the positive) and the terminal GND (the negative) to
terminal 0 (the negative).
15. Turn on the power. measure and record the dc output voltage as indicated by the dc voltmeter.

Vdc=_______________________V.

16. Turn off the power. Connect the dc voltmeter (0-20V Scale) across the dc output terminals
labeled DC5V and GND with test leads. The terminal DC5V should be connected to the
terminal 20V and the terminal GND to terminal 0.
17. Turn on the power. Measure and record the dc output voltage as indicated by the dc voltmeter.

Vdc=___________________V

18. Turn off the power. Connect the dc voltmeter (0-10V Scale) across the dc output terminals
labeled DC5V and GND with test leads. The terminal DC5V should be connected to the
terminal 10 V and the terminal GND to terminal 0.
19. Turn on the power. Measure and record the dc output voltage as indicated by the dc voltmeter.

Vdc=__________________V

Is there good agreement between steps 17 and 19?

CONCLUSION
The DC voltmeter is the measuring instrument used to measure dc voltage. It is always connected in
parallel with the terminals of the circuit component whose voltage we wish to measure. Verify the
polarity and measurement range before applying power to the circuit. Choosing a range too small or

11
reversing the polarity will cause the pointer to hit the mechanical stop at the end of the scale. It will be
impossible to obtain a valid reading in this case, and the voltmeter may be damaged.

The AC voltmeter is the measuring instrument used to measure ac voltages. The same rules about the DC
voltmeter apply to the AC voltmeter except that the polarity is regardless.

EXPERIMENT 2
UJT Characteristics
12
OBJECTIVE
1. Understanding the construction and Characteristics of a UJT.

2. Understanding the operation and two-transistor equivalent of a UJT.

3. Measuring the Characteristics of a UJT.

4. Construction and measuring basic UJT application circuits.

DISUSSION
The uni junction transistor (UJT) was first introduced in 1948 and become commercially
available device from 1952.

The UJT conventionally considered as a silicon bar to which a p-n junction is made as illustrated
in fig. The retifying contact is called emitter (E) in practice B2 terminal is usually made positive
with respect to the B1 terminal by potential of VB1B2 .

13
Diode equivalent circuit of ujt is shown in fig.

The diode represents the p-n junction characteristic between the emitter and base bar.

RBB =RB1+RB2 │IE=0

The magnitude of RBB is typically from 4 to 10 KΩ.

When IE=0, the voltage droop on the RB1 is determined by the voltage divider rule

VRB1=RB1∕ (RB1+RB2) VB1B2│IE=0= ᶯ(VB1B2)│IE=0

UJT Characteristics

The static Characteristics curve of typical UJT is shown in fig

14
When the applied emitter voltage is smaller than the peak point voltage the p-n junction at
emitter biase is reverse biaseand only a small leakage current IE0 normally flows in the emitter.

This current is measured in uA , corresponds very closely with the reverse leakage current Ico
of conventional bipolar transistor. This region is called cutoff region. When the voltage VE is
increased , a voltage is reached where VE is equal to the sum of the forward voltage droop
across the p-n junction and voltage across RB1.This voltage is called peak point voltage VP.
When the applied VL reaches the peak point voltage the diode will fire and the UJT will conduct
from the cut off region into the resistance region.

There are physical structures of a UJT. The most popular is bar structure. The other type is
cube structure. Both are shown below.

Testing UJT with Ohmmeter

15
An Ohmmeter, found on analog millimeter ,can be used to check the condition of UJT and to
identify the terminals of UJT.select the range of multimeter 1KΩ,connect the red lead base 2
and

black lead base 1. A reading between 4 and 10 KΩ is obtained. Reversing the polarity the same
reading should be obtained. This indicated that IE=0

Description of Experiment Circuit

Fig shows the Experiment on the KL-53001 module. Transistor Q1 and Q2 form a equivalent
circuit of UJT .The UJT and associated components are used for the Characteristics
measurements. Ac voltage source and the series network R4, VR1 and R5 determine the
emitter voltage VE of the UJT. IF UJT is very small, the UJT will appear in cutoff state.
Therefore Q3 and LED are off. If the condition VE>VP+0.5V is met by adjusting VR1, the UJT
will be turned ON and the output voltage appears on R11.This voltage drives both Q3 and LED
ON.

EQUIPMENT REQIUIRED
1- Power Supply Unit KL-51001
2- Isolation Transformer KL-58002
3- Module KL-53001
4- Analog Multimeter
5- Dual Trace Oscilloscope

PROCEDURE
UJT Characteristics Measurement

1. Insert connect plugs in 1,4,6, and 8 positions. Adjust VR1 fully CCW to obtain a minimum
resistance.

16
2. Turn on the power .Observe and record the state of LED.――――――.The UJT is operating
in――――region. Using the multimeter, measure and record the voltage across R11.―――V.

3. Measure and record the emitter voltage of the UJT with the multimeter (the red lead to E ,the
black lead to GND).VE=―――――V.

4. Slowly turning the VR1 to the right (CW), observe the change of VE until the voltage reading
reaches a peak value and abruptly reduces to valley value. Record the peak and valley values.
The peak value represents the peak point voltage of the UJT and valley value is the valley point
voltage.

Vp=―――――――――V.

Vv=―――――――――V.

5. The LED is――――――――― (ON or OFF)

The UJT should operate in―――――――――region.

6.using the multimeter measure and record the voltage across R11.

VR11=―――――――――V.

7. Set the dual trace oscilloscope to X-Y mode. Connect GND of the oscilloscope to the emitter
(E) of the UJT.CH1 input to the other terminal of R6,and CH2 input to the base 1(B1) of the
UJT. Plot the IE_VE curve on the display of oscilloscope in table below.

8. Adjusting VR1, observe and record the change of IE_VE curve.

17
9. Turn off the power.

CONCLUSION
In procedure step 5, the measured Vp and Vv should be about 2.5 V and 0.9V, respectively. By
the Equation Vp= ƞ VB1B2 + VD, the ƞ value of the UJT can be obtained.

A resistance increase of VR1 causes the emitter voltage V E to increase. When VE reaches the
value of VP+0.5V, the UJT is turned on and the voltage drop on the resistor R11 should be
about 0.5V. This voltage drives transistor Q3 into conducting so that the LED should be ON.

18
EXPERIMENT 3

UJT Temperature – Control Circuit.

Characteristics

OBJECTIVE
1. Understanding the construction and Characteristics of a UJT.

2. Understanding the operation and two-transistor equivalent of a UJT.

3. Measuring the Characteristics of a UJT.

4. Construction and measuring basic UJT application circuits.

DISUSSION
The uni junction transistor (UJT) was first introduced in 1948 and become commercially
available device from 1952.

19
Diode equivalent circuit of ujt is shown in fig.

The diode represents the p-n junction characteristic between the emitter and base bar.

20
RBB =RB1+RB2 │IE=0

The magnitude of RBB is typically from 4 to 10 KΩ.

When IE=0, the voltage droop on the RB1 is determined by the voltage divider rule

VRB1=RB1∕ (RB1+RB2) VB1B2│IE=0= ᶯ(VB1B2)│IE=0

UJT Characteristics

The static Characteristics curve of typical UJT is shown in fig

When the applied emitter voltage is smaller than the peak point voltage the p-n junction at
emitter biase is reverse biaseand only a small leakage current IE0 normally flows in the emitter.

21
This current is measured in uA , corresponds very closely with the reverse leakage current Ico
of conventional bipolar transistor. This region is called cutoff region. When the voltage VE is
increased , a voltage is reached where VE is equal to the sum of the forward voltage droop
across the p-n junction and voltage across RB1.This voltage is called peak point voltage VP.
When the applied VL reaches the peak point voltage the diode will fire and the UJT will conduct
from the cut off region into the resistance region.

There are physical structures of a UJT. The most popular is bar structure. The other type is
cube structure. Both are shown below.

Testing UJT with Ohmmeter

An Ohmmeter, found on analog millimeter ,can be used to check the condition of UJT and to
identify the terminals of UJT.select the range of multimeter 1KΩ,connect the red lead base 2
and black lead base 1. A reading between 4 and 10 KΩ is obtained. Reversing the polarity the
same reading should be obtained. This indicated that IE=0

Description of Experiment Circuit

22
EQUIPMENT REQIUIRED
1- Power Supply Unit KL-51001
2- Isolation Transformer KL-58002
3- Module KL-53001
4- Analog Multimeter
5- Dual Trace Oscilloscope

PROCEDURE

constructing and Measuring UJT Temperature – Control Circuit.

1:Remove the connect plug from position 4 and insert it in position 3 . Turn on the power.
Approach a hot soldering iron to the thermistor RTH . Measure and record the change of VE.
( Properly adjust VR1)

2:Keep heating the RTH. Observe and record the states of UJT and LED.

23
3:Remove the soldering iron from RTH. Observe and record the change of the UJT.

CONCLUSION
In procedure step 5, the measured Vp and Vv should be about 2.5 V and 0.9V, respectively. By
the Equation Vp= ƞ VB1B2 + VD, the ƞ value of the UJT can be obtained.

24
EXPERIMENT 4
UJT light control Characteristics

OBJECTIVE
1. Understanding the construction and Characteristics of a UJT.

2. Understanding the operation and two-transistor equivalent of a UJT.

3. Measuring the Characteristics of a UJT.

4. Construction and measuring basic UJT application circuits.

DISUSSION
The uni junction transistor (UJT) was first introduced in 1948 and become commercially
available device from 1952.

25
Diode equivalent circuit of ujt is shown in fig.

The diode represents the p-n junction characteristic between the emitter and base bar.

RBB =RB1+RB2 │IE=0

The magnitude of RBB is typically from 4 to 10 KΩ.

When IE=0, the voltage droop on the RB1 is determined by the voltage divider rule

26
VRB1=RB1∕ (RB1+RB2) VB1B2│IE=0= ᶯ(VB1B2)│IE=0

UJT Characteristics

The static Characteristics curve of typical UJT is shown in fig

When the applied emitter voltage is smaller than the peak point voltage the p-n junction at
emitter biase is reverse biase and only a small leakage current IE0 normally flows in the emitter.

27
across the p-n junction and voltage across RB1.This voltage is called peak point voltage VP.
When the applied VL reaches the peak point voltage the diode will fire and the UJT will conduct
from the cut off region into the resistance region.

There are physical structures of a UJT. The most popular is bar structure. The other type is
cube structure. Both are shown below.

Testing UJT with Ohmmeter

Description of Experiment Circuit

28
EQUIPMENT REQIUIRED
1- Power Supply Unit KL-51001
2- Isolation Transformer KL-58002
3- Module KL-53001
4- Analog Multimeter
5- Dual Trace Oscilloscope

PROCEDURE
UJT Characteristics using light control Measurement

1:Remove the connect plug from position 3 and insert it in position 2. Cover the CDS window
with your hand. Observe and record the states of UJT and LED. (Properly adjust VR1)

2:Remove your hand from the CDS window to increase sensed light level.

Observe and record the states of UJT and LED.

29
Measuring the Characteristics of Two- Transfer UJT

3:Insert connects plugs in 1, 4, 5 and 7 positions. Set the dual – trace oscilloscope to X- Y
mode

Connect GND of the oscilloscope to the emitter of Q1 , CH1 input to the other terminal of R6,
and CH2 input to the emitter of Q 2. Plot the IE-VE curve on the display of oscilloscope in Table

CONCLUSION
In procedure step 5, the measured Vp and Vv should be about 2.5 V and 0.9V, respectively. By
the Equation Vp= ƞ VB1B2 + VD, the ƞ value of the UJT can be obtained.

30
EXPERIMENT 5
UJT Oscillator and Timer Circuits

OBJECTIVE

1 Understanding the operation of UJT relaxation oscillator circuit

2 Understanding the operation of UJT timer circuit

DISCUSSION
UJT Relaxation Oscillator

Most triggering circuits for SCR and TRIAC triggering use the basic relaxation oscillator
as a pulse generator. Any semiconductor device whose V-l characteristic include a
negative resistance region may be used. The devices usually used the UJT, PUT, SCS,
DIAC, and Shockley diode.

a)Basic UJT Relaxation Oscillator

b)Emitter Voltage

c)Voltage across R1

Fig-3.1

31
Fig shows the circuit and voltage waveforms of the basic UJT relaxation oscillator. When the
switch is closed, the capacitor C charges towards V by current flow through R. The UJT will turn
ON at the point where the capacitor voltage V reaches the peak-point voltage V. The capacitor
then discharge through the E-to-B1 junction of UJT generating a voltage pulse output across
R1.

The amplitude of the output pulse is given by

Vo = l E x R1

When the emitter current decays to the level of the UJT valley-point current, l v ,
the UJT turns off and the capacitor begins to charge again. The cycle repeats
as long as the switch S remains closed. The period of oscillation is quite small
and typically a few micro second.

In fig. 3-1 (b), the voltage waveform of V E is basically an exponential curve. In

+ x
normal operation, the time constant of discharging is equal to ((RB1 R1) CE)
and the time constant of charging is (R E x C E ). Since R E >> (R B 1 +R1) in actual
circuits, therefore (R E x C E )>> ((R B 1 +R1) x C E ).

The period t1 of Fig. 3-1 (b) can be determined by the equation

Since VB1B2>>VD, the above equation can be re-written as

The capacitor charging from Vv to Vp can be expressed as

32
Since RBB>>R2 and VB»Vv in most applications, the above equation can be re-written as

Therefore the charging period t1 can be determined by

From Fig. 3-1 (c), the frequency of output pulse can be calculated by

where t1 is the charging period and t2 the discharging period. The period of
time to complete one cycle is usually defined by T, that is, T=t1+t2. The
capacitor discharges through the emitter of UJT, R B I and R 1 . Since R B I is small
enough to neglect and R E >>R1, the discharging period t2 therefore is quite
small compared with t1. In practice, the frequency of output pulse can be
calculated by the simplified equation:

Besides these two outputs mentioned above, the signal output from the terminal B2 in the UJT
relaxation oscillator circuit of Fig. 3-1 (a) is also available if necessary. Fig. 4-2 shows the
voltage waveforms of a UJT relaxation oscillator corresponding to the terminals of

33
UJT. In Fig. 3-2(b), the output waveform at B1 is a positive-going pulse train commonly used to
trigger thyristor devices such as SCR and TRIAC. The output waveform at B2

shown in Fig. 3-2(b) is a negative-going pulse train opposite to B1 output. The emitter output is
a sawtooth wave as shown in Fig. 3-2(d).

Now revert to Fig. 3-2(a). By applying the supply voltage V B so that B2 is positive, a small
current will flow between B2 and B1 as determined by the interbase resistor (R BB=RBI + RB2) ,
R1 , and R2, thus IB2=VB/(RBB+R1+R2). When the emitter voltage VE (the CE voltage) reaches the
peak voltage VP , the UJT switches on. The CE discharging current (IE) abruptly increases to
maximum that causes RB1 to decrease and IB2 to increase. The result is a decrease in B2
voltage caused by an increase in voltage drop across R 2 . At the end of discharging period the
UJT switches off so that the B2 output returns to initial potential. Thus the output waveform at
the terminal B2 is a negative pulse as shown in fig 3.2(b)

The resistor R2 is used for the temperature compensation and will be discussed later

34
Design of UJT Relaxation Oscillator

As mentioned above, the UJT in a relaxation oscillator circuit should operate in negative
resistance region. When designing a UJT relaxation oscillator, the load line must be designed to
pass through the static V E-IE curve in the negative resistance region as shown the load line 3 in
Fig 3-10. The design procedure steps are listed below

(1) Determining RE
The resistor RE must be chosen to ensure that the RE load line may intersect the UJT
characteristic curve in the negative resistance region. To meet this condition, the applied
voltage VB must be large enough to turn the UJT on, and the capacitor charging current must
be larger than the peak-point current Ip. The maximum R E is determined by the following
equation.

The RE(max) load line is the load line 1 shown in Fig. 3-10. The actual value of R E should be
chosen smaller than RE(max). If RE is too small to ensure the discharging current smaller

35
than the valley current lv, the UJT will operate in the saturation region (load line 2) and can not
be turned off. To ensure turning off, the minimum RE should be

The range of RF is therefore limited between RE(max) and RE(min). In general, the value of 2 or 3
times RE(min) is a reasonable value of RE to locate the load line in the negative resistance region.

2) Determining CE

Before determining the capacitor value, we first discuss the path of operation of
the UJT in the relaxation oscillator circuit to examine the effect of the charging
capacitor.

Fig. 3-11 shows the static V E -I E characteristic of the UJT discussed previously
and the dynamic path of operation. When the capacitor voltage reaches Vp
(point B), the UJT goes on and intends to operate at the point of intersection of
the corresponding load line with the device characteristic in the negative
resistance region. Since the capacitor voltage can not drop abruptly, thus the
operating point would be an abrupt transition at constant voltage to point C. The
time interval from B to C is called the turn-on time of the UJT and typically less
than one micro second.

3) Determining R1
The principal purpose of resistor R1 connected to B1 is to determine the voltage output In most
applications, R1 is chosen to less than 100 ohm; however, R1 value as high as 2-3Kohm is also
used in some special designs.

Generally the required output voltage across R1 depends upon the need of the load. For
example, a UJT relaxation oscillator is used to trigger a SCR, which needs a minimum trigger
voltage of 3V. In such a case, the output voltage across R1 should be larger than 3V.
The value of R1 can be calculated by

36
4) Determining R2
The UJT, like most semiconductor devices, is sensitive to temperature variation. The resistor R2
in B2 lead provides thermal stability for the oscillator From (2-3), we observe that the peak
voltage VP varies as VB1B2 , Eta and VD vary with temperature Therefore the oscillating
frequency of the UJT relaxation oscillator will vary with temperature variations
To obtain a stable and precise oscillating frequency, some techniques for
temperature compensation or thermal stability must be considered in a UJT
oscillator In practice, the most popular technique is that an appropriate resistor
simply connected to terminal B2.

There are a variety of UJT parameters affected by the temperature variation

such as the interbase resistance RBBl emitter reverse current lEO, peak voltage
and current, valley voltage and current, and eta and VD, etc. A precise
formulation of the R2 value to be used is quite complex due to the number of
UJT parameters involved. Motorola’s engineers report that an empirically
derived

37
Equipment Required
1- Power Supply Unit KL-51001 , KL-58002
1- Isolation Transformer KL-58002
1- Module KL-53001
1- Oscilloscope
1- Multimeter

Procedure
1- Connect AC110V input of Power Supply Unit KL-51001 , KL-58002 to AC
outlet using AC power cord. Turn on the power. Using the multimeter,
measure and ensure the ac output voltages and +5Vdc and +12Vdc
properly.
2- Referring to the circuit of Fig. 3-19, set S1 on Module KL-53001 to OFF.
Connect DC112V input to +12V output of Power Supply Unit using test
leads.
3- Insert connect plugs in position 1, 4, 7, 8, 11, 12, and 14. Turn VR2 fully
CCW to get the minimum value.
4- Switch S1 to ON position. Using the oscilloscope, measure and record the
output pulse at B1 in Table 3-1. Measure and record the period of
oscillation.
T=_____________________

(Note: If no oscillation occurs, slowly turn VR2 to the right until a visible
waveform is present.)
5- Using the oscilloscope, measure and record the voltage waveform at the
emitter of the UJT in Table 3-1. Measure and record the period of
oscillation. T=________________________

Do these two results of T agree?______________________

6- Turn VR2 fully CW. Observe and record the states of LED and buzzer.
LED_________________; Buzzer ________________________
Using a stopwatch, count and record the OFF time of LED.
T=_____________________________________________________

(If circuit can’t oscillate, turn VR2 CCW slowly.)

38
Table 3-1

_______ B1 E______________
V V

0 T 0 T

7- Observe and record the change of waveforms at E and B1 while turning the VR2 toward
the right.
_______________________________________________________ ___

8- Turn VR2 fully CW. Calculate the period.

T = (VR2 + R4) x C4 =________________________________________
(If circuit can't oscillate turn VR2 CCW slowly.)

9- Using the oscilloscope, measure and record the waveform at B1 in Table 3-2. Measure
and record the period of oscillation.
T=_______________________________

10- Do these two results in step 8 and 9 nearly agree?

__________________________________________________________

11- Measure and record the waveform at E in Table 3-2. Measure and record the period of
oscillation. T=_______________________________
Does this T agree with the T of step 9?
__________________________________________________________________

39
12- From the voltage waveform at E, determine the parameters of UJT.

Vv =___________________V; Vp=_____________________V

Conclusion:
The operation of UJT relaxation oscillator and timer circuits was examined. You have seen the
slight difference between the calculated T and the measured T values. This is caused by the
electrolytic capacitors that exist inherent error of capacitance.

In step 15, you have observed the voltage waveforms across the capacitor and the values of Vv
and Vp. It is a typical manner to obtain the important parameters of UJT from actual output
waveforms.

40
41
EXPERIMENT 6
PUT Characteristics

OBJECTIVE
1. Understanding the construction and Characteristics of a PUT.

2. Understanding the operation and two-transistor equivalent of a PUT.

3. Measuring the Characteristics of a PUT.

4. Construction and measuring basic PUT application circuits.

DISUSSION
The programmable unijunction transtior (PUT) is a four layer PNPN semiconductor device as
shown in fig.

The two transistor equivalent circuit of the PUT is shown in fig below.

42
It is constructed by a PNP and a NPN transistor interconnected as shown in fig.

The emitter of PNP is brought out as anode (A) terminal the collector of NPN as the gate(G),
and the emitter of NPN as the cathode(K). since the gate is closed to the anode , therefore it is
sometimes called the anode-gate. The construction of the PUT is similar to the SCR. The
difference is that the gate of SCR comes from the base of NPN transistor where as in case of
PUT gate comes from N material. The voltage and current ratings of PUT is smaller than that of
SCR. It is commonly used as triggering pulse generator or a low power switch.

PUT Characteristics and Parameters.

43
reverse leakage current IGA flows. As VA increases ,IA increases from negative to zero. When
IA reaches zero the VA at this point called Vs. The Vs infect value of ᶯVBB as defined for the
UJT. However the value of ᶯ of PUT can be programmed by circuit designers.

IGA: The gate anode leakage current is a small reverse current flowing between the gate and
anode It is measured under the condition s of an open circuited and reverse biase A-G junction

Ip:The peak current is the minimum current requires to fire the PUT. In the PUT relaxation
oscillator circuit the current flows in the changing resistor RT must be greater than Ip so that the
PUT can be turned on.

Vs = R1 V, Rg= R1R2

R1+R2 R1+R2

44
Vp :The peak voltage is the voltage value between the anode and cathode when IA=Ip.The Vp
is always greater than Vs

VT: The offset voltage is defined as the voltage difference between Vp and Vs.

Iv: The valley point current is the value of IA before the PUT enters the saturation region. For
the operation of the PUT relaxation Oscillator , the current flowing in RT should be smaller than
Iv.

Vv: The valley voltage is thevoltage between the anode and cathode at IA=Iv.As shown in fig
above , the amount of Vv can be expressed in eq form

Vv=VBE(SAT-PNP)+VCE(SAT-NPN)

It is sum of saturation voltages of both transistors .the Vv value is less than 1V

45
The above fig shows the characteristic of PUT.

If VAK>VGK+VT the B-E junction of the PNP transistor is forward biased so that the transistor
conduct. therefore the PUT operates in ON state. The resistance between A and K is very small
and thus the voltage droop VAK is small

Parameters Affected by the gate network

1.Ip: The Ip vs RG curves of PUT is shown in fig .It can be seen that the peak current Ip is
inversely proportional to the amount of RG.

46
2.Iv: when the PUT is in conduction state , the gate current IG=Vg/Rg flows to the gate .from
the above fig we can see that the valley current Iv is proportional to the gate current IG.

3.Vp: A base voltage divider network is usually used to biased the gate of the PUT.As shown in
the fig below the voltage droop on R2 provides Thevenin equivalent voltage VG is determined
by the voltage divider rule ;that is

VG = R1 (VBB)

R1+R2

Where ᶯ = R1/(R1+R2) as defined for the UJT, and VG=Vp

47
These three parameters discused above are very important in designing the PUT relaxation
oscialltor and can be programmed by designers.

Testing PUT with Ohmmeter

An Ohmmeter, found on analog millimeter, can be used to check the condition of PUT and to
identify the terminals of PUT.

1.set the range selector of the multimeter of R range . connect three red lead to the gate(G) of
the PUT and the black lead to the anode (A). A low R reading should be indicated. Reversing
the polarity will indicate an infinite reading.

2. The resistance B/W G and K is always infinite despite the polarity

3. With G open connect the black lead to the anode (A) and red lead to the cathode (K) and a
low reading is frequently indicated. This is caused by the very high triggering sensitivity of the
gate. If the reading is infinite touching the gate with your finger will cause low resistance
indicated on the scale. Reversing the polarity, the reading will be infinite.

Simulating PUT with two transistors

48
Two silicon complementary transistors connected as shown in fig below. They can simulate the
PUT diode D2 is used to increase the reverse voltage rating. The VR is for the

adjustment of gate triggering sensitivity. The magnitude of VR determines the values if Ip and Iv.

Description of experiment circuit

Above fig shows the experiment circuit on module KL-53002.It consists of the PUT device ,two
transistor equivalent circuit, CDS, RTH, and LED driver.

The power for the circuit comes from 12Vac voltage converted by the half-wave rectifier D1into
the pulsating dc voltage V+. The gate voltage VG of the PUT is determined by the voltage
divider network.

VG= R9V+

VR3+R9

Adjusting VR3 will change the amount of VG. The anode voltage VA is determined by the
voltage divider network consisting of R4,R5,and VR1and expressed as

VA= (VR1+R5)V+

VR1+R5+R4

The value of Va can be controlled by adjusting VR1.

49
When the power is applied and VA<VG, the PUT operates in off state so that both Q3 and LED
are off. By adjusting VR1for VA>VG+0.5V, the PUT conducts and a pulse appear at R8.Thus
Q3and LED are ON.

Transistors Q1 and Q2 form a two transistor equivalent circuit of the PUT. It is used the simulate
the operation of an actual PUT. The transistors Q3 acts as an LED driver and its base signal
comes from the trigger signal across R8.

EQUIPMENT REQUIRED
1-power supply unit KL-51001

1-isolation Transformer KL-58002

1-Module KL-53002

1-analog Multimeter

1-Dual trace Oscilloscope

PROCEDURE
1.Referring to Fig.4-16 , connect AC 12V from Power Supply Unit KL-51001 KL -58002 to
Module KL – 53002.

A.PUT Characteristic Measurement

2.Turn VR 1 and VR3 fully CCW.

3.Insert connect plugs in positions 1 ,4,6,7 and 10. Set the range selector of multimeter
to DCV range. Measure and record the gate – to-ground voltage of the PUT ( the red lead
to terminal G and the black lead to GND.)

Vg=________________ V

4. Adjust VR3 to get Vg=2V.

5. The LED is ____________________ (ON or OFF).

The PUT is operating in _______________ state.

Using the multimeter, measure and record the dc voltage across R8.

Vr8= ___________________V.

6. Using the multimeter , measure and record the anode – to – ground voltage.

50
VA=_____________________V.

7. Slowly turning VR1 to the right (CW), observe the change of Va until the voltage reading
reaches a peak value and abruptly reduces to a valley value. Record the peak and valley
values. The peak an valley values represent the peak and valley voltages of the PUT ,
respectively.

Vp=_____________________V.

Vv=______________________V

8. The LED is ___________________ (ON or OFF ).

The PUT is operating in __________state.

9. Using the multimeter , measure and record the voltage across R8.

Vr8=_________________ V.

10. Turn VR3 to the left (CCW ) to get Vg=3.3v.

At the moment LED is ________________ ( ON or OFF).

Measure Va=____________________ V.

The PUT is in ______________state.

11. Turn VR1 to the right until LED is turned ON.

Measure and record the voltages of Vp and Vv.

Vp=_________________V.

Vv=__________________V.

12. Compare the values of Vp and Vv in steps 7 and 11.

Do they agree ? ______________________________________________

Are the Vp and Vv values variable?____________________________________________

13. Set the dual – trace oscilloscope to X-Y mode. Connect GND to the anode (A) of the PUT ,
CH1 input to the other terminal of R6, and CH2 input to the cathode (K). Observe and plot the
Vak-lad curve on the scope display in Table 4-2.

51
14.Turning VR1 , observe and record the change of Vak- 1ak curve.

15. Turning VR3, observe and record the change of Vak-Iak curve.

CONCLUSION
In procedure step 3 , the measured Vg should be about 4.9 V. Since VG VA, the PUT and
LED are OFF. While increasing the resistance of VR1, the measured Va increases. When Va
reaches Vp=2.5 V, the PUT turns on and a voltage drop of 0.5 V on R8 that drives LED to turn
on. The measured Vv is about 0.9 V.

If Vg= 3V, the PUT will be off since Vg Vv. To turn the PUT on, the value of VA must be
adjusted by VR1 to reach 3.5 V. In such a case , the measured VV should be about 1V.

From this experiment , you should understand that the condition of swiching PUT from off to on
is Va VG+ 0.5V.

52
EXPERIMENT 7
PUT Temperature –Control Circuit.
Characteristics

OBJECTIVE
1. Understanding the construction and Characteristics of a PUT.

2. Understanding the operation and two-transistor equivalent of a PUT.

3. Measuring the Characteristics of a PUT.

4. Construction and measuring basic PUT application circuits.

DISUSSION

The programmable unijunction transtior (PUT) is a four layer PNPN semiconductor device as
shown in fig.

The two transistor equivalent circuit of the PUT is shown in fig below.

53
It is constructed by a PNP and a NPN transistor interconnected as shown in fig.

PUT Characteristics and Parameters.

54
IA reaches zero the VA at this point called Vs. The Vs infect value of ᶯVBB as defined for the
UJT. However the value of ᶯ of PUT can be programmed by circuit designers.

IGA: The gate anode leakage current is a small reverse current flowing between the gate and
anode It is measured under the condition s of an open circuited and reverse biase A-G junction

Ip: The peak current is the minimum current requires to fire the PUT. In the PUT relaxation
oscillator circuit the current flows in the changing resistor RT must be greater than Ip so that the
PUT can be turned on.

Vs = R1 V, Rg= R1R2

R1+R2 R1+R2

Vp :The peak voltage is the voltage value between the anode and cathode when IA=Ip. The Vp
is always greater than Vs

55
VT: The offset voltage is defined as the voltage difference between Vp and Vs.

Iv: The valley point current is the value of IA before the PUT enters the saturation region. For
the operation of the PUT relaxation Oscillator , the current flowing in RT should be smaller than
Iv.

Vv: The valley voltage is the voltage between the anode and cathode at IA=Iv.As shown in fig
above , the amount of Vv can be expressed in eq form

Vv=VBE(SAT-PNP)+VCE(SAT-NPN)

It is sum of saturation voltages of both transistors .the Vv value is less than 1V

56
The above fig shows the characteristic of PUT.

Parameters Affected by the gate network

1.Ip: The Ip vs RG curves of PUT is shown in fig .It can be seen that the peak current Ip is
inversely proportional to the amount of RG.

57
2.Iv: when the PUT is in conduction state , the gate current IG=Vg/Rg flows to the gate .from
the above fig we can see that the valley current Iv is proportional to the gate current IG.

VG = R1 VBB,

R1+R2

Where ᶯ = R1/(R1+R2) as defined for the UJT, and VG=Vp

58
These three parameters discused above are very important in designing the PUT relaxation
oscialltor and can be programmed by designers.

Testing PUT with Ohmmeter

An Ohmmeter, found on analog millimeter, can be used to check the condition of PUT and to
identify the terminals of PUT.

2. The resistance B/W G and K is always infinite despite the polarity

Simulating PUT with two transistors

Two silicon complementary transistors connected as shown in fig below. They can simulate the
PUT diode D2 is used to increase the reverse voltage rating. The VR is for the

59
adjustment of gate triggering sensitivity. The magnitude of VR determines the values if Ip and Iv.

Description of experiment circuit

Above fig shows the experiment circuit on module KL-53002.It consists of the PUT device ,two
transistor equivalent circuit, CDS, RTH, and LED driver.

The power for the circuit comes from 12Vac voltage converted by the half-wave rectifier D1into
the pulsating dc voltage V+, The gate voltage VG of the PUT is determined by the voltage
divider network.

VG= R9V+

VR3+R9

Adjusting VR3 will change the amount of VG. The anode voltage VA is determined by the
voltage divider network consisting of R4,R5,and VR1and expressed as

VA= (VR1+R5)V+

VR1+R5+R4

The value of Va can be controlled by adjusting VR1.

60
When the power is applied and VA<VG, the PUT operates in off state so that both Q3 and LED
are off. By adjusting VR1for VA>VG+0.5V, the PUT conducts and a pulse appear at R8.Thus
Q3and LED are ON.

EQUIPMENT REQUIRED
1-power supply unit KL-51001

1-isolation Transformer KL-58002

1-Module KL-53002

1-analog Multimeter

1-Dual trace Oscilloscope

PROCEDURE
Constructing and Measuring PUT Temperature –Control Circuit.

16.Remove the connect plug from position 4 and insert it in position 3.

17. Adjust VR3 to get Vg= 2.2V.

18. Slowly turn VR1 and stop at the point where the LED is near ON. Measure and record the
voltage of Va

Va=____________________________V.

19. Approach a hot soldering iron to the thermistor RTH. Measure and record the change of Va.

20. Keep heating the RTH. Observe and record the states of PUT and LED.

61
21. Remove the soldering iron from RTH. Observe and record the change of the PUT.

CONCLUSIO N
In procedure step 3 , the measured Vg should be about 4.9 V. Since VG VA, the PUT and
LED are OFF. While increasing the resistance of VR1, the measured Va increases. When Va
reaches Vp=2.5 V, the PUT turns on and a voltage drop of 0.5 V on R8 that drives LED to turn
on. The measured Vv is about 0.9 V.

If Vg= 3V, the PUT will be off since Vg Vv. To turn the PUT on, the value of VA must be
adjusted by VR1 to reach 3.5 V. In such a case , the measured VV should be about 1V.

From this experiment , you should understand that the condition of swiching PUT from off to on
is Va VG+ 0.5V.

62
EXPERIMENT 8
PUT Characteristics light control

OBJECTIVE
1. Understanding the construction and Characteristics of a PUT.

2. Understanding the operation and two-transistor equivalent of a PUT.

3. Measuring the Characteristics of a PUT.

4. Construction and measuring basic PUT application circuits.

DISUSSION
The programmable unijunction transtior (PUT) is a four layer PNPN semiconductor device as
shown in fig.

The two transistor equivalent circuit of the PUT is shown in fig below.

63
It is constructed by a PNP and a NPN transistor interconnected as shown in fig.

PUT Characteristics and Parameters

The Characteristics of the PUT is shown above. It is quite similar to the UJT. An advantage of
the UJT over a corresponding UJT is that the important parameter can be controlled by external
components. Refer to the above fig .At VA=0the PUT operates in OFF state and only small
reverse leakage current IGA flows. As VA increases ,IA increases from negative to zero. When
IA reaches zero the VA at this point called Vs. The Vs infect value of ᶯVBB as defined for the
UJT. However the value of ᶯ of PUT can be programmed by circuit designers.

IGA: The gate anode leakage current is a small reverse current flowing between the gate and
anode It is measured under the condition s of an open circuited and reverse biase A-G junction

64
Ip: The peak current is the minimum current requires to fire the PUT. In the PUT relaxation
oscillator circuit the current flows in the changing resistor RT must be greater than Ip so that the
PUT can be turned on.

Vs = R1 V, Rg= R1R2

R1+R2 R1+R2

Vp :The peak voltage is the voltage value between the anode and cathode when IA=Ip.The Vp
is always greater than Vs

65
VT: The offset voltage is defined as the voltage difference between Vp and Vs.

Iv: The valley point current is the value of IA before the PUT enters the saturation region. For
the operation of the PUT relaxation Oscillator , the current flowing in RT should be smaller than
Iv.

Vv: The valley voltage is the voltage between the anode and cathode at IA=Iv.As shown in fig
above , the amount of Vv can be expressed in eq form

Vv=VBE(SAT-PNP)+VCE(SAT-NPN)

It is sum of saturation voltages of both transistors .the Vv value is less than 1V

66
The above fig shows the characteristic of PUT.

Parameters Affected by the gate network

1.Ip: The Ip vs RG curves of PUT is shown in fig .It can be seen that the peak current Ip is
inversely proportional to the amount of RG.

67
2.Iv: when the PUT is in conduction state , the gate current IG=Vg/Rg flows to the gate .from
the above fig we can see that the valley current Iv is proportional to the gate current IG.

VG = R1 VBB,

R1+R2

Where ᶯ = R1/(R1+R2) as defined for the UJT, and VG=Vp

68
These three parameters discused above are very important in designing the PUT relaxation
oscialltor and can be programmed by designers.

Testing PUT with Ohmmeter

An Ohmmeter, found on analog millimeter, can be used to check the condition of PUT and to
identify the terminals of PUT.

2. The resistance B/W G and K is always infinite despite the polarity

Simulating PUT with two transistors

Two silicon complementary transistors connected as shown in fig below. They can simulate the
PUT diode D2 is used to increase the reverse voltage rating. The VR is for the adjustment of
gate triggering sensitivity. The magnitude of VR determines the values if Ip and Iv.

69
Description of experiment circuit

Above fig shows the experiment circuit on module KL-53002.It consists of the PUT device ,two
transistor equivalent circuit,CDS,RTH,and LED driver.

The power for the circuit comes from 12Vac voltage converted by the half-wave rectifier D1into
the pulsating dc voltage V+,The gate voltage VG of the PUT is determined by the voltage
divider network.

VG= R9V+

VR3+R9

Adjusting VR3 will change the amount of VG. The anode voltage VA is determined by the
voltage divider network consisting of R4,R5,and VR1and expressed as

VA= (VR1+R5)V+

VR1+R5+R4

The value of Va can be controlled by adjusting VR1.

When the power is applied and VA<VG,the PUT operates in off state so that both Q3 and LED
are off.By adjusting VR1for VA>VG+0.5V, the PUT conducts and a pulse appear at R8.Thus
Q3and LED are ON.

70
Transistors Q1 and Q2 form a two transistor equivalent circuit of the PUT. It is used the simulate
the operation of an actual PUT. The transistors Q3 acts as an LED driver and its base signal
comes from the trigger signal across R8.

EQUIPMENT REQUIRED
1-power supply unit KL-51001

1-isolation Transformer KL-58002

1-Module KL-53002

1-analog Multimeter

1-Dual trace Oscilloscope

PROCEDURE
1.Referring to Fig.4-16 , connect AC 12V from Power Supply Unit KL-51001 KL -58002 to
Module KL – 53002.

C. Constructing and Measuring PUT Light – Control Circuit.

22. Remove the connect plug from position 3 and insert it in position 2. Cover the CDS window
with your hand.

23.Repeat steps 17 and 18.

Va=___________________ V.

24. Remove your hand from the CDS window to increase sensed light level. Observe and
record the states of PUT and LED.

D. Measuring the Charactersitics of Two- Transistor PUT.

25.Insert connect plugs in positions 1,4,5,8 and 9. Repeat steps 2 through 13 and plot the
characteristic curve in Table 4-3.

Comparing the curves of Table 4-2 and 4-3 , do they agree?.

71
CONCLUSION
In procedure step 3 , the measured Vg should be about 4.9 V. Since VG VA, the PUT and
LED are OFF. While increasing the resistance of VR1, the measured Va increases. When Va
reaches Vp=2.5 V, the PUT turns on and a voltage drop of 0.5 V on R8 that drives LED to turn
on. The measured Vv is about 0.9 V.

If Vg= 3V, the PUT will be off since Vg Vv. To turn the PUT on, the value of VA must be
adjusted by VR1 to reach 3.5 V. In such a case , the measured VV should be about 1V.

From this experiment , you should understand that the condition of swiching PUT from off to on
is Va VG+ 0.5V.

72
EXPERIMENT NO 9
PUT Oscillator and Timer Circuits

OBJECTIVE
1. Understanding the operations and design of PUT relaxation oscillator
2. Understanding the operation of PUT timer circuit

DISCUSSION
The characteristic of the PUT was discussed in preceding discussion. We focus on the design
and application of the basic PUT relaxation oscillator. The characteristics of the PUT UGT are
similar. Since the PUT is a semiconductor device with the negative resistance characteristics.

At present only a few types of PUT are available in market. These are 2N6027 and 2N6028, and
equivalent types MEU21, and GE types DBT1 and DBT2. We introduce the specification of
2N6027 and 2N6028 in it.

Choice of the PUT type

The first step is to determine the desired frequency of oscillation. The next is to select the PUT
type whose frequency range covers the desired frequencies in your design. From data sheets,
the frequency range of 2N6027 is from 0.1 to 80KHz, whereas 2N6028 type frequency below
10KHz.

Basic PUT Oscillator Circuit

Fig. shows the circuit of basic PUT relaxation oscillator. The following notes are based on this
circuit.

73
Design Notes

1.Considering the frequency stability.

The period of oscillation in fig5.1 can be expressed

t=RTCTln(V-Vp/V+Vp)=RTCTln(V-Vn/V-ηV-VT)

where Vv=valley voltage

Vp= peak voltage

VT= offset voltage

If V>>Vv and ηV>>VT above eq written as

t=RT CT ln(1/1-η)

therefore the greater the supply voltage, the more stable the frequency becomes.

A silicon diode added to the gate shown in fig5.2 improves the efficiency stability of the PUT
oscillator. At the peak point on the characteristics curve of the PUT, forward voltage between
the anode and gate drifts with the temperature coefficient of -2.5mV/degree centigrade . the
variation affects the offset voltage.

74
2 .Determining Ip and Iv

A PUT relaxation oscillator needs a wide range of the negative resistance region for a wide
range of frequencies. In other words, the smaller Ip and Iv as possible are required. But from
fig5.3 we can see that the value of RG must be lagger for a small Ip and RG must be small for a
large Iv.

Fig 5.3 Rg VS lp and lv

Obviously, the adjustment of RG can not meet the requirements of Ip and Iv simultaneously.
When the PUT operates at the peak point, the diode is reverse- biased so that the resistance of
RG can be considered as high as 1Mohm. At the valley point, the diode is forward biased. And
RG=R1/R2 is enough to provide a large Iv.

75
Another technique to obtain a high Iv in fig5.4. in the circuit ,R1 and R2 are enlarged for a low
Ip. Both Q1 and Q2 conduct at the valley point. The current flow in Q2. R3 used is to cut Q2 off
peak point.

In the circuit of Fig.4, the period of oscillation can be expressed as

t= RT CT ln (V-Vv-VBE(Q2)/V-η V-VT)

3.Requirements for oscillation

Refer to fig5.5.the load line should lie in the negative resistance portion on the characteristics
curve to ensure oscillation.

76
In addition, the scope of dynamic load line should be smaller than that of tangent at Q point.

V-Vp/Ip>RT> (V-Vv/Iv)(10+CT/5+CT)

Where CT is measured in nF(10^-9F).the term of (10+CT)/(5+CT) is an empirically derived

equation for 2N6027 and 2N6028. If CT is very high, this term can be considered as 1.

4.Determining RTCT time constant

The maximum and minimum values of RT are expressed. In normal operation, RT value can be
chosen by

RT=1Mohm for f=10Hz,

RT=3Kohm for f= 20Hz

The value of CT should be greater than the 0.001micro farad to minimize the effect of
capacitance between the anode and cathode of the PUT. Fig.6 shows the relationship between
the pulse output voltage and CT value.

5. Determining Rk

The cathode resistor Rk is used to limit the capacitor discharging current and provides the pulse
output. The typical value of RK is calculated by

RK=20+1ohmxCT

where ,CT is measured in micro farad.

6. Determining RG

By Thevenin’s theorem RG=R1//R2=R1xR2/(R1+R2).magnitude of RG determines the values of

Ip and Iv. Two factors are:

The amount of RG is inversely proportional to the power dissipation in oscillator circuit.

Fig.7 shown, the larger the RG the more sensitive to temperature the Ip and Iv become.

77
Design Example for PUT Relaxation Oscillator

We now summarize the design procedure of PUT relaxation oscillator, in table 1 using the circuit
as an example

Table5-1

Procedure Example

1.List requirements of the PUT oscillator such 1.Refering to fig.8 assume that
as:

78
Supply voltage V=? V=12v

Frequency f=? f=1KHz

Max .operating temperature Tmax=? Tmax=50 degree centigrade

Min operating temperature Tmin=? Tmin=-25 degree centigrade

2.select a suitable PUT 2.since f=1KHz, use 2N6027

3.calculate the period of oscillation t=1/f 3.t=1/f=1ms

4.Determine η value and RTCT time constant 4.Pick η=0.63

t=RTCTln(V-Vv/V-ηV-VT) Since V>>6V

in general, Vv=1.0V and VT=0.5V t=RTCT=̃1ms

if η=0.63 and >>6V,then t~= RTCT

5.Determine RT and CT. 5.let RT=100Kohm and

Generally a large RT and small CT are desired. CT=0.01 micro farad

6 .Calculate the currents in R1at peak and valley 6.

points.
I(AP)=12-0.63x12-0.5/100K = 39micro
I(AP)=V-ηV-VT/RT ampere

I(AP)=V-Vv/RT I(AP)=12-1/100K=110 micro ampere

7 .Determine Ip and Iv values under the worst 7.

case.
 Ip(-25 degree centigrade)<39 micro
 Ip(Tmin)< I(AP) ampere
 Iv(Tmax)>I(AV) (10+CT/5+CT)  Iv(50 degree
CT in nanoFarad(10^-9F) centigrade)>110x10+10/5+10 micro
ampere
The worst case: Iv(50 degree centigrade)>147 micro ampere

1. Ip at min. temp
2. Iv at max. temp

8.Determine IP and IV in normal condition 8. From the curve of RG= 10Kohm in fig.7. we

79
obtain

 Ip(25 degree centigrade) <  Ip(25 degree centigrade)<39/2.8 micro

Ip(Tmin)/typical value at Tmin ampere
 Iv(25 degree centigrade) < Ip(25 degree centigrade)< 14 micro ampere
Iv(Tmax)/typical value at Tmax
Typical values of Ip and Iv are found in fig.7a  Iv(25 degree centigrade)>147/0.8
and 7b. micro ampere
Iv(25 degree centigrade)>184 micro ampere
The required RG curve must meet the condition
of RG less than equal to 0.1RT.

9. Determine the RG min. from fig. 3a and the 9.Since Ip(2c)<14 micro ampere, then
condition in step8. RGmin=̃ 700 ohm

RGmin=_________

10. Determine the min value of IG from fig.3b 10. Iv(25 degree centigrade)> 184 micro
and in step 8. Then calculate RG max. ampere

RGmax =̃ηV/IG(min) RGmin= approx 4.5mA

RGmax= 0.63x12/4.5 =1.68 KΩ

11. Select RG value between RG max and RG 11. Use RG =1.2 KΩ

min.

12. Calculate R2 and R1. 12. R2= 1.2Kohm/0.63=1.9kΩ,

R2=RG/η Pick 1.8kohm

R1=(η/1-η)R2 R2=(0.63/1-0.63)x 1.8kohm = 3kohm

13. Draw the circuit. 13. As shown in fig.9

80
Quick Design for UJT Relaxation Oscillator

Table 5.2
quick design for 2N6027(MEU21)
RT\R2(max)\CT 1nF 10nF ≥ 100nF

10K 330 330

12K 330 390

15K 330 390 470

18K 330 390 560

22K 390 470 680

27K 470 560 820

33K 560 680 1K

39K 680 820 1.2K

47K 820 1K 1.5K

56K 1K 1.5K 1.8K

68K 1.2K 1.8K 2.2K

82k 1.5K 2.2K 3.3K

100K 2.2K 3.3K 4.7K

120K 2.7K 3.9K 6.8K

150K 3.3K 4.7K 8.2K

180K 4.7K 6.8K 10K

220K 5.6K 8.2K 12K

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270K 8.2K 12K 18K

330K 12K 18K 27K

390K 18K 27K 39K

470K 22K 33K 47K

560K 33K 47K 68K

680K 47K 68K 100K

820K 68K 100K 120K

1M 82K 120K 180K

Table 2,3 are suitable for these conditions: 1. Supply voltage less than 25V. 2. Ambient temp.
at 25 degree centigrade

At 50 degree centigrade, the values of R2 column must be times 0.7.

If R1 = 1.7 R2, then t=̃ RTCT.

Table 5.3
quick design for 2N6028(MEU22)
RT\R2(max)\CT 1nF 10nF ≥ 100nF
22K 330
27K 300 390
33K 330 470
39K 390 560

82
47K 470 680
56K 390 560 820
68K 470 680 1K
82k 560 820 1.2K
100K 820 1K 1.5K
120K 1K 1.2K 1.8K
150K 1.2K 1.5K 2.2K
180K 1.5K 1.8K 2.7K
220K 2.2K 2.7K 3.3K
270K 2.7K 3.9K 4.7K
330K 3.3K 4.7K 6.8K
390K 4.7K 6.8K 10K
470K 5.6K 8.2K 15K
560K 8.2K 12K 18K
680K 12K 15K 22K
820K 18K 18K 27K
1M 22K 27K 39K
1.5M 33K 47K 68K
2.2M 5.8K 82K 120K

83
PUT Timer circuit

A PUT timer circuit is used a relaxation oscillator with a long period of oscillation. Since the
parameters of PUT are programmable, the design of the PUT timer circuit is more flexible than
UJT.

Its design is similar than PUT relaxation oscillator. Various PUT Timer circuit in fig.10 as shown.

A special timer circuit is shown in fig.11 PUT timer with timing network in the gate circuit.
Operations as

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1.When SW is closed, the anode voltage is calculated by the Voltage-divider formula:

VA=VB x R2/R1+R2= 10V

In it capacitor not change so Vc =0 and VG>VA, Put Off.

2.When the capacitor is charged up VG is reduce to meet VA >VG, the PUT is switches on.
Charging time calculate as

T=RG C ln R1+R2/R2

3.If RG= 1.1 MΩ, the charging time will be

T= 1.1 x10^6 x10x10^-6 In 470+330/330 = 11In2.43 =10sec

Description of Experiment circuit

Fig.12 shows the experiment circuit on Module KL-53002. It is similar to UJT.

85
The Gate voltage of PUT is calculated by voltage divider. The η of the PUT is

η =R10/R9+R10

The function of diode D5 and the resistor R8 are introduced in the circuit of fig.12. as mentioned
above D5 is used to introduce the Ip value for stability. The period of oscillation is calculated by
eq 2. The constant current source consisting of Q1, D3 a D4 provides the charging current to
the capacitor. When the capacitor voltage reaches the peak voltage of the PUT; that is
VA=VG+VT, the PUT is turned on. The period of oscillation is calculated by
T=(R4+VR2)xCxln[1/1-η] . If η= 0.63, then T=(R4+VR2)xC.

When the PUT conducts, the capacitor discharges through PUT and the load resistor R7 so
positive pulse at R7. The pulse drives Q3, LED and buzzer on. Timing switched circuit formed.
The capacitor voltage is therefore a ramp wave with good linearity, the input 18-Vac voltage is
rectified by diodes D1 and D2 followed by a zener diode to supply the required dc voltage of 12
for operation.

EQUIPMENT REQUIRED
1-Power Supply Unit KL-51001

1-Isolation Transformer KL-58002

86
1-Module KL-53002

1-Oscilloscope

PROCEDURE

1. Connect the DC 12-0V input terminals On module to DC12V-0v output terminals on Power
Supply Unit KL-58001, KL-58002. Set S1to off position.

2. Insert connect plugs in position 1, 4,7,9,11, 12, and13. Turn VR2 fully CCW to go the
minimum value.

3. Calculate the value of η of the PUT oscillator by the equation below.

η =R10/R9+R10= 3K/1.8K+3K =0.63

the period of oscillation T= R4 x C4= ______________

4. Turn on the power. Using a stopwatch, count and record the interval from setting S1 ON to
LED and BZ ON.(when T is near ms, it can’t visually saw the reaction of LED. You have to
connect an oscilloscope)

T= _________________

5 . Does the measured T agree with the calculated T? ____________

6. Using the oscilloscope, measure and the record the voltage waveform at the anode(A) and
cathode(K) of the PUT in table 5-4. Measure and record the period of oscillation.

T= ________________

Does this T value agree with the T values in step 3 and step 4

87
Table 5-4

VA VK

7.Slowly turning VR2 toward the right, observe and record the change of T.

When VR2 reaches at the most right end (maximum value), measure and record

Voltage waveforms at the anode (A) and cathode (K) of the PUT of the PUT in

Table 5-5.

Record the period of oscillation. T= ________________

Table 5-5

VA VK

88
8.Calculate the period of oscillation.

T =(VR2 + R4) x C4 = __________________________

9.From Table 5-4, observe and record the values of Vp and Vv.

Vp = ________ V, Vv = _ _V

10.Remove the connect plug from position 7 and insert it in the position 6 or 5. Set S1 to Off and
turn VR2 fully CCW.

11.Repeat step 3 through 9 and record the result in tables 5-6 and 5-7.

Table 5-6

VA VK

89
Table 5-7

VA VK

12. Set S1 to Off position. Turn VR1 fully CCW. Insert connect plugs in positions 1, 4, 7, 8, 9,
10, 11, 12, 13.

13.Repeat the 3 through 9 and record the result in table 5-8 and 5-9.

Table 5-8

VA VK

90
Table 5-9

VA VK

91
CONCLUSION
The resistance between the anode and cathode of PUT in conduction is lower than the
resistance between the emitter and base one of the UJT in conditioning. Therefore the
discharging time is shorter and the pulse voltage on the cathode resistor R7 is higher and
narrower in a PUT Relaxation oscillator. To switch the PUT from off to on state, the anode
current in (VR2+R4) at the peak point be larger than Ip. That is,

(VR2+R4) max= VBB -Vp/Ip

This condition limits the maximum value of charging resistor and lowest frequency of the
oscillation. . To switch the PUT from on to off state, the current flow in (VR2+R4) at valley point
be smaller than Iv. That is,

(VR2+R4) min= VBB -Vv/Iv

92
EXPERIMENT 10
Ramp and staircase Generators

OBJECTIVE
1. Understanding the operation of PUT application circuits.

2. Understanding and measuring the PUT ramp generator.

3.Constructing and measuring the PUT staircase generator.

DISUSSION
PUTs are widely used in industrial electronics circuits as triggering devices for thyristors since
the features of easy to oscillate and good frequency stability.

Wide-Range oscillator Circuit

Below figure shows the PUT relaxation oscillator with two frequencies ranges. The transistor Q2
is used to yield a low Ip and high Iv of the PUT. The gate resistor RG may be as large as
22K(33//68) because Q2 is added. The charging resistor Rt can vary from 100Ω to 2MΩ. when
switch is set to Low position the frequency range is from 1Hz to 2.2KHz. If the switch is at igh
position , the frequencies between 1Hz to 20KHz are thus obtained.

93
Voltage – Controlled Ramp Generator

Fig . shows a voltage –controlled ramp generator circuit. The charging current is provided by the
constant – current source to obtain a ramp voltage with excellent linearity. The input dc control
voltage controls the gate voltage VG so that determines the period of oscillation with a rate of
0.2 ms/V. The period of oscillation is 1ms at Vin=5V.

Low-
Impedance Staircase Generator

The staircase generator with low – impedance output is shown in Fig 6-3. The Darlington – pair
transistors Q4 and Q5 having very high input impedance and very low output impedance are
sued to reduce the load effect. When the first positive pulse is applied to the input of Q1,Q1 and

94
Q2 conduct and charge the capacitor with a constant current. If the input pulse is absent both
Q1 and Q2 are off so that the capacitor ceases to charge. The capacitor voltage will remain at a
fixed level that charged in the duration of the first pulse. This voltage level appears at the output
as indicated in Fig 6-3. If a pulse train is applied to the input in sequence, output as indicated in
Fig.6-3.

Frequency Divider

Fig 6-4 shows the frequency divider circuit. The operation of this circuit is similar to the circuit of
Fig.6-3 except that the pulse output of the frequency divider is taken from the cathode of the
PUT. By applying the positive pulses to the input, capacitor C2 charges up until the capacitor
voltage reaches Vp so that PUT conducts and an output pulse presents at the cathode
resistor.The ratio of the number of input pulses to the number of output pulses is called the
frequency divided ration.

95
Schmitt Trigger

The circuit of Fig.6-5 operates as a Schmitt trigger. The gate voltage Vg is set to 6V by voltage-
divider rule. When the input voltage is larger than 6.8V, the PUT switches on and the output
voltage falls from 6V to Vv. If the input voltage is smaller than 1.5V,the PUT will turn off and the
output voltage returns to 6V.

NAND Circuit

The circuit of Fig.6-6 performs logic NAND function. The PUTs are connected in parallel. When
one of these PUTs is turned on by pressing the button connected to the cathode, other PUTs
cannot be turned on because the Va level is pulled down to Va ^ Vg. Therefore these PUTs
cannot be turned on because the Va level is pulled down to PUT can operate in every minute.

96
PUT / SCR Phase Control Circuit

In Fig 6-7 , the PUT oscillator produces trigger pulse to the gate of the SCR. The operation of
PUT oscillator synchronizes with line voltage to ensure the SCR is triggered at the same voltage
level in each positive half cycle of line voltage. By adjusting the 100-KQ VR, phase – shift
angles from 30 to 160 may be easily achieved.

Overload Protection in DC Power Supply

97
Fig, 7-8 shows a dc power supply circuit with overload protection circuit formed by the PUT.
When the load current exceeds 1A, the voltage drop on 0.47 –Q resistor forward biases the
PUT to conduct. The conducting PUT causes transistor Q2 off so that the load current is cut off.
By pressing reset switch once, the load current is then resumed.

Zero Voltage Switch

In SCR or TRIAC AC static switching circuits, the thyristors are used to turn on and off the AC
power supplied to the loads. When a power circuit is switched on and off highly frequency
components are generated that will cause interference problems. These high frequency
components are generated that will cause interference problems. These high frequency
components are called electromagnetic interference (EMI).

An ideal PUT zero voltage switch circuit is shown in Fig6-9. If switches S is closed , the PUT
can be turned on by gate current flow through diode D1 and resistors R1 and R2.However , as
soon as the line voltage rises above 5V, diode D1 becomes reversed bias and the PUT can no
longer turn-on. Since the gate of the PUT is sampling the SCR anode voltage, this circuit may
be used with any load power factor.

98
Description of Experiment Circuit

Fig 6-10 shows the experiment circuits on Module KL-53003. The module consists of two
circuits : the PUT ramp generator on the left side, and the PUT staircase generator on the right
side. PUT 1 and surrounding components form a relaxation oscillator to generate a ramp output.
Transistor Q1 operates as a constant – current source providing a constant current to charge
C3.When Vc^ VP Put 1 conducts and C3 discharges rapidly. If Vc^ Vv PUT 1 will turn off.
Adjusting VR1 to vary the value of Vg can change the peak voltage Vp so that changing the
slope of ramp.

The PUTS performs the function of staircase generator. The control pulse to the input of the
staircase generator is taken from the cathode of PUT1. When the positive pulse is applied to
the base of Q2.Q2 conducts and causes the constant current source Q3 conducting and
charging to C4. Since the duty cycle of pulse is too small to provide sufficient capacitor voltage
for VA>Vp, the PUT is still off even the first pulse ends. If the capacitor leakage current is
negligible the charged voltage on capacitor will remain before the next pulse appears. The
magnitude of charging current controlled by VR2 determines the step size of staircase wave.
The height of staircase is controlled by the magnitude of Vg adjusted by VR3. Darling pair
transistors Q4 and Q5 provide a sufficient current for driving the next stage.

Experiment Circuits

EQUIPMENT REQUIRED
1-power supply unit KL-51001

1-Isolation Transformer KL-58002

1-Module KL-53003

1-Voltmeter

99
1-Oscilloscope

PROCEDURE
1. Connect AC 18V from poer supply to Module KL-53003 18V,0V.

A.PUT Ramp Generator

2. Turn VR1 to obtain minimum frequency of oscillation. Using the Oscilloscope measure and
record the waveforms of Vc3 and anode voltage of PUT in table. Record period T1. Using the
multimeter, measure and record gate voltage of PUT as VG1.

VG1= ------------------------------

T1= --------------------------------

VC3 VK

3.Turning VR1, observe and record the change in waveform and slope of VC1.

-------------------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------

4. Turn VR1 fully CW. Using the scope measure and record the voltage waveforms of VC3 and
VA in table. Record the period T2. Using the voltmeter , measure and record the gate of PUT1
as VG2.

T2= ------------------------

VG2= ----------------------

100
VC3 VK

5. calculate the slope of the ramp using the equation.

(T1-T2)/(VG1-VG2)= -------------------------------------------------------------

B. PUT staircase generator

6. insert connect plugs in position 1 and 2. Turn VR2 and VR3 fully CCW. Observe the voltage
waveform Vo using the oscilloscope.

7. turning VR1 slowly , observe and record the change of output waveform.

------------------------------------------------------------------------------------------------------------------------------

8. turning VR2 observe and record the output waveform.

------------------------------------------------------------------------------------------------------------------------------

9.turning VR3 observe and record the change of output waveform.

------------------------------------------------------------------------------------------------------------------------------

10. Adjust VRs to display a 5-step staircase with the period of 1ms per step on scope. Plot the
waveform in table

101
Vo

CONCLUSION
From this experiment, you can find that the ramp generator is essentially a PUT relaxation
oscillator with excellent linearity. If the changing current is constant, the gate voltage of the
PUT1 determines the frequency of the oscillation. From the equation
VG=VS(R4+VR1)/(R4+VR1+R3), the gate voltage is adjusting VR1. The slope of the ramp
outside is proportional to the amount of charging current that is collector current of Q1, I C=VS x
R8/(R8+R9)/R6. With an additional transistor connected to C3 in parallel by refering to first
figure on page 79 of experiment 9 given below, this this circuit can operate as an ideal sawtooth
generator.

The stair case generator is usually used in the circuit of transistor curve tracer, which is an
electronic instrument for plotting a set of transistor’s characteristic curves on scope display. The
output staircase voltage provides the base voltages of the transistor under under testing. If this
circuit operates at very low frequency, each step voltage will slightly lower due to the capacitor
leakage current as shown in Figure below.

102
103
EXPERIMENT 11
SCR and RC phase control

OBJECTIVE
1. Understanding the construction and Characteristics of an SCR.

2. Understanding the operation of an SCR.

3. Measuring the SCR with ohmmeter..

4. Understanding the gate triggering modes of SCR.

DISUSSION
The silicon controlled rectifier (SCR) is a most important thyristor in the family of PNPN devices.
It was developed by General electric in 1957. The SCR acts as a switch in an AC power control
circuit.

SCR (a)circuit symbol,(b)PNPN structure

104
SCR operation

The SCR is a PNPN four layer semiconductor device having three terminals: anode Cathode,
and Gate. In the most control applications the control signal is applied between the gate and the
cathode while the load is connected to either the anode or cathode in series. The PNPN four
layer structure of SCR is shown in Fig below. We will discuss the operation of an SCR by two
equivalent transistor circuits.

When the gate is open and a forward voltage is applied between the anode and cathode the
SCR is in off state due to the absence of base currents of transistors Q1 and Q2. In such a
situation only small leakage current flows through the SCR.

If the positive potential is applied to the SCR gate, the potential VG will produce a gate current
IG to turn Q2 on (IG=IB2). The collector current of Q2 will then rise to a value sufficiently large to
turn Q1 on (IB1=IC2). As Q1 turns ON IC1 will increase resulting in corresponding increase in
IB2. The increase in base current for Q2 will result in further increase in IC2. The net result is a
regenerative increase in the collector current of each transistor. Transistors Q1 and Q2 conduct
into saturation in a very short time. The resulting anode to cathode resistance of an SCR is very
small so that a large current flows from the node to cathode. Thus yhe SCR is turned ON.

SCR Characteristics Curves

The basic anode Characteristic of the SCR is shown in fig below for IG=0. The peak reverse
break down voltage is defined as the maximum instantaneous negative voltage (PRV) that
should ever be applied at the anode under any conditions. The value of PRV depends upon the
coefficient of resistance of semiconductor and the thickness of base of PNP transistor. When we
applied reverse voltage is smaller than the PRV value the SCR is in off state and only very small

105
current flows in the anode. if the reverse voltage is greater than PRV a large amount of current
will flow and SCR will damage.

The value of VBo on the ᾇ the value of internal transistor and PRV value is given by

VBO = PRV(1- ᾇ1- ᾇ2)^2

Where n is constant and lies between 2 and 3 for a silicon material. From the equation above it
acan be seen that the magnitude of VBO should be slightly smaller than the PRV rating for an
ideal SCR.

SCR Characteristic

Consider the SCR conducting in its forward conduction region. A decrease in the anode voltage
VAK will cause the anode current to decrease as indicated on the fig below.

106
SCR output Characteristic with variable gate current

SCR parameters and Definations

VRRM: Repetativepeak reverse voltage – this represents the maximum reverse voltage that cann
be repeditly applied to the SCR with the gate circuit open and stillblock current flow.

VRSM : Nn repetive peak reverse voltage – this represents the maximum transient reverse
voltage level that should be applied to SCR under reverse blocking conditions with the gate
circuit open.

VGFM: Peak farward gate voltage – This represents the maximum farward voltage that should be
applied at the gate.

VCRM: Peak reversee gate voltage- This represents the maximum reverse voltage that should be
applied at the gate.

VGT:DC gate trigger voltage – This represents the dc voltage applied to the gate and the
cathode required to producing the gate trigger current.

VF:Instantaneous farward voltage droop- this represents the voltage droop between the anode
and the cathode when the SCR is in ON state.

Miscellaneous

I^2 t: this term describes the maximum, forward , non repetative over current capability of the
SCR.

107
PGM: The maximum Instantaneous product of gate current and gate voltage allowed to exist
during any of the forward biase conditions.

Td: Delay time-the time interval B/W the 10% point of leading edge of the gate current pulse
and the 10% point of anode current wave form.

Tr: Rise time – The time is defined as the time required for the anode current to rise from10% of
its final value to 90%.

SCR Triggering Characteristic

From the Characteristics of SCR mentioned above it can be seen that two conditions must be
met to fire an SCR. That are

(1) Anode voltage should be positive with respect to cathode

(2) Gate voltage should be positive with respect to cathode

We have found that successful gate triggering depends on the satisfaction of three
conditions.

(1) Trigger current and voltage must be with in the triggering area;
(2) Power dissipation in the gate circuit should be minimize
(3) Trigger signal must be properly timed.

SCR Gate triggering

Three basic types of gate triggering signals are usualy used . these are dc dignal pulse and sc
shift signals however pulse triggering is the most popular type.

DC triggering

108
DC triggering signal is rearly used in practical SCR applications. The SCR operating under DC
triggering is shown below.

The current limiting resistance is used to ensure the gate dissaption with in its rating.this circuit
act as a dc switch which uses a low power signal to control a high power load.if a high power
load such as a power relay is used this circuit can control an ac power with a dc signal.

AC phase shift triggering

The basic SCR phase shift control is shown in fig below.

109
The purpose of the ac phase shift circuit is to delay application of triggering voltage at the gate
untill the ac voltage reaches to the phase angle a. This angle is called firing angle.current is
supplied to the load for the remaining portion of the positive anode voltage. This portion of the
positive anode cycle, when load current flows , 0, is called conduction angle.

The phase angle B/W Vout and Vin is delay angle , a, so from the trinagle

tan(a)=VR/Vout=IR/IXC = R/Xc = R/1/wc=Rwc

where R= resistance in ohms

C=capacitance in farads

W=radian frequency

From the above eq it is clear that when R and C increases , a increase and when R and C
decreases , a decreases.

Pulse triggering

The gate to cathode junction of an SCR is essentially a PN junction. When ever voltage is
applied at the junction such that the farward biase is achieved, current flows across the junction
and power is disipated in the form of heat.Gate power dissaption can be minimize by using a
pulse triggering sorce.

110
The above fig shows the relationship of the line voltage,anode voltage and triggering pulse in
the ac controlled SCR circuit.One precaution that must be taken in applying pulse sources at the
gate of SCR is that the reverse biase limait of the gate is not exceeded.A common technique for
limiting the negative voltage at the gate is to clamp the gate to the forward droop across a
diode.

Clamping the gate reverse biase with a rectifier diode

Turn ON SCR

An SCR may br triggered into conduction by

(1) Applying a positive trigger signal to the gate

(2) Exceeding the anode forward blocking voltage
(3) Exceeding the maximum allowable temperature
(4) Excessive rate of change of anode voltage

SCR protection

To obtain satisfactory operation of SCRs and their associated equipments it is necessary to

provide protection against high voltage transients and over current.

An SCR may be damged by

(1) In on state excessive forward current may be caused by

 Load short circuted
 Energizing current or starting current in an inductive load
 One SCR yurned on in paralled SCR circuit.
(2) Excessive transient current from off to on.
(3) Excessive triggering voltage or current at the gate.

Protection strategies

111
(1) Over current protection :use fuses, breakers or series reactor
(2) Over voltage protection
 Using the SCRwith high voltage rating
 Connecting another SCR or diode in serie

Testing SCR with Ohmmeter

1.set the range selector of ohmmeter to R*100.connect the black lead to G and red lead to K.A
low resistance reading must be indicated by pointer. By reversing the polarities the reading is
infinite.In most cases the anode of SCR is internally connected to heat sink.

2. with gate open set the range selector of ohmmeter ti R*1 position.and connect the black lead
to the anode A and the red lead to the cathode K.the resistance reading should be infinite. At
this time extend the black lead from the anode to the gate,the reading should indicate a low
value.Retract the black lead from the gate and the reading should remain.

3.The above steps can be used to identify the terminals and test the SCR with ohmmeter.

Description of Experiment Circuit

The experiment circuit contains two major parts:dc triggering and ac phase shift triggering.In dc
triggering when the gate voltage of SCR id 0V, the SCR is inOFF state.if the increase in the
resistance of VR1 rises the gate voltage VG to reach a sufficent level the SCR will be turn
on.when the SCR turns on the gate voltage is not able to turn off.

The basic network , (VR2+R5) and C3 performs the function of ac phase shifting. The OPAMP
U1 is used as a differential amplifier to amplify the differential out put of bridge network.

112
EQUIPMENT REQUIRED
1-power supply unit KL-51001

1-isolation Transformer KL-58002

1-Module KL-53003

1-analog Multimeter

1-Dual trace Oscilloscope

PROCEDURE
1.Set the range selector of the ohmmeter to Rx1 position. Connect the black lead to terminal A
and the red lead to terminal G. Read and record the reading indicated by the pointer.
Rag=_______________________. Reversing the lead, Rag=________________.

2. Connect the black lead to terminal G and the red lead to terminal K. Read and record the
reading indicated by the pointer.

Rgk=_____________________.

3.Connect the black lead to A and the red lead to K. Read and record the reading indicated by
the pointer. Rak=___________________ . Reversing the leades,
Rak=_____________________.

113
4.Connect the black lead to A and the red lead to K. connecting G to A with a wire, read and
record the resistance reading indicated by the pointer. Rak=______________________

The SCR is __________________(go or no go).

Read and record the voltage reading on LV scale as the forward voltage drop between the
anode and cathode.

Vak=________________________V.

5. Connect 12 VDC and 18 VAC power supplies to Module KL- 53003. Place the 12-V lamp in
RL socket.

6. Turn VR1 fully CCW and insert connect plugs in positions 1,3 and 7.

7. Observe and record the state of RL________________________. Using the voltmeter ,

measure and record the anode and gate voltages. Va=

______________________V

Vg=_______________________V

The SCR is operating in ___________________( on or off ) state.

8.Slowly turning VR1 the right , observe and record the change of Vg.

When the lamp lights, measure and record the gate voltage.

Vg=___________________V.

The SCR is operating in ___________________( on or off ) state.

9. Using the voltmeter m measure and record the anode voltage of the SCR. This voltage is the
forward voltage drop (Vf) between the anode and cathode of the SCR.

Vf=_______________________V.

10. Turn VR1 fully CW.Observe and record the states of RL and SCR.

Turn VR1 fully CCW.Observe and record the states of RL and SCR.

Explain the
changes.___________________________________________________________________

____________________________________________________________________________
_________.

11.Remove the connect plugs form position 1 and then insert it back.Observe and record the
states of RL and SCR.

114
12.Remove connect plugs from positions 1 and 3. Insert conncet plugs in positions 2,4 and
7.Using the oscilloscope , measure the voltage waveform across RL.Turning VR2, observe and
record the changes of the SCR conduction angle and lamp brightness.

13. Turn VR2 to get maximum conduction angle.

U=___________________________degress.

Using the oscilloscope , measure and record the voltage wavefroms of Vg and Vk in Table 7-1.

Table 7-1

VG Vk

14.Remove connect plug from position 7. Insert conncet plugs in positions 5.6.8 and 9. Using
the oscilloscope , measure the voltage waveform across RL.Turning VR2, observe and record
the changes of the SCR conduction anlge and lamp brightness.

115
15.Adjust VR2 to get the conduction angle to 90 degrees . Measure and record the voltage
waveforms of Vg and Vk in Table 7-2.

VG Vk

16. Remove the connect plug from position 9. Observe and record the changes of Vg and Vk.

_________________________________________________________________________

CONCLUSION.
You have experimented the dc triggering and ac phase shift triggering for the SCR. When and
SCR operate in dc voltage to the gate will turn on the SCR. The conducting SCR remains in on
state even the gate signal is removed. When ad voltage is applied, the SCR is turned on by the
gate triggering signal and is automatically turend off when the applied ac voltage reduces to
zero voltage on each half cycle.

116
EXPERIMENT NO 12
AUTOMATIC LAMP AND DIMMING CIRCUITS

OBJECTIVE
 Understand the operation of TRIAC and SCR phase control.
 Understand the operation of DIAC-TRIAC phase control circuit.
 Performing an automatic lamp dimming control.

DISCUSSION
TRIAC Phase Control:

1-RC phase control

TRIAC often used in an AC circuits to control power on load. It can operate in full – wave
phase control circuits while an SCR can operate in half-wave phase control
circuits.TRIAC is more convenient in AC applications.

In RC V c lags behind Vtt and angle depending upon RC time constant.

117
The most elementary form of full-wave phase control is the DIAC-TRIAC circuit. DIAC and
TRIAC turns on with capacitor voltage (Bleak over voltage).

2-Phase control with pulse triggering

The pulse triggering is generated by a UJT relaxation oscillator and coupled by transformer to

the gate of the TRIAC

Circuit diagram

118
.EQUIPMENT REQUIRED
 Power supply unit KL-51001
 Isolation transformer KL-58002
 Module KL-53007
 Oscilloscope

PROCEDURE:

1. Connect 110 VAC power supply from KL-51001, KL-58002 to module KL-53007.
Install the lamp in the socket on module.

2. Insert plugs in positions 1,4,5,9 .Turning VR1 randomly observe and record change of
lamp brightness.

3. Set VR1 at mid position. Measure and record the voltage waveforms of SCR anode and
capacitor C1.

119
SCR-1 Vc1

4. Remove the connect plug from position 9 and insert in position 12. Repeat steps 2
and 3.

Record the results in table.

TRIAC-T2 Vc1

5. Remove all plugs and insert them in positions 1,4, 6 and 10.Repeat steps 2 and 3. Record
results in table.

SCR -A Vc1

120
6. Remove the connect plug from position 10 and insert in 11. Repeat steps 2 and 3. Record
results in table.

TRIAC-T2 Vc1

121
7. Insert plugs in position 2,4,8 and 9. Turning VR1,observe and record the change of lamp
brightness.

8. Set VR1 to its mid position. Measure and record voltage waveforms of SCR anode and the
capacitor C2 in table.

SCR-A Vc2

9. Remove plug from position 9 and insert in 12. Repeat steps 7 and 8 and record the results.

TRIAc-T2 Vc2

122
10. Insert plugs in positions 2,4,7 and 10.Repeat steps 7 and 8 and record results.

SCR-A Vc2

123
11. Remove plug from position10 and insert in 11. Record the results.

TRIAC-2 Vc2

12. Which of the trigger circuit is the best?

Which of the power control circuit has maximum power output?

124
13. Insert plugs in positions 1 , 3 ,6 and 11. Expose CDS to normal light level. Adjust VR1to
keep TRIAC in off state before conducting.

14. Cover CDS window with your hand . Observe and record states of lamp , DIAC and
TRIAC.

15. Remove your hand from CDS and observe state of lamp, DIAC and TRIAC.

CONCLUSION
You have experimented the automatic lamp dimming control. Single section of RC phase
shifting may cause hysteresis phenomenon. This effect can be eliminated by adding an RC
network in series.

Since SCR conducts only during the positive half cycle of line voltage, the power deleivered to
the load is smaller than the TRIAC control circuit. This effevt has been demonstrated by
measuring the load voltages and observing the brightness of the lamp. By the way, the CSD
light control circuit can be used as a street light control circuit.

125
EXPERIMENT 13
DIAC AND TRIAC Characteristics

OBJECTIVE
 Understanding and measuring the characteristics of TRIAC.
 Understanding and measuring the characteristics of DIAC.
 Performing the DIAC-TRIAC phase control circuit.

DISCUSSION
TRIAC Characteristics

The triode AC switch (TRIAC) , sometime called triggering bidirectional thyristor, is a three-
terminal semiconductor device used in AC power control applications. The operation of the
TRIAC in AC circuits can be considered as inverse parallel SCRs in AC circuits. Either positive
or negative voltage is applied to MT2 terminal, the TRIAC can be turned on by applying the gate
triggering signal. There are many types of TRIACs available in market such as low power type
of RCA 2N5754 (2.5A, 100V) and high power type of RCA 40924 (80A, 600V).

TRIAC Construction

The TRIAC device was developed by General Electric. Fig. 13-1 (a) shows the cross section of
TRIAC. The region between terminals MT2 and MT1 is a PNPN switch in parallel with an NPNP
switch. The circuit symbol of TRIAC is shown in Fig. 13-1(b). Its terminals are main terminal #2

126
(MT2) or anode 2, terminal #1 (MT1) or anode 1, and gate. A practical structure of TRIAC is
shown in Fig. 13-2.

(a) MT2 positive or negative, gate circuit open

In this mode the junctions P1-N1 and N1-P2 are reverse-biased. The TRIAC is turned off.

(b) MT2 positive, positive gate current

In this mode the TRIAC behaves strictly like an SCR. Active parts are P1-N1-P2-N2 and the
gate current flows through G-P2-N2-MT1.

(c) MT2 positive, negative gate current

Operation is analogous to the junction gate thyristor. P1-N1-P2-N2 is the main structure, with
N3 acting as the junction gate region.

(d) MT2 negative, positive gate current

P2-N2 is forward biased and injects electrons, which are collected by P2-N1.
P2-N1 becomes more forward biased. Current through the P2-N1-P1-N4 portion increase and
this section switches on. This mode, too, is also analogous to remote gate operation.

(e) MT2 negative, negative gate current

Remote gate mode, P2-N1-P1-N4 is the main structure, with junction P2-N3 injecting electrons,
which are collected by the P2-N1 junction.

TRIAC Characteristics

The TRIAC performs the function of the inverse parallel SCRs configuration. Fig.13-3(a) shows
the anode characteristic of the TRIAC under zero gate current condition. The TRIAC will block
voltage of either polarity so long as the magnitude of the voltage is less the forward breakover
voltage, VBOR or VFOM. The anode current is limited to a very low leakage level, usually less than
a few milliamperes under forward blocking conditions. There is no reverse voltage specification

127
for the TRIAC. Parameters VFOM PFV, VDRM, and VBR are defined exactly the same as SCR
specifications.

From Fig. 13-3(b), it is tound that the voltage applied to the gate of TRIAC has no limitation in
polarity. The breakover voltage reduces as the gate current increases. The control of firing
angle for a TRIAC on each half cycle of ac source is similar to the SCR. Fig. 13-4(a) is a typical
TRIAC control circuit. Fig. 13-4(c) shows the load current waveform, the conduction angle 0,
and the firing angle a. The total conduction angle is the sum of 01 and 02.

The operation of TRIAC is similar to two SCRs connected in reverse parallel. An operation
summary of the TRIAC is indicated below:

128
(1) With the gate open. The TRIAC will be in off-state as long as the MT2-to-MT1 voltage is less the
forward breakover voltage.

(2) When MT2-MT1 voltage is over 1.5 volts, the TRIAC can be triggered to conduct by applying a
gate triggering signal.
(3) The gate signal can not control the TRIAC operating in on state.
(4) One method to turn off the TRIAC is to reduce the MT2 current below the holding current l H,
typically a few microamperes. TRIAC will turn off at the end of each half cycle in AC circuits.

(5) The gate signal to turn TRIAC on has no limitation in polarity. The magnitude of triffering current
depends upon the polarity of triggering voltage.
(6) The MT2-to-MT1 voltage reduces to a small value of about 1.5V when TRIAC turns on.

Triggering Characteristics of TRIAC

The difference between TRIAC and SCR triggering is in the polarity of gate triggering signals.
The SCR is triggered by applying a positive gate signal when the anode voltage is positive. The
TRIAC can be triggered under four gate conditions:

 I+ :MT2 positive, VG positive

 I- :MT2 positive, VG negative
 III+ : MT2 negative, VG positive
 III- : MT2 negative, VG negative

Fig. 13-5 shows the typical triggering requirements for TRIAC. The gate currents required
triggering a TRIAC in I+ and III- modes are equal: That is , the same gate current is required
when the gate and MT1 voltage are in same polarity. Notice that the gate current required to
trigger in the I- and III+ modes is higher than the gate current required to trigger in the I+ and III-
modes under the same conditions. The significance of this property is that given a symmetrical
gate triggering source, either I+ and III- and I- and III+ modes should be used in order to get
symmetrical triggering. Other combinations will result in a1 being different than a2 and
asymmetrical load current.

129
The turn-on time of TRIAC, typically 10us, like that of SCR, slightly varies with the amount of the
gate triggering current. That is, the greater the gate current, the smaller the turn-on time.

Static Measurement for TRIAC

The appearance of a TRIAC is very similar to an SCR. An ohmmeter can be used to identify
these two devices and if a TRIAC can work properly. The Procedure and results of testing a
TRIAC with an ohmmeter are shown in Tabel 13-1.

(1) Connect the black lead of ohmmeter to terminal T2 and the red lead to T1 as shown in Fig. 13-6
The resistance reading should be infinite.

130
(2) Extend the black lead to touch the gate and retract it back. The reading should be indicated
about 10Q as shown in Fig. 13.7

DIAC Construction and Characteristics

The di-electrode AC switch (DIAC) is three-layer NPN semiconductor device used as a trigger
device for TRIAC in AC circuits. The circuit symbols and structure are shown in Fig. 13.8

Fig. 13-9 shows the V-I characteristics of the DIAC. When the voltage applied to the terminals is
less than the breakover voltage VBO, the DIAC will turn on and the voltage drop between two
terminals will reduce to about 10V. The VBO value of the DIAC lies between 20V and 40V.

131
Two Transistors Simulating DIAC

Two-transistor configuration can be used to simulate the operation and characteristics of the
DIAC. we first recall and focus on the break down characteristics of conventional BJTs as
follows.

VCBO: The collector-to-base reverse breakdown voltage with the emitter open, shown in fig. 13-
11(a), is the maximum breakdown voltage of transistor (see Fig. 13-10). When breakdown
occurs, the characteristic is like a zener diode.

Fig. 13-10 Comparison among breakdown voltages of transistor

VECO: The collector-to-emitter breakdown voltage is measured with the base open as shown
Fig. 13-11(b). As shown in Fig. 13-10, the value of VCEO is less than the value of VCBO.

VCES: The Collector-to-emitter breakdown voltage is measured with the base and emitter
connected together as shown in Fig. 13-11(c). VCES=VCBO.

132
VCER: The collector-to-emitter breakdown voltage is measured with connecting a resistor in
parallel between the base and emitter terminals. As shown in Fig. 13-10, when the applied
voltage reaches VCBO, the first breakdown occurs and then the voltage reduces of V CEO called the
second breakdown as the current increases. This Characteristic is the same as that of DIAC.
The magnitude of VCER depends upon the resistance between the base and emitter. For a
large R the VCER is close to VCEO and is close to VCES for small R.

Two NPN transistors connected as shown in Fig. 13-12 form a simulating circuit of DIAC. The V-
I characteristics are similar to the DIAC. The breakdown voltage VCBO of transistors should be
less than 30 volts.

DIAC Operation and Testing

The DIAC with negative resistance characteristic can be used in relaxation oscillator circuit. As
shown in Fig. 13-13 (a), the DIAC acts as neon tube. When the capacitor voltage is less than

133
the breakover voltage of DIAC. the DIAC is off and the capacitor charges through the resistor R.
If the capacitor voltage reaches VP, DIAC turns on and the capacitor discharges through DIAC.
When the capacitor voltage reduces to VV, DIAC returns to off and a complete cycle is finished.
The voltage waveform is shown in Fig. 13-13(b). Fig. 13-13(c) shows the voltage waveform
when the applied voltage is in reversal polarity.

Fig. 13-13 DIAC relaxation oscillator

Testing a DIAC with an ohmmeter is made as shown in Fig. 13-14, Since the internal battery6
voltage is less than the VBO of DIAC, the resistance reading indicated by the pointer is always
infinite whenever the polarities are.

134
Trigger Circuits of TRIAC

Fig 13-15 shows the simplest TRIAC AC power control circuit. The trigger devices commonly
used in trigger circuit neon tubes, DIACs, and silicon bilateral switch thyristors (SBS).

TRIAC Static Switching Circuits

The TRIAC is suited for the use of AC switches. For the circuit of Fig. 13-16 example, the
control switch is used to supply the triggering voltage to the gate of the TRIAC. When the switch
is set to position 1, gate current flows through R to trigger the TRIAC to conduct. During the
TRIAC in conducting, even the gate current is blocked by switching the switch to position 2 the
TRIAC will remain its on state until the end of the half cycle of AC source.

The RC suppression network also

called snubber circuit connected in
parallel with MT2-MT1 is used to
prevent the damage against the
excessive dv/dt in inductive loads

The circuit of Fig. 13-16 is a hypothetical switching circuit to indicate that the proper gate signal
should be applied to the gate during each half cycle appears at MT2 terminal. Referring to the
circuit of Fig. 13-17,

135
Fig. 13-17 Relationship between the gate signal and AC source

(1) On the positive half cycle of ac supply, the triggering signal to terminal B should be positive to
turn TRIAC on.
(2) On the negative half cycle of ac supply, the triggering signal to terminal B should be negative to
turn TRIAC on.

Fig. 13-18 shows the gate circuit of TRIAC constituted by two diodes and a variable resistor. D1
and D2 are used to control the polarity of gate voltage in positive and negative corresponding to
the applied ac voltage, respectively. The resistor is used to control the gate current level to the
gate of the TRIAC and hence the firing and conduction angles are controlled.

(1) During the positive Half cycle is applied, the positive current through D1 and R1 to the gate
turns on the TRIAC.
(2) During the negative half cycle is applied, the negative current through D1 and R1 to the Gate
turns on the TRIAC.
(3) The Magnitude of R1 determines the amounts of firing angle 0 F and conduction angle 0C of the
TRIAC , see load current waveform.

136
a. When turning R1 toward the right, 0F becomes larger and 0C becomes smaller.
b. When turning R1 toward the left, 0F becomes smaller and 0C becomes larger.

Basic DIAC-TRIAC Phase Control Circuit

Fig. 13-19 shows a basic DIAC-TRIAC phase control circuit. The RR phase shifting circuit is
used to control the firing angle of TRIAC.

Fig. 13-20 shows the voltage waveforms in the circuit of Fig. 13-19. The capacitor voltage V C
lags behind input voltage. When VC reaches the breakover voltage of DIAC (+VP or –VP), the
DIAC and TRIAC are turned on. The ac power is delivered to the load as shown in the shaded
area.

We summarize the operation of the circuit of Fig. 13-19 as follows.

137
(1) The capacitor C1 charges through resistor R1 while C1 discharges through DIAC and the gate
of TRIAC.

(2) To turn on the TRIAC, it is necessary to charge C1 to the potential over the breakover voltages
of the DIAC, +VP and -VP.

(3) If R1C1 time constant is increased by adjusting R1, the firing angle O F will increase and the
conduction angle OC will decrease. Hence the power delivered to the load is decreased.

(4) Inversely, if R1C1 time constant is decreased by adjusting R1, the firing angle O f will increase
and the conduction angle 0C will increase. Hence the power delivered to the load is increased.

(5) R2 and C2 form the snubber circuit to avoid the excessive dv/dt.

(6) This circuit is often used as a light as a light control circuit.

A disadvantage exists in the circuit of Fig. 13-19. It is called hysteresis phenomenon as shown
in Fig. 13-21.

(1) The voltage levels +VP and -VP represent the trigger levels of the DIAC.
The Vc1 waveform is the capacitor voltage without hysteresis.

(2) When R is adjusted to very small, the rate of charging of C1 becomes very fast. This causes the
different capacitor initial voltages at the beginning of each half cycle and hence the DIAC
triggers the TRIAC at different input levels.

(3) The hysteresis phenomenon results in the asymmetrical load voltage as shown.

138
For a resistive load such as a lamp, as shown in Fig. 13-22(a) the hysteresis phenomenon
becomes severely.

(1) When R1 is set to a high resistance to control the lamp in a very weak brightness, turn off the
power. If turning on the power again, TRIAC will not be turned on and hence the lamp is off. R1
should be adjusted again to turn the TRIAC on.

(2) While lamp brightness is increasing slowly, at a specified point the lamp brightness enhances
suddenly. Therefore it can not be controlled smoothly.

There are many ways to improve the hysteresis phenomenon. The circuit of Fig. 13-22(b) is a
simple way. The 10 KQ resistor is used to avoid the charging resistor decreases to zero when
adjusting R. An additional RC network is connected to the DIAC to extend the discharging time.

139
Experiment circuits

Fig. 13-23 shows the circuits used in the experiment. We will use the upper circuit to perform
the characteristic measurements of DIAC and TRIAC. The characteristics of DIAC and TRIAC
have been introduced above in detail. The variable resistor VR2 is used to very the dc voltage to
the gate of the TRIAC for plotting the V-I curve. D1 and C1 are used to supply a dc voltage to
the DIAC from 36-Vac voltage. VR1 is to control the charging current to capacitor C2.

The lower circuit is a DIAC-TRIAC phase control circuit. As mentioned above, this circuit has a
disadvantage of phenomenon. R9 and C4 are used to improve the effect.

EQUIPMENT REQUIRED

1 - Power supply Unit KL-51001

1 – Isolation Transformer KL-58002

1 – Module KL-53006

140
1 – Oscilloscope

PROCEDURE
1. Connect 110VCV and 36VAC supplies from Supply Unit KL-51001 KL-58002 5o Moeul3 KL-
53006. The 36VAC is supplied by connecting two 18VAC supplies in series.
2. Insert connect plugs in positions 2 and 3. Set the oscilloscope to X-Y mode. Connect CH1 input
to ACOV terminal, GND to the other terminal of load R2,and CH2 input to AC36V terminal.
Adjust scope controls to indicate the V-I characteristic on scope display and plot it in Table 13-1.

3. From the V-I curve, DIAC VBO=________________ volts,.the voltage between two anodes =
_________________ bolts.

4. Turn off the power. Remove the connect plug from position 1 and insert it in position 4. Turn on
the power. Measure and record the capacitor voltage of C1 using the multimeter

VC1 = _________________ v

5. Set VR1 to its midposition. Using the oscilloscope, measure and record the voltage waveform
across the capacitor C2 in Table 13-2.

6. From Table 13-2, DIAC VP = ____________ volts: VV = _ volts.

7. Remove the connect plug from position 1 and inset it in position 5. Connect DC 12V supply from
Power Supply Unit to Module KL-53006

141
8. Set Scope to X-Y mode. Connect GND to TRIAC T2 terminal, CH1 input to the other terminal of
load R7, and CH2 input to TRIAC T1 terminal. Adjust scope controls to display V-I characteristic
curve and plot the curve in Table 13-1.

9. Turning VR2, observe and record the change of V-I characteristic.

_______________________________________

10. Plot two V-I curves for VBO =OV and VBO=10V in Table 13-1 and mark the voltage and current
values.

11. Connect AC110V from Power Supply Unit to Module KL-53006. Remover the connect plug from
position 5 and then inset it in position 9. Turing VR3, observe and record the change of lamp
brightness.

___________________________________________

Set VR3 to its midposition. Using the oscilloscope, measure and record the voltage waveforms
of capacitor C3 and TRIAC2 T2 in Table 13-3.

142
12. Remove the connect plug from position 9. Inset connect plugs in positions 7 and 10. Turing
VR3, observe and record the change of lamp brightness.
___________________________________________
Set VR3 to its midposition. Using the oscilloscope, measure and record the voltage waveforms
of capacitor C3 and TRIAC2 T2 in Table 13-4.

13. Remove connect plugs from positions 7 and 10, and insert them in positions 6 and 11. Turning
VR3, observe and record the change of lamp brightness.

Comparing to the result of step 11, is the hysteresis phenomenon improved?

_____________________________________________

143
Set VR3 to its midposition. Using the oscilloscope, measure and record the voltage waveforms
of capacitor C3 and TRIAC2 T2 in Table 13-5.

CONCLUSION
In step 2, you have observed the characteristic curve of the DIAC using the oscilloscope. The
VP and VV values of DIAC are obtained from the waveform of VC2.

The VR2 is used to adjust the magnitude of the gate voltage of the TRIAC1 for TRIAC
characteristic measurement. That is, the greater the VR2 resistance, the greater the gate
current becomes.

The operation of the DIAC-TRIAC phase control circuit is similar to SCR phase control circuit.
By changing VR3xC3 time constant, the conduction angle of TRIAC2 and the output power on
load are regulated. The components R9 and C4 are used to improve the hysteresis
phenomenon found in step11.

144
EXPERIMENT 14 PUT-SCR Power Control

OBJECTIVE
1 Understanding the operation of a PUT-SCR power control circuit
2 Constructing and measuring the automatic light control circuit

DISCUSSION
The PUT is flexible and suitable for the use of relaxation oscillator or delay circuit since its
important parameters are programmable. The SCR is an ideal AC Power switch With
appropriate gate triggering techniques, the SCR performs excellent control function in ac power
circuits. In this experiment. we combine the PUT and SCR to form an ac power control circuit.

Fig. 13-1 shows the PUT-SCR ac power control circuit. The power applied to the PUT oscillator
is a pulsating dc voltage with the peak limited by zener diode. The pulsating dc that comes from
18-V ac input voltage followed by a bridge full-wave rectifier 01-D4 is used to synchronize with
ac line input.

Fig. 13-1 Experiment Circuits

145
The PUT acts as a relaxation oscillator when the gate voltage VG is fixed the PUT switches on if
its anode voltage is greater than Vg Plus Vt. The anode voltage is the capacitor voltage
determined by the charging current and RC timing network. The capacitor charges through R2
and VR1. When the capacitor voltage reaches the value of Vp, the PUT turns on and then a
positive pulse is developed on R4. The positive pulse is applied to the gate of SCR to fire the
SCR.

The RC time constant network determines the period of oscillation. which controls the firing
angle of the SCR. In other words. the longer the time constant, the larger the firing angle
becomes. Since the load is a larnp, the conduction angle of the SCR determines the power
delivered to the load and the brightness.

The CDS connected to the gate of the PUT is used to vary the gate voltage according to the
light level When the CDS is exposed to different light levels, the different gate voltages
determine the variation of the firing angle and therefore the brightness of lamp is controlled by
the light level.

EQUIPMENT REQUIRED
1 - Power Supply Unit KL-51001

1 - Isolation Transformer KL-58002

1 - Module KL-53005

1 - Oscilloscope

1 - Multimeter

1 - 20-W Lamp

PROCEDURE

 1. Connect ac power supplies 18Vac and 130Vac from Power Supply Unit (KL- 51001
KL-58002) to Module KL-53005

 2. Install the 20-W lamp in the socket on KL-53005. Turn VR1 fully CW. Insert connect
plugs in positions 1, 4, 5 and 7.

146
 3. Observe and record the state of LP_________________________________________
Using the multimeter, measure and record the gate voltage of the PUT.
VG = _______________________ V
 4. Slowly turning VR1 to the left. observe and record the state of LP .
_________________________________________________________________________

Stop VR1 at midpoint. Using the oscilloscope measure and record the voltage waveforrn at
the anode of PUT in Table-13-1

Table 13-1

PUT A

0 T

 5. Measure and record the voltage waveforms of PUT cathode and SCR anode in Table
13-2

147
Table 13-2

SCR A PUT K

V V

0 T 0 T

 6. Turn VR1 fully CCW. Observe and record the change of LP brightness.

Measure and record the Voltage waveform of PUT anode in Table 13-3.

Table 13-3

PUT A

0 T

148
 7. Measure and record the voltage waveforms of PUT cathode and SCR anode in Table
13-4

Table 13-4

SCR A PUT K

V V

0 T 0 T

 8. Turn VRI randomly. Observe and record the change of LP brightness.

Is the power on the load controlled by VR13?

 9. Turn VR1 fully CW. Remove the connect plug from position 4 and then insert it in position

3. Repeat steps 3 and 4 and record the result in Table 13-5.

149
Table 13-5

PUT A

0 T

 10. Repeat step 5 and record the results inTable 13-6

Table 13-6

SCR A PUT K

V V

0 T 0 T

 13. Repeat step 6 and record the result in Table 13-7

150
Table 13-7

PUT A

0 T

 12. Repeat step 7 and record the results in Table 13-8

Table 13-8

SCR A PUT K

V V

0 T 0 T

151
 13. Turn VR1 fully CW. Remove the connect plug from position 3 and then insert it in
position 2. Repeat steps 3 through 7. Observe and record the relationship among the
waveforms.
_________________________________________________________________________
_________________________________________________________________________
 14. From the above steps, comment on the relationship between the capacitor and
conduction angle of SCR.
_________________________________________________________________________

 15. Turn VR1 fully CCW. Remove the connect plugs from positions 2 and 4 and
insert in positions 5 and 6.

 16. Expose the CDS to normal light level. Measure and record the gate voltage of
PUT. VG=______________________ V
Adiust VR1 to keep PUT in off state before conducting.
 17. Cover the CDS window with your hand. Is the lamp lighting?
___________________________________________________________________
The PUT and SCR are _______________________(on or off).

 18. Remove your hand from CDS window. Is the lamp lighting?
_________________________________________________________

The PUT and SCR are _______________________(on or off).

CONCLUSION

In this experiment the PUT oscillator is used to trigger the SCR with its pulse output.
The SCR controls the ac power delivered to the load with different conduction
angles. The firing angle is controlled by the RC network in the anode circuit of the
PUT relaxation oscillator Adjusting either VR1 or capacitance can change the RC
time constant. The longer the period, the smaller the power on load becomes.

Automatic light control circuit in this experiment was built by the CDS sensor and
PUT-SCR power control circuit. The CDS changes the gate voltage of PUT in the

152
variation of light level. Therefore, the power on the load is controlled by the light level
automatically.

EXPERIMENT 15 SCR DC Motor

Forward/Reverse Control

OBJECTIVE

1. Understanding the construction and operation of electromagnetic relays.

2. Understanding the turn-off methods of SCRs.

3. Performing the direction of rotation control of a dc motor.

DISCUSSION

SCRs with the features of unidirectional conduction and easy to control are widely used
to control the direction of rotation for dc motors.

Relay Applications

Relays are electrically operated switches. Relays. with the features of amplification and
remote control and signal conversion, are widely used in modern industrial electronic
circuits as remotely controlled mechanical switches to turn on or off a sequence of
events.

An electromagnetic relay utilizes a current through a coil winding to provide a magnetic

field that moves the switch contacts If the current in the coil is sufficient, the magnetic

153
force attracts the armature that moves the movable contact until it touches the
stationary contact. If the current is disappeared from the coil, the movable spring moves
the movable contact apart from the stationary contact. The mechanical construction and
appearance of an electromagnetic relay are shown in Fig 14-1. It consists of the
armature, yoke, coil, core, contacts, springs. The housing either plastic or metal is used
to protect the relay against the damage of foreign objects and the interference of
electromagnetic field.

The commonly used circuit symbols of relays are shown in Fig. 14-2. Either circle or
rectangle in Fig. 14-2(a) represents the relay coil. The normally open contacts are often
abbreviated NO as shown in Fig. 14-2(b). The NO contacts will make when coil is
energized. The normally closed contacts (NC), shown in Fig.14-2(c), will break when the
coil is energized. A combination of two stationary contacts and one movable contact
which engages one stationary contact when the coil is energized and the other
stationary contact when the coil is not energized is called a single-pole double-throw
(SPOT) relay as shown in Fig. 14-2(d). The movable contact is called common contact
abbreviated as C. The normal contact (N) Is NC and the transfer contact (T) is NO.

Fig. 14-1 Electromagnetic relay

154
Fig. 14-2 Circuit symbols of relay

There are three popular driver circuits to control the operation of relay. These are:

(1) DC source driving

Applied a dc voltage to the relay coil will energize the relay as shown in Fig 13-3(a). The
applied voltage a. current must be within the ratings.

(2) Transistor driving

Fig. 14-3(b) shows a transistor driver used to energize the relay. The control signal is
applied to drive the transistor to conduct. The conducting transistor provides sufficient
current to energize the relay.

(3) Thyristor driving

The thyristor such as an SCR can be used to drive a relay in dc circuits as shown in Fig.
14-3(c). In this application a reset switch is often necessary to turn the SCF2 off.

Fig. 14-3 Relay drivers

155
In most applications relays are used in electronic circuits as remotely controlled
mechanical switches used to control a large current load which is isolated with the
signal conditioning circuit. Fig. 14-4 shows an automatic light control circuit which
consists of a relay, CDS, and transistor. R and CDS form a voltage divider to provide a
bias to the base of transistor Q. The value of R is designed to equal ten times CDS
resistance in normal light level. This arrangement causes the transistor off in daylight so
that the lamp off. At night, CDS resistance increases to apply a forward bias driving the
transistor to conduct. The collector current through relay coil energizes the relay and the
common contact is transferred to NO contact so that the lamp lights.

To reverse the direction of rotation of a dc motor, it is simply to reverse the polarity of

applied voltage to the motor. In our experiment circuit we use two electromagnetic
relays to switch the polarity of applied voltage Fig. 14-5 snows a typical electromagnetic
relay with SPDT contacts. When the relay coil has no current flow. COM contact
connects to NC contact. If a sufficient current flows though the relay coil, the COM
contact is pulled to touch with NO contact. Therefore, the relay acts as a switch.

Fig. 14-4 Automatic lamp control circuit

156
Fig. 14-5 Electromagnetic relay

Turn-off of SCR

The turn-off methods of the SCR are discussed in experiment 7. For convenience we
summarize these turn-off methods as follows.

1. Reduce the anode-to-cathode Current IAK below the holding current IH.
2. Short-circuit the anode and cathode terminals
3. Open-circuit the anode-cathode loop
4. Reverse the anode-to-cathode voltage
5. Use self-commutation technique —
In Fig. 14-6, when neither SCR is conducting, there is virtually no charge on the
capacitor C. If a triggering pulse is applied to the gate of the SCR1, current flows
through RL, R1, and SCR1. Current also flows through R2, C, and SCR1 to
charge the capacitor with the polarities of positive at the right-hand side and
negative at the left-hand side. When a gate triggering pulse is applied at the
SCR2, SCR2 conducts — dropping its anode voltage to approximately 1V. The
capacitor voltage is then placed across the anode to cathode of SCR1. This
reverse anode-to-cathode voltage causes SCR1 to turnoff. The capacitor
discharge path is then RL, RI, and SCR2. Current flows through RI and SCR2 to
charge the capacitor to the opposite polarity. The circuit is now ready for a gate
triggering signal at SCR1 and the cycle repeats.

157
Fig. 14-6 SCR self-commutation technique

Description of Experiment Circuit

Fig 14-7 shows a dc motor forward/reverse control circuit. The SCR self-commutation
technique is used in this circuit to control the direction of rotation for a dc motor. When
the instant the dc power is applied, SCRs are off and relays are off. The dc motor does
not run since its two terminals are grounded through relay's NC contacts. If the light to
CDS1 is blocked, the resistance of CDS1 increases to turn SCR1 on and RELAY1 on.
The COM1 transfers to NO1 contact, hence the dc motor runs in forward direction. The
capacitor C1 charges through RELAY2 coil and SCR1. The negative charges are at the
left terminal of C1. When the light to CDS2 is blocked, SCR2 begins to conduct and the
negative potential at SCR1 anode turns SCR1 off. The on SCR2 energizes RELAY2
and hence COM2 transfers to NO2 contact. Therefore the dc motor runs in reverse
direction.

The pushbutton S1 is used to stop the dc motor. The S1 is basically a normally closed
switch. Once S1 is pressed, the SCR in conducting is turned off and the circuit returns
to initial state.

158
Fig. 14-7 Experiment circuit

EQUIPMENT REQUIRED

1 - Power Supply Unit KL-51001

1 - Isolation Transformer KL-58002

1 - Module KL-53006

1 - Multimeter

159
PROCEDURE

 1. Connect DC14V power supply from Power Supply Unit KL-51001 KL-58002 to
Module KL-53006.

 2. At this time the SCR should be off. Observe and record the state of LED.
________________________________________________________________

Using the multimeter. measure and record the anode-to-cathode voltages of

SCR1 and SCR2.

VAk1 = _ V ; VAK2 =____V.

Record the state of each SCR.

___________________________________________________________________

 3. Using the multimeter, measure and record the voltages at COM contacts of
RELAY1 and RELAY2
VCOM1 = _______________ V ; VCOM2 =__________________V.

 4. Using the multimeter. measure and record the voltages across CDS1 and
CDS2.

VCDS1 = _ V ; VCDS2 =____V.

Record the state of each SCR.

___________________________________________________________________

 5 Expose CDS1 to high light level. Measure the voltage across CDS1 using the
ohmmeter. Is this voltage changed? __________________
Measure the anode-to-cathode voltage of SCR1. Is SCR1 on or off?
___________________________________________________________________

Cover COSI window with your hand. Observe and record the state of relay.
___________________________________________________________________

Remove your hand from CDS1 window. Measure the voltage across CDS1 using the
ohmmeter. Is this voltage changed? ______________________________________
Measure the anode-to-cathode voltage of SCR1. Is SCR1 on or off?

160
___________________________________________________________________

Measure and record the voltage at point COM1._____________________________

Does LED2 light?_____________________________________________________

 6. Using the multimeter, measure and record the voltage across the capacitor C1.
VC1 =______________________ V
The polarity of VC1 at the anode terminal of SCR1 is__________________________
(positive or negative).
 7. Cover CDS2 window with your hand. Does the LED2 extinguish?
___________________________________________________________________
Does the LED1 light?
___________________________________________________________________
Using the multimeter, measure the voltage across CDS2 and VAK of SCR2. Is SCR2
on?______________________________________________________
Measure VAK of SCR1. Is SCR1 off? _____________________________________
Measure and record the voltages at relay1 COM1 and relay2 COM2.
VCOM1 = _______________ V; VCOM2 =__________________V.
Remove your hand from CDS2 window. Observe and record the states of SCRs.
___________________________________________________________________
___________________________________________________________________

 8. Using the multimeter, measure and record the Capacitor voltage. The polarity of
capacitor voltage at SCR2 anode terminal is _____________________ (Positive or
negative). V = ________________________________________________________ V

 9. Cover CDS1 window with your hand. Does the LED1 extinguish?
___________________________________________________________________
Does the LED2 light? _________________________________________________

Cover CDS2 window with your hand. Does the LED2 extinguish?
___________________________________________________________________
Does the LED1 light? _________________________________________________
 10. Press S1 to stop motor. Do the LEDs extinguish?

161
___________________________________________________________________

To start motor, cover any CDS with your hand.

CONCLUSION
You have experimented the operation of a dc motor control circuit for the direction of
rotation. The use of CDS is just an application example in this circuit You may use other
sensors or switches to design a control circuit similar to this application.

The self-commutation technique is very useful and widely used to turn off SCRs. For
normal operation the commutation time of the SCR should be short to avoid SCRs
conducting simultaneously. Since the commutation time of an SCR is typically 10µS, it
can be ignored in this circuit.

162
Experiment 16: SCR inverter.

Objective
1. Understanding the operation of SCR inverters.
2. Performing an SCR inverter circuit.

Discussion
An inverter converts dc power at some desire output voltage and frequency. It is widely
used in the fields of stand-by power supplies, uninterruptible power supplies (UPS),
variable-speed ac motor drives, induction heating, and so on.

Since the features of small forward voltage drop, short turn-on and turn -off time, and
high reliability, SCR is commonly used in the inverter applications described above.

SCR inverters are available in power rating as high as kilowatts and in wide dc input
voltages ranging from 15V to 800V.

A SCR inverter circuit is usually accomplished by using two SCR’s. According to circuit
configurations, inverters can be classified into series and parallel inverters. Series
inverters are inverter systems in which reactive elements are placed in series with the
load circuit to provide load commutation. On the contrary, parallel inverters are inverter
systems in which reactive elements are placed in parallel with the load circuit.

Operation of parallel inverter

163
Fig.15-1 shows a parallel inverter circuit. Assume SCR1 conducting and SCR2 blocking.
Current from the DC supply flows through terminals a and b of the transformer primary.
Therefore, an induced voltage in secondary winding supplies to the load.
Autotransformer action produces a voltage of 2E at the anode off SCR2 charging C to 2E
volts with the polarity as shown. When SCR2 is triggered, the cathode of SCR1 rises to
approximately 2E volts, reverse biases SCR1, and turn it off. Capacitor C maintains the
reverse bias for the required turn-off time. When SCR1 is again trigged, the inverter
returns to the first state. It follows that the DC supply current flows alternatively
through each side of the transformer primary producing a square-wave AC voltage at
the secondary.

Fig. 15-1 Basic parallel Inverter

Fig.15-2 shows the voltage and current waveforms in parallel inverter with resistive
load. For understanding the instantaneous operation, the waveforms are plotted by

164
assuming the inverter operating at reasonably high frequency. In practice, the wave
shapes of the output should be nearly square waves.

Fig.15-2 Voltage and current waveforms in the circuit of Fig.15-1

The inductor L in Fig. 15-1 is the di/dt limiting inductor used to ensure that an enough
time is provided for the SCR to be turned off during commutating. The value of L must
be chosen appropriately. If the inductance is chosen too high, the inverter will lose
control in such a case of abrupt load variation.

Parallel inverters with improved Commutation

165
The disadvantage of the SCR inverter described above is that the SCRs will suffer a high
voltage when the load current decreases and the output wave shape is changed from
square to triangle wave. Therefore, a limitation of load variation is necessary.

166
Fig. 15-3 Commutation-improved inverters

The circuits of Fig.15-3 are the inverters with improved commutation. The feature of
these circuits is that the load power is fed through diodes back to dc source. The result
is a smaller commutating capacitor and inductor required. The feedback diodes limit the
load voltage to reach the source voltage. The output voltage waveform is always a
square wave under any load conditions. The resistor connected in series with feedback
diode is used to absorb the stored energy in commutating inductor.

To understand the operation of commutation-modified inverter, we explain the inverter

shown in Fig.15-4 with various loads as follows.

Fig.15-4 Commutation-modified inverter

1. With inductive load

167
The voltage and current waveforms in the circuit of Fig.15-4 with inductive load are
shown in Fig.15-5. For the purpose of analysis, we explain the operation by the following
six intervals.

Fig.15-5 Voltage and current waveforms in the circuit of Fig. 15-4 with inductive load.

(1) Interval A

168
In the circuit of Fig. 15-4, assume that the SCR1 is on and the SCR2 is off. If the value of
di/dt in load is not very high, the potentials at points Z and p can be considered as the
same.

(2) Interval B

When the SCR2 is triggered on, the potential at point Y is rapidly reduced to equal the
potential at point Q. Since the voltage across commutating capacitor C can not be
changed instantaneously, the induced voltage of 2Ed across the commutating inductor
is reverse biased SCR1 to turn off. After the turn-off time to of SCR1, the load current to
is thus supplied by the conducting SCR2.

At the beginning of SCR1 turn off time, the potential at point Z reduces since the
commutating capacitor discharges. When the voltage at Z drops to the potential at Q
point, the commutation time ends. The current in commutating inductor i2 becomes the
maximum value, Im.

(3) Interval C

The current i2 in the commutating inductor now reduces from its maximum value Im. An
induced voltage is thus developed between Z and Y with the positive at terminal Y. when
the potential at point Z’ drops to equal the potential at point Q, feedback diode D2
conducts and causes the commutating inductor L to release the stored energy through
the loop of SCR2, D2, Z and Z’. the time spent for dissipating inductance energy is given
by

lim (1−n)
t=
Edn

169
When this current reduces to zero, load energy will feed through D2 back to dc power
supply. This is because the inductance nature of current lagging voltage. At this time, a
reverse voltage of nEd/(1-n) induced between Z and Z’ forces SCR2 to turn off.

(4) Interval E

Since load feedback current reduces to zero, diode D2 is reverse blased and therefore is
cut off.

(5) Interval A’

In this interval the load current reversed, D2 is still in off state. If SCR2 is gated by a
trigger signal, SCR2 will conduct again. At the end of this interval, the load current is -lo.

The interval B in Fig.15-5 is called the commutating duration. The period of the inverter
is much longer than the turn-off time of an SCR. Assume that SCR is turned on at t=0 and
the load current during commutating duration is Io, then

d i2 i 2 + Io
2 Ed =L +∫ dt
dt C
--------------------(15-1)

Solving the above equation, we yield

2 Ed
i 2= sinωt + I O (2 cosωt −1)
ωL
-------------------(15-2)

Where

1
ω=
√ LC

170
When the voltage across commutating inductor L reduces to 0, the commutating
duration, tc, ends and is expressed by

Ed
tanωtc=
ωL I o
--------------------------------(15-3)

tc=√ LC tan−1
[ √]
Ed C
Io L
--------------------------------

(15-4)

At t=tc, the current i2 is equal to the maximum current Im. The Im can be derived from
Eq. (15-2):

--------------------------------(15-5)
ℑ=2
√ C 2 2
E + I −I
L d o o

The ratio of im to io is given by

Im
=2 √ x +1−1=f (x)
2
Io
--------------------------------(15-6)

Where

√
Ed C
x=
Io L

At, t=to reverse voltage accorss SCR1 is zero to is expressed as

171
to −1 x −1 x
=g ( x ) =sin −sin
√ LC √x 2
+1 2 √ x +1
2

--------------------------------(15-7)

In commutating duration tc, the energy W storaged in commutating inductor is

2
W [ f ( x )]
= ----------------------------------(15-8)
Ed I o t o 2 xg (x)

The relationship among Eqs. (15-6), (15-7) and (15-8) is shown in Fig. 15-6. Fi.15-7 shows
the relationship among commutating capacitance, commutating inductance, and x o.

Fig. 15-6 Relationship among Eqs, (15-6), (15-7) and (15-8)

172
Fig. 15-7 Relationship among commutating capacitance, commutating inductance, and
x o.

In Fig. 15-6, minimum commutation loss is found in the range from x=0.75 to 1.15. in
maximum load condition, If choosing x=1, the values of commutating capacitor and
inductor can be determined by

to Io
C=
0.425 Ed
------------------------(15-9)

173
to Ed
L= ---------------------(15-10)
0.425 I o

2. With capacitive load

Fig. 15-8 shows the voltage and current waveforms in the parallel inverter circuit of
Fig.15-4 with a capacitive load.

Fig.15-8 Voltage and current waveforms in parallel inverter with capacitance load.

174
(1) Interval A

Assume SCR1 conducting and supplying the load current io, D1 conducting to feed the
stored energy in capacitor back to power supply. At the same time, the reverse voltage
between Z and Z’ turns SCR1 off.

(2) Interval B

SCR2 is triggered to turn on. The voltage at point Y drops rapidly to the potential at
point Q. Since the capacitor voltage can not change instantaneously, a reverse voltage
of 2Ed/(1-n) induced between X and Z forces SCR1 to turn off. The turn-off time is given
by

L I o (1−n)
t o= ------------------------------(15-11)
Ed (2−n)

(3) Interval C

Commutating current forces D1 to conduct. Same as the interval B of the inverter with
inductive load.

(4) Interval D

175
Same as the interval C of the inverter with inductive load.

(5) Interval E

Diode D2 stops conducting and load current i2 decreases.

(6) Interval F

Load current reversed

(7) Interval A’

Diode D2 conducts again and load voltage rises.

In parallel inverter circuits, if no trigger signals present, the conducting SCR will cause
the transformer core operating in the state of magnetic saturation. If the period of
trigger pulses is unfair, two SCRs will conduct in unbalance and produces harmonic
components in output wave shapes.

Series Inverter
Series inverters are inverter systems in which reactive elements are places in series with
the load circuit to provide load commutation. The advantages of series inverters include
the following:

1- High reliability
2- Long life
3- Small in volume
4- High efficiency

176
5- Output wave shape near sine wave

Fig. 15-9 Basic series inverter circuit

The circuit of Fig. 15.9 illustrates the basic series inverter. The two halves of the
commutating inductor are equal and tightly coupled by being wound on the same core.
When SCR1 is turned on, the capacitor C charges through L and R and builds up a
positive voltage. When SCR2 is triggered on, the capacitor discharges through SCR2 and
produces a reverse pulsating current in the load. At this time the left L induces a reverse
voltage to turn SCR1 off. The cycle completes and is repeated when the next trigger
pulse comes. Hence, alternate current appears at load.

The waveform of the load voltage in the series inverter depends on the type of load. In
other words, the conduction time of SCR depends on the load. The operation of the
series inverter can be divided into three regions: natural commutating, critical
commutating and forced commutating. During natural commutating, the conducting
SCR is naturally turned off. During critical and forced commutating, the conducting SCR
is forced to turn off by the induced voltage in the commutating inductor. Which region

177
the inverter operating in is dependent on the relationship between the inherent
oscillatory frequency f of series LCR network and inverter frequency f o. If f < fo, the
inverter operates in natural commutation. If f = f o, the inverter operates in critical
commutation. If f > fo, the inverter operates in forced commutation. The operating
frequency of the inverter can be calculated by

√
2
1 1 R
f o= − ----------------------------- (15-12)
2π LC 4 L2

The voltage and current waveforms in the series inverter with the resistive load are
shown in Fig. 15-10.

Fig. 15-10 Voltage and current waveforms for the circuit of Fig. 15-9

When the series inverter operates in over-load or short-circuit load condition, a very
high voltage will be applied to the anode of each SCR. To protect SCRs against high
voltage damage, the circuit of Fig. 15-11 is recommended. In this circuit, if a high current
flow in the load, the high induced voltage across inductor L will cause diode D
conducting and clamping the anode voltage of SCR at a desired value.

178
Fig. 15-11 Voltage protection circuit of inverter

Trigger Source of Inverter

The trigger pulses to the gates of SCRs in the inverter require proper time
interval, sufficient amplitude, and short rise time. For the purposes the trigger sources
are usually from transistor multivibrator outputs, or the flip-flop output of the UJTs and
PUTs. As shown in Fig. 15.12, the trigger signal generator is constituted by a UJT
relaxation oscillator and a transistor bistable multivibrator.

Fig. 15-12 Trigger pulse generator.

179
The circuit of Fig. 15-12 is commonly used to trigger the SCRs in commutation-modified
inverters. This circuit in-fact is a transistor bistable multivibrator with trigger signal from
the output of a UJT relaxation oscillator. In this circuit a negative trigger pulse is taken
from resistor R3 and coupled by capacitor C2 to the base of transistor Q1. The output
pulse of the emitter follower triggers the bistable multivibrator formed by transistor Q2
and Q3. The frequency of the bistable multivibrator should be below a half of inverter
frequency. Pulse transformer is used to couple the output pulses of the flip-flop to the
gates of inverter SCRs. Each trigger pulse is a square wave with positive and negative
polarities. The negative pulse is used to avoid accident triggering for the SCR in off state
and to shorten the turn-off time.

By adjusting the magnitude of the charging resistor R2, the frequencies of the UJT
relaxation oscillator and the bistable multivibrator are changeable.

In order to prevent the transformer against saturation at that instant the inverter
starting, air gaps are considered in designing the transformer core to limit the maximum
flux in the core within the range of a half of saturation flux. This method is useful in
high-frequency inverters. However, bulky transformer should be used in the inverters
operating at 60Hz. The circuit of Fig. 15-13, the trigger pulse generator with high-
frequency starting circuit, provides a good solution for this problem. The operation of
this circuit is explained is follows.

Fig. 15-13 Trigger pulse generator with high-frequency starting circuit

180
In Fig. 15-13, at the instant dc power applied the voltage drop across R11 is
approximately twice the zener voltage of D5. This voltage causes diode D3 conducting
and D4 blocking. Thus the capacitor C1 charges up through D3 and R4. The charging
time to reach the peak voltage of UJT is just a half of normal time. Therefore the
frequency of output pulse is doubled.

The voltage across R11 will decay with the time constant of C5 (R10 + R11). When this
voltage drops to equal the zener voltage, D3 blocking and D4 conducting, the pulse
generator circuit operates in normal condition.

Voltage Regulation of Inverter

Sometimes the inverter is required to hold a constant output voltage independent in
any variations of load. Of-course, changing the magnitude of the commutating capacitor
in parallel inverters can achieve the change in the output voltage; however, it is
impractical.

The inverter output voltage can in general be controlled by the following methods:

1. Regulating the output of the inverter: by applying a voltage regulator between

the inverter output and load.
2. Regulating within the inverter: by connecting several inverters in series and
employing phase control.
3. Regulating the DC supply voltage to the inverter: by using a regulated DC to DC
converter or a phase control rectifier.

Improving Inverter Output Waveform

The required output wave of inverter depends upon the applications. As a sine wave is
required, a low-pass filter is usually used to filter out the higher order harmonics from
the inverter output. The simple filters are shown in Fig. 15-14.

181
Fig. 15-14 Basic LC filters for harmonics

In case if extreme load variations, a complex filter must be employed. There are a
number of factors that must be considered in designing a filter. These include at least
frequency variation and filter loss. The filter shown in Fig. 15-15 can operate in no load
condition and therefore is suited for the applications of extreme load variation. The
resonant frequency of L1-C1 series network is designed to equal the fundamental
frequency of the inverter. The resonant frequency of L2-C2 series network is equal to
the third harmonic frequency of the inverter to bypass 3 rd harmonics. Capacitor C3 is
used to attenuate higher harmonics. Hence, an excellent output with sine-wave is
obtained.

Fig. 15-15 LC filter with series resonance

Fig. 15-16 shows the LC filter with parallel resonance. The effect of the filter is equal to
the circuit of Fig. 15-15. The resonant frequency of the parallel network formed by L1
and C1 is designed to equal the frequency of third harmonic of the inverter. L2 and C2
form a low-pass filter to attenuate higher order-harmonics. The frequency of L3-C2
parallel resonant network equals the fundamental frequency of the inverter. Capacitor
C3 is used to compensate the filter loss.

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Fig. 15-16 LC filter with parallel resonance

Description of Experiment Circuit

Fig. 15-15 Experiment Circuit

Fig. 15.15 shows the SCR inverter circuit in this experiment. The inverter is basically a
parallel inverter with improved commutation as shown in Fig. 15-3(c). The trigger pulses

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are generated by PUT relaxation oscillators. These two PUT relaxation oscillators are the
same. The VR1 is used to adjust the frequency of relaxation, and VR2 is to control the
symmetry of these two oscillators.

SCR1 and SCR2 form the inverter. C4 is the commutating capacitor and L1 is the
commutating inductor. The output waveform of the parallel inverter is a square-wave
on T3 secondary. The low-pass filter consisting of L2 and C5 is used to filter out the
harmonics to output a pseudo sine-wave at about 60Hz.

The bridge full-wave rectifier D3-D6 and capacitor C6 are used to convert the inverter
output ac voltage to dc voltage. In the view of dc source, the DC-to-DC conversion is
known the converter.

Equipment Required
1-Module KL-53013

1-DC Power Supply (30V, 3A)

1-Oscilloscope

1-Multimeter

Procedure
1. Set the DC power supply output to 30V and connect to Module KL-53013.

2. Insert connect plug in position 1. Measure and record the voltage of PUT1 V G=
____________ V, and PUT2 VG= ____________ V.

3. Using the oscilloscope measure and record the voltage waveform of PUT1
anode and PUT2 anode in Table 15-1.

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Table 15-1

PUT1 A PUT2 A

V V

0 T 0
T

4. Using the oscilloscope measure and record the base voltage of transistors Q1
and Q2 in Table 15-2.

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Table 15-2

Q1B Q2B

V V

0 T 0 T

5. Using the oscilloscope, measure and record the voltage waveform of T1

secondary and T2 secondary in Table 15-3.

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Table 15-3

T1 T2

V V

0 T 0 T

6. Turning VR1, observe and record the changes of the above waveforms.
_______________________________________________________________
_______________________________________________________________
_______________________________________________________________
______________________________________________________________

7. Turning VR2, observe and record the relationship between T1 and T2 pulses.

_______________________________________________________________
_______________________________________________________________

8. Turn off the DC power supply. Insert connect plugs in positions 2 and 3. Set
the current output to maximum. Turn on the power.

9. Turn VR2 to its mid-position. Using the multi-meter, measure and record the
voltage across T3 secondary terminals. When turning VR1, fully CW, the
measured voltage is ______________ V. When turning VR1 fully CCW, the
measured voltage is ______________ V.

10. Turning VR2, observe and record the change of the voltage across T2
secondary terminals.

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_______________________________________________________________
_____________________________________________________________
11. Set VR2 to its mid-position. Using the oscilloscope measure the voltage
waveform of T3 secondary and adjust VR1 to obtain the frequency of 60Hz.
Record the result in Table 15-4.

Table 15-4

T3 C5

V V

0 T 0 T

12. Insert connect plug in position 4. Measure and record the maximum and
minimum rms voltages across the capacitor C5.
Vmax = _______________ V; Vmin = _______________ V

13. Using the oscilloscope, measure the voltage waveform across C5 and adjust
VR1 to obtain the frequency of 60Hz. Record the result in Table 15-4.
14. Using the oscilloscope measure and record the anode voltages of SCR1 and
SCR2 in Table 15-5.

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Table 15-5

SCR1 A SCR2 A

V V

0 T 0 T

15. Insert connect plug in position 5. Turn VR1 and observe the state of lamp.
Does the lamp light?

________________________________________________________________

16. Using the oscilloscope, measure the voltage on lead LP. Compare this
waveform with the waveform of T3 secondary and comment on this
difference.

__________________________________________________________________
__________________________________________________________________
__________________________________________________________________
________________________________________________________________

189
17. Insert connect plug in position 6. Remove the connect plug from position 5.
Turn VR1 to get 110Vrms on T4 primary. Measure and record the secondary
voltage of T4 and the dc voltage across C6.

VT4 = V; VC6 = V

Conclusion
You have experimented the operation of SCR inverter. The frequency of trigger pulse is
adjusted by VR1. VR2 is used to set the frequencies of two PUT oscillators equal. The
output waveform of the inverter is square-wave. To obtain a sine-wave, the low pass
filter L2 and C5 should be added. Adjusting VR1, the output voltage of the inverter is
changed from 5V to 120V. The maximum voltage output occurs at 60Hz.

190
EXPERIMENT 17 SCR RECTIFIER CIRCUITS

OBJECTIVE

1. Understanding the operating principles of various SCR rectifier circuits.

2. Implementing and measuring SCR single-phase rectifier circuits.
3. Implementing and measuring SCR three-phase rectifier circuits.

DISCUSSION
Most of electronic equipment and instruments require dc voltages for operation. The dc voltages
are usually obtained from the ac power system either single or three phase AC power sources. In
order to obtain the required dc voltage from ac power source, a dc power supply circuit is
required to convert ac voltage to dc voltage. Generally, a dc power supply circuit consists of
rectifier, filter, voltage regulator and protection circuits.
In this experiment, we will discuss various SCR rectifier circuits and the trigger circuits
providing the gate signals to SCRs.

SCR Single-Phase Rectifiers

Single-phase rectifiers can be divided into three configurations: half-wave rectifier, full-wave
rectifier, and bridge rectifier.

Single-Phase Half-Wave Rectifier

The SCR is a unidirectional conduction device. When the SCR' is reverse-biased by a negative
anode-to-cathode voltage, it Is turned off and no current can flow. When the SCR is forward-
biased by a positive anode-cathode voltage but below the forward break over value, it is turned
off until a positive gate signal with respect to cathode is applied. Once the positive gate signal is
applied, the SCR is turned on and currents can flow from anode to cathode.

Fig 25-1 shows the single-phase half-wave rectifier circuit which uses only an SCR. During the
negative half-cycle of the AC supply voltage. The SCR blocks the flow of load current. During

191
the positive half-cycle of the AC supply voltage, the SCR Is forward-biased and will conduct if
gated. on. If the SCR is turned on, load current will flow and the supply voltage minus the device
drop of approximately one volt is applied to the load.
The trigger signal to the gate is provided by the UJT relaxation oscillator circuit.

Fig. 25-1 Single-phase half wave rectifier

Single-Phase Full-Wave Rectifier

The simplest configuration of the half-wave single-phase rectifier mentioned above is seldom
used in power electronic applications because of the high ripple voltage a content in its output, to
the bridge circuit and, the midpoint circuit. Midpoint rectifiers which are supplied from tapped
transformers. Bridge rectifiers which may be supplied directly from the ac source. When using a
center-tapped power transformer and two SCRs, a single phase a full-wave rectifier is
constructed as shown in Fig. 25-2. During the positive half-cycle of the AC supply voltage,
SCR1 is forward-biased, the upper half-part of the transformer secondary carries the load
currents, the load voltage, and SCR2 is reverse-biased. During the negative half-cycle of the AC
supply voltage, SCR2 is forward-biased, the lower half-part of the transformer secondary carries
the load current, the load voltage, and SCR1 is reverse-biased. The result is a pulsating dc output
across the load. The required trigger signals to the gates of SCRs are provided by the UJT
relaxation oscillators.

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Fig. 25-2 Single-phase full wave rectifier
Single-phase Bridge Rectifier
There are two major disadvantages of the full-wave rectifier circuits discussed above. They are:
(1) a center-tap power transformer required, and (2) the SCR (in off-state) with higher reverse
voltage rating required. To improve these, the full-wave rectifier circuit can be replaced by a
bridge rectifier circuit which eliminated the requirement for an input transformer.

Midpoint rectifiers while they use only half of the number of thyristors required in a bridge
rectifier, find economies in cost and simplicity of the control section, which is offset to some
extent by the increased cost of the higher voltage rating of the thyristors.

There are two types of SCR single-phase full-wave bridge rectifier circuit. One is the half bridge
rectifier shown in Fig. 29-3 consisting of two SCRs and two diodes. The other is the full bridge
rectifier circuit shown in Fig 29-4. In the circuit, four SCRs are employed.

Fig. 25-3 Half bridge rectifier

Fig. 25-4 Full bridge rectifier

In the half bridge rectifier circuit, two SCRs are employed and therefore two sets of trigger pulse
are required. Of course, a trigger signal can be used to control two SCRs If they are common
cathode connected In the full bridge rectifier circuit 'Illustrated in Fig.25-4, four SCRS are

193
employed and three sets of trigger pulse are required because thyristors SCR3 and SCR4 are
common cathode connected.

turned on, the current passes through the path of SCR1, load. and D2. During the negative half-
cycle of AC supply input. the forward-biased SCR2 and 01 (SCR1, D2 reverse-biased) are turned
on, the current passes through the path of SCR2. load, and D1. The load current is therefore
unidirectional. Since the reverse-biased SCR cannot be turned on by the gate trigger pulse. two
SCRs with the cathodes shorted can share a trigger signal

Fig 25-4 shows the full bridge rectifier circuit. In this circuit diagonally opposite pairs of SCRs
conduct and commutate together. The control is identical to that of the midpoint rectifier; i.e.. it
controls the mean output dc voltage from a maximum positive to zero. During the positive half-
cycle of AC supply input, the forward-biased SCR3 and SCR2 (SCR1. SCR4 reverse-biased) are
turned on, the current flows through SCR3, load, and SCR2 During the negative half-cycle of
AC supply input. the forward-biased SCR4 and SCR1 are turned on and the current passes
through SCR4, load, SCR1. The load current is therefore unidirectional. Similarly, SCR3 and
SCR4 can share a trigger signal.

SCR Three-Phase Rectifiers

In order to reduce the ac ripple content of the output dc voltage, and to minimize the need for
smoothing, as well as to increase the power output capability of a rectifier circuit, a three-phase
version of rectifier circuit was developed. The popular used versions of three-phase SCR
rectifiers are half-wave rectifier and bridge rectifier circuits.

Three-Phase Half-Wave Rectifier

The simplest version of three-phase rectifier is the half-wave midpoint rectifier circuit shown in
Fig. 25-5. In this circuit. each SCR is fired at the point when it becomes forward-biased. that is,
o=0', or 30' after the phase voltage crosses the zero axis. and as a result the ac input voltage with
the instantaneous value is applied to the dc load terminals, and the mean dc output voltage is at
its positive maximum.

194
Fig 25-6 Three-phase half-wave rectifier

In order to trigger the three SCRs sequentially, three sets of triggering Circuits are required, as
shown in Fig. 25-6. In this circuit, the three togged circuits are the same. The half-wave-rectified
and capacitor-filtered do voltage supplies the power to the tog get circuit. Darlington pair Q1-02
operates in saturation or cutoff according to the output of phase shifting circuit The triggering
pulse is produced by the differentiator circuit (C3 and R3), and amplified by transistor 03 to
drive the primary of the pulse transformer.

The transistor 04 and the associated components are constructed as a phase control circuit which
controls the firing angle of each SCR_ Its simplified circuit is shown in Fig_ 25-7. The base to
emitter voltage controls the resistance between the collector and emitter terminals so that the
phase shift angle is vaned as the base to emitter voltage changes.

Description of Experimental Circuit

The circuits on the KL-53014 Module shown in Fig. 25-10 include three separate identical UJT
relaxation oscillators, six SCRs, and a light bulb for the practice of various SCR rectifier circuits
mentioned before. The circuits and component values of the three UJT relaxation oscillators are
the same. The light bulb is used as it load of rectifier circuits.

The full-wave-rectified signal obtained from the rectifier bridge is used to supply both power and
synchronizing signal to the trigger circuit of the UJT relaxation oscillator.

195
The potentiometers VR1 through VR3 are used to control the triggering angles of SCRs. The
triggering signal applied to the gate of each SCR is electrically isolated by the pulse transformer.

Fig. 25-10 KL-53014 Module

As mentioned above_ if the SCFRs are used as the rectifier devices in a Three-Phat full bridge
rectifier circuit. six sets of trigger pulse are required to tom on the SCF sequentially. In this
experiment, three 1:1.1 pulse transformers T4 through T8 (. secondary windings each
transformer) are used for this purpose. If a positive voltage is applied to the primary of the pulse
transformer and maintained a short duration and then removed rapidly, this kind of input voltage
is known as a pulse as shown in Fig. 25-11. The output voltage on the secondary of the pulse
transformer will be direct proportion to the input voltage, but the output voltage waveform
cannot completely follow the input voltage waveform. The time that is required for the
secondary voltage of the pulse transformer increasing fron zero to maximum is known as the rise
time. The rise time is determined by the leakage inductance and capacitance of the transformer.
When the input voltage maintains constant. the output voltage decreases inversely proportional
to the inductance of primary winding When the input voltage is removed. the output voltage
cannot immediately fall to zero due to the energy stored in iron core discharging through the
winding capacitor and load resistor. Therefore, several cycles of damping oscillation tail away as
shown in Fig.

Since the required duty cycle of trigger pulse is usually very small, therefore a small pulse
transformer is enough to handle a very high energy of pulse.

196
Fig. 25-11 Input and output waveforms of a pulse transformer.

EQUIPMENT REQUIRED
1- KL-51001
2- 1- KL-58002
3- 1- KL-53014
4- Oscilloscope

PROCEDURE
1. Place Modules KL-51001 KL-58002, and KL-53014 on the experimental frame Apply
220 V AC posse r supply from Module KL-51001 to the primary winding of power
transformer 11 on Module KL-53014
2. Place the connect plugs in positions 1. 14. and 17 Using the connecting leads complete
the circuit shown In Fig 25.12

3. Turn the VR1 fully CCW Observe and record the light bulb's brightness

197
Using the oscilloscope measure and record the voltage waveforms across the UJT1 E-G1.

4. Set the signal frequency across UJT1 E-G1 terminals to 60 Hz by adjusting the VR1 and
record the voltage waveform in Table 25-2 Observe and record the bulb's brightness

198
5. Slowly turn the VR1 CW to turn off the light bulb L1. Using the oscilloscope measure
and record the voltage waveforms across the UJT1 E-G1 terminals and the light bulb L1
in Table 25- using the oscilloscope measure and record the voltage waveform across the

199
light bulb Lt in Table 25-3

6. Turn the VR1 fully CW Observe and record the light bulb s brightness Using the
oscilloscope measure and record the voltage waveforms across the UJT1 E-G1 terminals
and the Sight bulb L1 in Table 25-4

200
7. What is the type of this rectifier circuit?
8. Turn off the P008,
9. place the connect plugs in positions 1, 2, 14, 15, and 17 Using connecting leads complete
the circuit shown in Fig 25-13
10. Turn the VR1 and VR2 fully CCW

201
11. Set the signal frequencies across UJT1 E-G1 and UJT2 E-G2 terminals to 60 Hz by
adjusting the VR1 and VR2. respectively. Does the light bulb L1 operate in its maximum

brightness?
12. Comparing the bulb's brightness of steps 4 and 11. which is the greater one

and why?

______________________________________________________________________________
______________________________________________________________________________
______________________________________________________________________________
_____________________

202
13. What is the type of this rectifier circuit?

14. Turn off the power.

15. Place the connect plugs in positions 1, 2. (4, and 17 Using connecting leads. complete the
cloud shown in Fig 25-14

203
16. Turn the VR1 and V122 fully CCW.

17. Set the signal frequencies across UJT1 E-G1 and UJT2 E-G2 terminals to SC Hz by
adjusting the VR1 and VR2, respectively_ Does the bulb L1 operate ir its maximum brightness
without flashing?
______________________________________________________________________________
______ 18. Arbitrarily turning the VR1 and VR2, observe and record the change in the voltage
waveform across the light bulb L1

19. Turn off the power.

20. Place the connect plugs in positions 1, 2, 5, 7, 10, 11, 12, 14. 15, and 17 Using connecting
leads, complete the circuit

21. Turn the VR1 and VR2 fully CCW

204
22. Set the signal frequencies across UJT1 E-GI and UJT2 E-G2 terminals to 60 He by adjusting
the VR1 and VR2. respectively Does the light bulb LI operate in its maximum brightness without
flashing? If no readjust the VR1 and VR2. Using the oscilloscope. measure and record the
voltage waveforms across the UJT1 E-G1 terminals. UJT2 E-G2 terminals. and the light bulb L1
in Table 25-8.

205
23. Arbitrarily turning the VR1 and VR2, observe and record the change in the voltage
waveform across the light bulb L1.

______________________________________________________________________________
______

What is the type of this rectifier circuit?

24. Turn off the power.

25. Place the connect plugs in positions 1, 2, 4, 6, 10, 11, 12, 14. 15. and 17 Using connecting
leads. complete the circuit.

26. Turn the VR1 and VR2 fully CC,"

27. Set tne signal frequencies across UJT2 E-G2 terminals and UJT1 E-G1 to 60 Hz by adjusting
the VR2 and VR1, respectively. Does the light bulb Li operate in its maximum brightness
without flashing, no. readjust the VR1 and VR2. Using the oscilloscope. measure and record the

206
voltage waveforms across the UJT1 E-G1 terminals, UJT2 E-G2 terminals and the light bulb L1
In Table 25-9

28. Arbitrarily turning the VR1 and VR2, observe and record the change in the voltage
waveform across the light bulb L1.

207
______________________________________________________________________________
______

What is the type of this rectifier circuit?

______________________________________________________________________________
______ 129. Turn off the power

30. Place the connect plugs in positions 1, 2, 3, 14, 15, 16, and 17. Using connecting leads,
complete the circuit shown in Fig. 25-17

31. Turn the VR1, VR2 and VR3 fully CCW

32. Set the signal frequencies across UJT1 E-G1 terminals, UJT2 E-G2 terminals and UJT3 E-
G3 terminals to 60 Hz by adjusting the VR1. VR2, and VR3 respectively Does the light bulb L1
operate in its maximum brightness without flashing? If no, readjust the VR1, VR2 and the VR3
Using the oscilloscope. measure and record the voltage waveforms across the UJT1 E-G1
terminals. UJT2 E-G2 terminals. UJT3 E-G3 terminals and the light bulb Ll in Table 25-10

208
33. Turning the VR1. VR2. and VR3. observe and record the change in the voltage waveforrn
across the light bulb Li?

______________________________________________________________________________
______ What is the type of this rectifier circuit?

______________________________________________________________________________
______

34 Turn off the power

209
35. Place the connect plugs in positions 1, 2. 3. 5. 7. 9, 10, 11, 12, 13, 14. 15. 16, using
connecting leads complete the circuit shown in Fig. 25-18

36. Turn the VR1 VR2 and VR3 fully CCW

37. Set the signal frequencies across UJT1 E-G1 terminals. UJT2 E-G2 terminals and UJT3 E-
G3 terminals to 60 Hz by adjusting the VR1, VR2 and VR3 respectively_ Does the light bulb L1
°aerate In Its maximum brightness without flashing? If no, readjust the VR1, VR2 and VR3.

Using the oscilloscope, measure and record the voltage waveforms across the UJT1 E-G1
terminals, UJT2 E-G2 terminals, UJT3 E-G3 terminals, and the light bulb Li in Table 25-11

38. Turning the VR1, VR2, and VR3, observe and record the change in the voltage waveform
across the light bulb L1?

______________________________________________________________________________
_____

What is the type of this rectifier circuit?

______________________________________________________________________________
_____

39. Turn off the power

210
CONCLUSION

In this experiment, you have constructed various SCR rectifier circuits and observed the
operations of rectifiers using the oscilloscope You saw that the SCR rectifiers are very similar to
the diode rectifier circuits and the main difference is that the output voltages can be controlled by
changing the triggering angles of SCR device.

211
In procedure steps 1 to 8, you constructed a half-wave SCR rectifier circuit and measured the
triggering signal and load voltage waveforms You also observed the bulb's brightness which is
proportional to the average dc load voltage You observed that the maximum brightness occurs
when the frequency of trigger signal is exactly set at 60 Hz by adjusting the VR1

In steps 9 to 14, you constructed a full-wave SCF2 rectifier circuit which consists of two SCRs
and two separated triggering circuits The potentiometers VR1 and VR2 are used to adjust the
trigger angles of SCR2 and SCR4, respectively. You observed that the bulb's brightness of step
11 is greater than that of step 4 since the average do load voltage of a full-wave rectifier is
greater than that of a half-wave rectifier You also constructed another type of single-phase full-
wave rectifier circuit which contains two SCRs connected in reverse-parallel in steps 15 thou 19
and observed the same result.

In steps 20 thou 24, you implemented and measured a half bridge SCR rectifier circuit which
consists of two SCRs and two diodes. In steps 25 thou 29, you also implemented and measured a
full bridge SCR rectifier circuit which consists of four SCRs You observed that the results of
these two circuits are the same

In steps 30 to 34 i built and measured a three-phase half-wave rectifier circuit with midpoint You
observed that the ac input voltage with the instantaneous value is applied to the load and the
mean dc output voltage is at its positive maximum.

Ito steps 35 thou 39. you constructed and measured a three-phase half-bridge full wave rectifier
circuit which consists of three SCRs and three diodes You observed that the bulb's brightness is
controlled by the three potentiometers VR1 VIR2 and VR3

212
EXPERIMENT 18 FET/MOSFET Characteristic and
MOSFET Speed Control

OBJECTIVE

1. Understanding the structure and characteristics of JFETs.

2. Plotting the characteristic curves of a JFET.

3. Understanding the structure and characteristics of MOSFETs.

4. Plotting the transfer characteristics curves of a MOSFET.

5. Implementing and measuring a MOSFET motor- speed control circuit.

DISCUSSION

Field-Effect Transistor (FETs)

The field effect transistor (FET) is a semiconductor device which depends for its operation on
the control of current by an electric field and conducts the current with a single carrier, hole or
electron. According to the structure, there are two types of FETs, junction Field Effect Transistor
(JFET) and Metal-Oxide Semiconductor FET (MOSFET). The FET differs from the Bipolar
Junction Transistor (BJT) in the following characteristics:

A. It is a unipolar device similar to the vacuum tube.

B. It is immune from radiation.

C. It has an extremely high input impedance, typically many megaohms.

D. it is less noisy than BJT.

E. It provides greater thermal stability than BJT.

F. It provides greater thermal stability than a BJT G. Its key disadvantage is the relatively small
GBP of the device compared to the BJT

213
The structure and operation of the FET are different to those of the BJT. The current of the BJT
contains majority and minority carriers which flow through two p-n junctions, while the current
of the FET is only the majority carrier flowing in drifting. For the FET, its channel width can be
controlled by an external electric field so that the magnitude of channel current is determined by
the electric field. On the contrary. the magnitude of BJT collector current is controlled by the
injected base current

Either JFET or MOSFET, there are n-channel and p-channel FETs according to the channel type.
Basically, the operating principles of JFET and MOSFET are very similar; however, the input
resistance of the JFET is smaller than that of the MOSFET (up to 10. CI) due to a pn-junction
between the gate and channel. Furthermore. the MOSFET has many advantages in
manufacturing so that the MOSFET is more important than the JFET microelectronics industry.
In this experiment, you will study the basic electrical characteristics and circuits of JFET and
MOSFET devices.

The FET is a semiconductor device which delivers the current with a single earner The charge
carrier in a p-channel FET is hole. while in an n-channel FET is electron. Compared to the BJT,
the MOSFET which features smaller Gain-Bandwidth Product (GBP). higher 'fleet impedance.
and lower manufacturing complication, is suited for manufacturing the Large-Scale Integrated
(LSI) and Very-Large-Scale Integrated (VLSI) circuits

Junction Field-Effect Transistors (JFETs)

The JFET devices can be divided into p-channel and n-channel JFETs. 26-1 shows the cross
section of a typical n-channel JFET structure. The JFET is a three-terminal device containing the
source (S), gate (G), and the drain (D) terminals. The circuit symbol shown is the n-channel
JFET. For a p-channel JFET, the arrow at the gate points in the opposite direction Generally a
JFET can be considered as a gate-voltage-controlled variable resistor. Either end of the channel
may be used as a source or drain

214
Fig. 26-1 N.channel JFET structure, circuit symbol, and output characteristics

The voltage across drain-source VDS, which results in a drain current I D from drain to source.
This drain current passes through the channel surrounded by the p-type gate Since the gate-
source voltage VCS will reverse bias the gate-source junction, no gate current will result. The
effect of the gate-source voltage will be to create a depletion region in the channel and therefore
reduce the channel width to increase the drain-source resistance resulting in less drain current.
We first consider the n-channel JFET operation with V GS=0 V, the drain current 10 increases
linearly with the drain-source voltage VDS. The drain current through the n-material of the drain-
source produces a voltage drop along the channel, which is more positive at the drain-gate
junction than at the source-gate junction This reverse-bias potential across the p-n junction
causes a depletion region to form as shown in Fig. 26-1 When the Vos is increased, the 10
increases, resulting in a larger depletion region. As the voltage V0s is increased, the depletion
region is fully formed across the channel. Any further increase in V DS, greater than the VDS(sat) will
result in no increase in the drain current, the current 10 then remaining constant or saturation and
designated as loss. This is described in the V GS=O characteristic curve of Fig. 26-1. With the
reverse-bias voltage VG, increased, the depletion region fully forms at a lower level of drain
current. If the gate-source voltage V GS is increased to the pinch-off value V P or the drain current
reduces to 0, and the JFET is completely turned off. The pinch-off voltage V P and the saturation
drain-source current loss are two important parameters of the JFET device and they are indicated

215
in the transfer characteristic curve of Fig. 26-

JFET Drain Characteristic

The drain characteristic is a set of curves for different values of V CS from 0 V to the pinch-off
voltage, V, or VGS(0FF) , the voltage at which the depletion region is formed without any drain
current and at which no drain current can occur.

Fig. 26-3 shows the typical n-channel JFET drain characteristic curves plotted the actual drain
current 10 at different values of drain-source voltage Vos fora range of gate-Source voltage
values VG,. The drain characteristic contains the ohmic region, saturation region, avalanche
region, and cutoff region.

216
For VGS=0V. the curve plotted shows that the drain current increases as VD, is increased until a
point (VGS=4V) at which the current reaches saturation and loss 10 mA. From the previous
discussion we know that the internal depletion region acts to limit the drain current. If the gate-
source voltage is set at VG, = -1 V, the current increases as VD, is increased until a saturation
level is reached, this time at a lower level than for VG, = 0 V. since the depletion region, starting
partly formed due to VG, = -1 V, fully forms at a lower level of drain-source current. If the gate-
source voltage is increased beyond the pinch-off value (-6 V), the dram current reduces to O. and
the JFET device is completely turn. off. Since the drain current is a single carrier, each
characteristic curve therefore passes through the origin.

JFET Transfer Characteristic Curve

The transfer characteristic curve also called transconductance curve is a plot of drain current to
as a function of gate-source voltage V GS, for a constant value of drain-source voltage V°, The
transfer curve of an n-channel JFET shown in Fig. 26-4 is plotted from the drain characteristic
curves of Fig. 26-3 and mathematically expressed by the parabolic approximation.

217
Metal-Oxide-Semiconductor FETs (MOSFETs)

A field-effect transistor can be constructed with the gate terminal insulated from the channel.
The popular Metal-Oxide-Semiconductor FET (MOSFET), or sometimes called the Insulated
Gate Field Effect Transistor (IGFET), is constructed as either a depletion MOSFET (DMOS) or
enhancement MOSFET (EMOS). In the depletion-mode construction a channel is physically
constructed and current between drain and source will result from a voltage connected across the
drain-source terminals. The enhancement MOSFET structure has no channel formed when the
device is constructed. Voltage must be applied at the gate to develop a channel of charge carriers
so that a current results when a voltage is applied across the drain-source terminals.

Since the MOSFET device has the features of low noise and good stability, it is widely used in
high input impedance and high voltage amplification circuits The very thin insulating layer
between the gate and substrate of a MOSFET can easily be punctured if an excessive voltage is
appli.. Human body .n build up extremely large electrostatic charges due to friction If this charge
comes in contact with the terminals of a MOSFET device, an electrostatic discharge would
occur, resulting in a possible arc across the thin insulating layer causing permanent damage. To
avoid this damage, the MOSFET terminals are usually shorted with a conductive ring or
conductive foam in shipping and the conductive ring must be removed after soldering.

Fig. 26-5 shows the structure and characteristic of an n-channel MOSFET Like the JFET. it can
be considered as a gate-voltage-controlled variable resistor and it is a three-terminal device
containing the source (S), gt (G). and drain (D) terminals. The main difference between
MOSFET and JFET is an oxide layer between the gate and p-substrate (not a p-n junction) of the
NMOSFET Therefore the MOSFET's input resistance is much higher than the JFET.

218
Fig. 26-6 shows the transfer characteristics of depletion and enhancement NMOSFETs. The
depletion MOSFET of Fig. 26-6a) is shown to operate with either positive or negative gate-
source voltage, negative values of V SS reducing the drain current until the pinch-off voltage V p
after which no drain current occurs. The transfer characteristic is the same for negative gate-
source voltages. but it continues for positive values of Vss. Since the gate is isolated from the
channel for both negative and positive values of V SS, the device can be operated with either
polarity of VGs and no gate current resulting in either case.

1. Depletion MOSFET
Fig. 26-7 shows the structure a. circuit symbol of the n-channel depletion MOSFET. Source and
drain are made by the higher-doped n-type semiconductor material and the channel is a lower-
doped n-type region. A metal layer is deposited above the n-channel on a layer of silicon dioxide
(Si, which is an insulating layer. This combination of a metal gate on an oxide layer over a
semiconductor substrate forms the depletion MOSFET device. The gate-source voltage to this
kind of MOSFET can be either positive or negative. For the n-channel depletion MOSFET of
Fig. 26-7. negative gate-source voltages push electrons of the channel region to deplete the
channel and a large enough negative gate-source voltage W will pinch off the channel. Positive
gate-source voltage on the other hand will result in an increase in the channel size (pushing away
p-type carries). allowing more charge carriers and therefore greater channel current to result

The circuit symbol in Fig. 26-7 shows the addition of a substrate terminal on which the device
type is indicated. the arrow here indicating a p-substrate and thus n-channel device.

219
2. Enhancement MOSFET
Fig. 26-8 shows the structure and circuit symbol of n-channel enhancement MOSFET. The
substrate a lower-doped P-type semiconductor material and source and drain are higher-doped n-
type semiconductor material. It has no channel between drain and source as part of the basic
device structure. Application of a positive gate-source voltage will re. holes in the substrate
region under the gate leaving a depletion region. When the gate voltage Is sufflolenffy Positive
electrons are attracted into this depletion region making it then act as an n-channel between drain
and source. There is no drain current until the gate-source voltage exceeds the threshold voltage
VT result In increased drain current The transfer characteristic A descnbed in Fig. 26-5(b). Note
that no value loss can be associated with an endangerment MOSFET beCause no drain current
occurs with VG,0 V Although the enhancement MOSFET is more restncted in operating range
than is the depletion device. the enhancement device is very useful in large-scale integrated
circuits in which the simpler corAtruction and smaller size make it a suitable device
Complementary MOSFET (CMOS)

220
A complementary MOSFET (CMOS) connects enhancement PMOS and NMOS FETs into a
complementary device which is unmanly used m AgAboS The input is internally

Connect in common to the gate of both PMOS and NMOS FETs A high input voltage

drives the PMOS Of and the NMOS on A low input voltage will correspondlegh, drive the

PMOS on and the NMOS off Power MOSFET. The power Metal-Oxide-Semiconductor PET
(power MOSFET) s a ...al and voltage-controlled device Power MOSFET has the features of fast
watching speed good high-frequency characteristic. high input impedance small dnve power.
excellent

thermal stability, no second breakdown. wide Safe Operating Area (SOA) and high operating
linearity, etc. Since the key advantages of small size and lightweight, the power MOSFET
provides a high speed, high power, high voltage, and high gain device. The power "C'SFET used
M high-power switching applications such as power supplies. converters and PVVM motor
controls.

Structure of Power MOSFET

Power MOSFET is an integrated power devi. which contains tens of thousands small MOSFETs
Interconnected In parallel. Fig 26-9 shows the typical structure of an n-channel Power MOSFET
Two higher-doped n. regions are constructed as source and drain terminals. An insulating layer
(5i02) exists between gate and channel.

221
The power MOSFET shown in Fig. 26-9 is a 4-layer sandwich configuration of n•(,)pn•. The
lower-doped n- region is a drift region which increases the device voltage rating In the device,
two back-to-back pn-junctions exist between drain and source. If no gate voltage is applied, the
device is always in off state whenever the drain-source voltage is either positive or negative.

Static Characteristics of Power MOSFET

Power MOSFET's output characteristic curves have two distinct operating regions a constant-
resistance region and a constant-current region. In the constant-resistance region, the drain
current is direct proportion to the increase in the drain-source voltage until the drain-source
voltage reaches at its pinch-off voltage. Beyond this point, the drain current remains constant and
the device operates in the constant-current region

When the power MOSFET is used as an electronic switch, the drain-source voltage drop is
proportional to the drain current, that is, the MOSFET operates in the constant resistance region
and it can be considered as a resistive component. The on-state drain-source resistance Rpso„, is
the key parameter which determines the power losses at a given drain current. The drain current
starts to flow at the applied gate voltage over the threshold voltage (typically 2 to 4 V). Once the
gate-source voltage is over the threshold voltage. the relationship between drain current and gate
voltage is approximately linear.

The common-source forward transconductance gm or g, specifies the power MOSFET ac

amplification. It is measured with drain-source shorted and indicates how much the ac drain
current will change due to an applied ac gate-source voltage.

Safe Operating Area (SO, of Power MOSFET

As mentioned before, a MOSFET is a majority-carrier device and therefore it has a positive

temperature coefficient of resistance and its second breakdown effect is minimal compared to
that of a BJT device. A comparison of the forward-biased safe operating areas is shown in Fig.
26-10. The dc and pulse SOAs of power MOSFET are spinor to those of the BJT under dc (solid
line) and pulse dotted line, operating conditions.

222
Full- Bridge ZVS MOSFET

In recent years, the power requirements of power supply systems are higher and higher
especially in telecommunication and server applications These requirements push the Power
electronics industry to develop the power supply equipment with higher power density and
reliability. This is a strict challenge to design engineers how to promote the power density from
5.7 Min' to 10 Wile The use of the phase-shifting Zero-Voltage-Swrtching !NS, technique may
be a good solution of this problem With ZVS design, higher power density and reliability can be
obtain.. In designs, the ZVS technique can minimize the switching losses and increase relatively
higher switching frequency. Higher switching frequency implies that the smaller size and shorter
response time of filtering devices may be used so that the circuit size is reduced and the power
density is prom... Lower swItch.g loss means that a lower temperature rise can be obtained so
that the requirement of heat sink is lowered. In addition, NS operation can reduce the effects of
transient dv/dt and di/dt, and increase reliability of power supply equipments. However, the
MOSFET in a full-bridge ZVS converter may be failure under some conditions such as slow
recovery body diode, especially at low reverse voltage condition. Another case of MOSFET
failure is the puncture-through problem of Cdv/dt. When the MOSFET is forced to ON or OFF.
NS converter could be failure under no load or light load conditions.

In brief, the ZVS technique maximizes efficiency and enables higher power output in switch-
mode power-supply (SMF'S) circuits.

MOSFET Body Diode in VS Circuits

223
The research for the MOSFET operation in ZVS circuits leads the development of MOSFET
technology to a new generation of fast built-in body diode. The main purposes are to lower the
reverse recovery time of body diode, to enhance the permission of dvicit. to minimize puncture
through effect of Cdv/dt, and to increase the reliability in high-frequency and high-power phase-
shifting NS applications without pay of efficiency.

In a full-bridge NS circuit, if the reverse recovery process of built-in body diode does', complete
before the MOSFET is turned off, the transient dv/dt will result in the MOSFET failure_ When
the NS circuit operates at higher frequencies, this problem becomes worse because the
permissible reverse recovery time of the built-in body diode becomes shorter.

Basically, the NS converter cannot switch at zero voltage under a tight-load condition so that the
MOSFET in on-state will be forced to turn off, similar to the operation of forced-font., full-
controlled badge circuit. and the Cdv/dt transient will create a vokage surge at the 9.e and will
result in a damage to the device.

In no-load or light-load conditions. the reliability of NS circuits will be improved by enhancing

the permission of Cdv/dt. The failure of Cdv/dt puncture through can be improved by reducing
the Ogcl/C/gs1 ratio and internal gate resistance Rg.

Description of Experimental Circuit

Fig. 26,1 shows the circuit for JFET/MOSFET characteristic measurements on Module KL-
53015. Fig. 26-12 shows the MOSFET motor-speed control circuit

The 2SK30A is a silicon n-channel JFET Its major electrical specifications include gate to drain
voltage VG. = -50 V. gate current IG = 10 mA, drain power dissipation Po = 100 mW, drain to
source leakage current to, = 0.3 mAmin to 6 5 mAmax (test conditions: Vos=10 V. Vos=0

The 2SK2698 is a silicon n-channel MOSFET. Its major electrical specifications include, drain
to source voltage Voss = 500 V. drain current lo = 15 A (continuous) or 60A (pulsed), drain
power dissipation Po = 150 W, drain to source on resistance Rost,,,, = 0.35 L2 (test conditions'
Vos = 10 V. lo = 7 A), gate to source threshold voltage Vo, 2.0 Vmin to 4Vmax (test conditions:
Vos=10 V, 1,1 mA).

224
Basically the NS converter cannot switch at zero voltage under a tight-load condition so that the
MOSFET in on-state will be forced to turn off, similar to the operation of forced-font., full-
controlled badge circuit. and the Cdv/dt transient will create a vokage surge at the 9.e and will
result in a damage to the device.

In no-load or light-load conditions. the reliability of NS circuits will be improved by enhancing

the permission of Cdv/dt. The failure of Cdv/dt puncture through can be improved by reducing
the Ogcl/C/gs1 ratio and internal gate resistance Rg.

Description of Experimental Circuit

Fig. 26,1 shows the circuit for JFET/MOSFET characteristic measurements on Module KL-
53015. Fig. 26-12 shows the MOSFET motor-speed control circuit

225
The 2SK2698 is a silicon n-channel MOSFET. Its major electrical specifications include, drain
to source voltage Voss = 500 V. drain current lo = 15 A (continuous) or 60A (pulsed), drain
power dissipation Po = 150 W, drain to source on resistance Rost,,,, = 0.35 L2 (test conditions'
Vos = 10 V. lo = 7 A), gate to source threshold voltage Vo, 2.0 Vmin to 4Vmax (test conditions:
Vos=10 V, 1,1 mA).

The motor-speed control circuit is illustrated in Fig. 28-12 The 38-V AC input Is full-wave-
rectified by the DR1 bridge rectifier and capacitor-filtered by tha capacitor C1 and about 50 Vdc
is obtained to supply the power to universal motor and MOSFET The additional 12-V DC supply
provides the working voltage for the operational amplifier Ut

The combination of the U1 operational amplifier and MOSFET acts as the feedback speed
controller which can be adjusted to provide the predelermined motor speed The reference voltage
is provided by the Zener diode ZD1 and the diode D1 connected in series (temperature-
compensated configuration) and is adjusted by the speed control potentiometer VR1. The
feedback voltage which is directly related to the speed is .d from the voltage drop across the
resistor R2. The differ.ce or enor between the feedback voltage (proportional to the motor speed)
and the reference voltage can then be used to "felt' the system whether it should increase the
speed or reduce it, in order to bring it back as close as possible to the reference value.

226
EQUIPMENT REQUIRED

 KL-53015 Module
 KL-51001 Module
 KL-58002 Module
 Analog Multimeter 2 Multimeter (DMM)

PROCEDURE

A. JFET/MOSFET Static Characteristics

1. Place Module KL-53015 in the experimental frame Locate the circuit for JFET/MOSFET
characteristic rneasurement. The circuit is located on the upper half of the module. Remove all
connect plugs from the Module.

2. Set the range selector of analog multimeter to Rx10 setting. In this case. the multimeter is used
as an Ohmmeter and the internal battery is used to bias the JFET device The positive polarity (+)
of internal battery is interconnected to the black lead, and the negative is interconnected to the
red lead. According to the following tables, connect the Ohmmeter leads to the JFET pals and
record the measured values JFET Pin JFET Pin Ohrnmeter Lead Red (-) Black (+) Ohmmeter
Lead Red (-) Black (+1 Result Result JFET Pin JFET Pin Ohmmeter Lead Black (+) Red (-)
Ohmmeter Lead Black (+) Red (-) Result.

227
3. From the above results what is the type of this JFET?
__________________________________________________________________________

4. Set the range selector of analog multimeter to the Rx10 setting, According to the
following tables, connect the Ohmrneter leads to the MOSFET pins and record he
measured values.

5. From the above results, what ts the type of the MOSFET,

JFET Characteristic Curves

1) Place Module KL-53015 in the experimental frame. Locate the JFET/ MOSFET
characteristic circuit on the module The circuit is located on the upper half of the module.
2) Connect 110 V AC power source to Modules KL-51001 and KL-58002. Place the power
switch in OFF position. Connect the 12V-0V-12V AC supply from Module KL-51001 to
Module KL-53015.
3) Turn the VR1 fully CW and the VR2 fully CCW Place the connect plugs in positions 1.
4. 6, and 7.

228
4) Two DMMs are required in the following procedure. Set the range selectors of DMMs to
DCV 20 setting. In this case, these two DMMs are used as DVMs (digital voltmeters) for
measuring the JFErs VG; and 10 values. The drain current 10 is obtained by measuring
the voltage drop across the R3, VR,, and by calculating 1p = Vi,, /1 Kfl.
5) Turn on the power of KL-51001

6) Connect a DVM across JFET G-S terminals for measuring the VG; values, and a DVM
across the R3 for measuring the VA, values. Adjust the VR1 and set Vcs 2 10 V to ensure
the JFET operating in saturation (V0, VG; - V0). Adjusting the potentiometer VR2 for
each of the listed VG; values. measure and record the corresponding VG, values in the
table below. Calculate and record the 1,, values using the equation 1,,,,/1 KC).

7) Remove the connect plug from position 1 to position 2. Connect a DVM across the JFET
G-S terminals for measuring the VG; values. Connect a DVM across the R3 for
measuring the Vn, values. Adjusting the potentiometer VR2 for each of the listed VG;
values, measure and record the corresponding VR, values in the table below Calculate
and record the I, values using the equation 10,01 K

8) Plot the V-I curves (transfer characteristic curve) (Jame the results In Steps 6 and 7
Determine the pinch-off voltage V, and describe the transfer curve
________________________________________________________________________
________________________________________________________________________
_____________________________________________________________________

229
9) Remove the connect plug from position 2 to position 1 Adjust the VR2 a. set VGs value
to -1 5 V Adjust the VR1 for each of the values listed in the table below Measure and
record the correspo.ng values of V., a. calculate the I, values using the equation ly.V.,1
KΩ

Adjust the VR2 and set Vos value to -1.0 V Adjust the VR1 for each of the V,,s values listed
in the table below. Measure and record the corresponding values of VR, and calculate the
values using the equation 10,4,1 KO.

10) Using the results in Step 9. plot the Vos - lo curves (drain characteristic curves) at
different Vos values in the graph below and describe the difference among these curves.

230
___________________________________________________________________________
_________________________________________________________________________

MOSFET Transfer Curve

1) Place Module KL-53015 on the experimental frame. Locate the JFET/ MOSFET
characteristic circuit on the module. It is located on the upper half of the module.
2) Connect 110 V AC supply to Modules KL-51001 and KL-58002. Place the power
switch in OFF position. Connect 12V-0V-12V AC supply from Module KL-51001 to
Module KL-53015.
3) Turn the VR1 fully CW and the VR2 fully CCW Place the connect Plugs in positions
1. 4. 5. and 8.
4) Two DMMs are required in the following procedure Set the range selectors of DMMs
to the DCV 20 setting. In this case. these DMMs are used as DVMs for measuring the
MOSFET gate-source voltage VG, and the drain current
5) Turn on the power of Module KL-51001.
6) Connect a DVM across MOSFET G-S terminals for measuring VG,. and a DVM
across the R4 for measuring lo Adjust the VR1 and set V. 10 V to ensure the
MOSFET operating in saturation (Vps Vos Vp),

231
7) potentiometer VR2 for each of the VG, values listed in the table below Measure and
record the V. and calculate the 10 values using the equation 1,, V. 1KΩ

8) Remove the connect plug from position 1 to position 2. Connect a DVM across
MOSFET gate-source terminals for measuring VGs, and a DVM across the Ra for
measuring 10. Adjust the potentiometer VR2 for each of the VGs values listed in the
table below. Measure and record the V. and calculate the lo values using the equation
I, / 1 KO. Plot the curve (transfer characteristic curve) using the results of steps and 7.
Determine the threshold voltage VI value.
________________________________________________________________________
______________________________________________________________________

MOSFET Motor-Speed Control

1) Place the Module KL-53015 on the experimental frame Locate the MOSFET motor-
speed control circuit on Module KL•53015 is located on the lower half of this module
2) Connect 110 V AC supply to Modules KL-51001 and KL•58002. Place the power switch
in OFF position. Connect 36V-OV AC supply and 12 V DC supply from Module KL-
51001 to Module KL-53015 Connect the universal motor from Module KL-58001 to
Module KL-53015
3) Turn the speed control potentiometer VR1 fully CCW

232
4) Turn on the power of Module KL-51001 JS Connect a DVM (DCV 20 setting) across the
gate (UI pint) and ground Connect a DVM (DCV 20 setting) across the R2.
5) Slowly adjust the speed control potentiometer VR1 until the motor runs Observe and
record the motor speed Measure and record the voltage on U1 pint and the voltage drop
across the R2, Vt,,, in the table below

6) Test Point Result U1 Pint

7) Slowly adjust the VR1 to increase the motor Woad Observe and record the change in
motor speed Measure and record the voltage on U1 pint and the voltage d op across the
R2, \ix, in the table below.

8) 8 Turn the VR1 to its maximum value Observe and record the change in motor speed
Measure and record the voltage on U1 pint and the voltage drop across the R2 V,. in the
table below.

9) Record the voltage on U1 pint when the motor runs at its highest speed

233
CONCLUSION

A. JFET/MOSFET Static Characteristics

In the exercise of JFET/MOSFET static characteristic. You measured the JFET dc resistances
of gate-source. gate-drain and drain-source using an Ohmmeter. You saw that a low
resistance of 100 it exists between gate-source and gate-drain when the black lead is
connected to the gate and the red lead (-) is connected to drain or source, and a high
resistance of 700 f/ between drain and source terminals. You therefore identified that the
JFET is an n-channel FET.

Y. also measured the MOSFET dc resistances of gate-source, gate-drain and drain-source

using an Ohmmeter You observed that a very high resistance exists between gate-source and
gate-drain terminals since an insulting layer is between the gate and channel You also
observed that the forward resistance of body diode is about 500 when the black lead is
connected to the source and the red lead to the drain Therefore the channel type of the
2SK2698 couldnt be identified according these testing results.

B. JFET Characteristic Curves

In the exercise of plotting JFET characteristics curves. you Plotted the transfer characteristic
curve and the drain characteristic curves of the 2SK30A You observed that the In value of
the JFET Is 12135mA approximately

234

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