CS223 – DIGITAL DESIGN

STUDY QUESTIONS # 2

Q1. Consider the following CMOS logic gate.

(a) Write a simplified Boolean equation for the output of this gate in
terms of inputs A, B, C.
(b) Fill in the truth table below. For transistors N1, N2, N3, P1, P2,
P3 you should write the states whether ON or OFF. For the output Y,
you should enter either 0 or 1.

Inputs Transistors Output

A B C N1 N2 N3 P1 P2 P3 Y
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

Q2. Given the following truth table for a logic function

(a) Write a Boolean equation in Sum-of-Products (SOP) canonical form.

(b) Write a Boolean equation in Product-of-Sums (POS) canonical form.
(c) Find a minimal Boolean equation for the function using Karnaugh map method.

Q3. Implement the function 𝒀𝒀 = 𝑨𝑨𝑨𝑨𝑪𝑪 + 𝑨𝑨𝑩𝑩 + 𝑨𝑨𝑩𝑩𝑪𝑪 using only one 2x1 multiplexer and one 2-
input XOR gate (do not use any other logic gate). Sketch your circuit using inputs 𝐴𝐴, 𝐵𝐵, 𝐶𝐶.

CS223-Digital Design 2022 Spring – Alper SARIKAN

Q4. Write a minimized Boolean equation for the function performed by the following circuit (inputs
are A, B, C and the output is Y ).

B 0

C 1

B 0 2:1
C 1
Mux

Q5. Suppose that we have the following Boolean function 𝑌𝑌 = 𝐹𝐹(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷).

AB
CD 00 01 11 10
00 1 0 1 1
01 1 1 0 0
11 1 1 0 0
10 1 0 1 1

(a) Using Karnaugh map method (draw your circles on K-map), find a minimized Boolean
equation in sum-of-products (SOP) form.

(b) Using Karnaugh map method (draw your circles on K-map) and Boolean algebra, find a
minimized Boolean equation in product-of-sums (POS) form.

Q6. Suppose that we have the following Boolean function 𝑌𝑌 = 𝐹𝐹(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷).

AB
CD 00 01 11 10
00 1 0 1 1
01 0 0 X 0
11 1 X 0 0
10 1 0 1 X

(c) Using Karnaugh map method (draw your circles on K-map), find a minimized Boolean
equation in sum-of-products (SOP) form.

(d) Using Karnaugh map method (draw your circles on K-map) and Boolean algebra, find a
minimized Boolean equation in product-of-sums (POS) form.

CS223-Digital Design 2022 Spring – Alper SARIKAN

Q7. Design a Finite State Machine (FSM) using the state transiton diagram given below

(a) Using binary state encodings, write the state transition table and output table for the FSM.
Write Boolean equations for the next state and output logic.

(b) Sketch a schematic for your FSM circuit.

Q8. Design a Finite State Machine (FSM) that receives a bit string of 1’s and 0’s at the input and
outputs 1 whenever it detects a sequence of 11; otherwise outputs 0.
(a) Draw the state transition diagram of FSM.
(b) Write the state transition and output tables of FSM using binary state encoding.
(c) Write Boolean equations for the next state and output of FSM.
(d) Sketch the circuit schematic of FSM.

Q9. Design a Finite State Machine (FSM) that receives a bit string of 1’s and 0’s at the input on
each rising edge of clock signal and outputs 1 whenever it detects a sequence of 1001;
otherwise outputs 0.
(e) Draw the state transition diagram of FSM.
(f) Write the state transition and output tables of FSM using binary state encoding.
(g) Write Boolean equations for the next state and output of FSM.
(h) Sketch the circuit schematic of FSM.

Q10. Given the logic function𝐹𝐹(𝑎𝑎, 𝑏𝑏, 𝑐𝑐, 𝑑𝑑) = ∑ 𝑚𝑚(0,2,3,8,12,14) + ∑ 𝑑𝑑(7,10,13) where
represents minterms of the function and represents don’t cares. Find the minimal Boolean
expression for using the Karnaugh map method.

Q11. For the logic function

(a) Write the truth table.

(b) Write the function in Sum-of-Products (SOP) and Product-of-Sums (POS) canonical forms.

CS223-Digital Design 2022 Spring – Alper SARIKAN

Q12. Find a minimal Boolean expression for the function given in the following Karnaugh map.
Implement the function using only NOR gates assuming that the complements of input
variables are available.
CD 00 01 11 10
AB
00 1 X 1

01 1

11 X 1 X 1

10 X X 1

Q13. You are required to design an 8-bit synchronous Up/Down counter. The inputs are CLK,
Reset, and Up. When Reset is 1, the output bits are all 0. Otherwise, when Up = 1, the
circuit counts up, and when Up = 0, the circuit counts down. You can use only one 8-bit
register with reset input, one 8-bit adder, and one 8-bit 2:1 multiplexer. Sketch the circuit
schematic of your design using the component symbols given below.

Register Adder Multiplexer

Q14. Find the minimized Boolean expression for the logic function performed by the following
circuit (inputs are and the output is ).

CS223-Digital Design 2022 Spring – Alper SARIKAN

Q15. Let us define the distance between two binary numbers as the number of bit positions that
the numbers differ from each other. For example, the distance between 001 and 100 is 2 since
they differ in two-bit positions. The distance between 000 and 111 is 3 since they differ in
three-bit positions. The distance between 010 and 000 is 1 since they differ in one-bit position.

Design a combinational circuit that will take two 3-bit binary numbers ( and )
as input and will produce a 2-bit binary number ( ) as output. The output will give the
distance between input binary numbers. For example, if the inputs are and
, then the output will be indicating that the distance is equal to 2.
Draw the logic diagram of your circuit. You can use only AND, OR, NOT, and XOR gates.

Q16. The state transition diagram of an FSM is given below. The FSM receives two inputs A, B
and it has one output Y.
(a) Write the state transition and output table using binary state encodings.
(b) Write the minimized Boolean equations for the next-state logic and output logic.

Q17. Analyze the Finite State Machine (FSM) given below.

(a) Write the state table and output table for the FSM using binary state encodings.
(b) Sketch the state transition diagram of the FSM.

Q18. Design a Mealy Finite State Machine (FSM) that receives a bit string of 1’s and 0’s at the
input and outputs 1 whenever it detects a sequence of 010; otherwise outputs 0. Draw the state
transition diagram of your FSM. Write the state transition and output table for the FSM using
binary state encodings.

Q19. Design a system that counts the number of events on a single-bit input B and always outputs
two unsigned numbers on 16-bit outputs C10 and C01, which are initially 0. An event is a

CS223-Digital Design 2022 Spring – Alper SARIKAN

 change from 0 to 1 (C01 is incremented by 1) or from 1 to 0 (C10 is incremented by 1).
Assume the system count rolls over when the maximum value of either C10 or C01 is reached.
(a) Capture the system behavior as an HLSM and draw the state transition diagram.
(b) Create a datapath for your HLSM. Label the input/output signals of all components.

Q20. Design a high-level state machine (HLSM) that counts the number of 0’s in an 8-bit input A
and outputs the result on a 4-bit output C, which is initially 0. The computation starts when a
single-bit input b changes from 0 to 1. The input b becomes 1 for one clock cycle and then it
returns to 0. The computed result should be held at the output until the next time b changes
from 0 to 1 and a new value is computed.
(a) Capture the system behavior as an HLSM and draw the state transition diagram.
(b) Create a datapath for your HLSM. Label the input/output signals of all components.
(c) Connect the datapath to the controller and show all signals between two units.
(d) Derive the FSM and draw the state transition diagram.

Q21. Design a circuit (HLSM) with a clock input and two outputs and . The circuit will
generate output for 5ms then for 25ms then for 12ms and
for 6ms. You are given a clock signal, up-down counters, multiplexers, registers,
D flip-flops and logic gates. You may also use a timer in your circuit. Show your design
clearly by showing the connections, number of bits and clock frequency.

Q22. The state transition diagram of an FSM is given below. You will design the controller for
this FSM using only a minimum number of 4:1 multiplexers and 2:1 multiplexers.

(a) Write the state transition table and output table for the FSM using binary state encodings.
(b) Write the Boolean equations for the next state and output of FSM.
(c) Sketch the circuit schematic of FSM using state register, two 4:1 multiplexers, and two 2:1
multiplexers. Don’t use any logic gate. You can use the logic levels 1 and 0 as input.

CS223-Digital Design 2022 Spring – Alper SARIKAN

Q23. For the sequential circuit (FSM) given below (B is the input, Q is the output)

S2
S1
S0
S2

S1

S0
0 000
0 001
CLK
1 010
B 011

CLK
1 100 Out D Q
S2
1 101
reset

1 110
B 1
reset
111

8:1 Multiplexer CLK

S2
S1
S0
CLK
D Q
S1

S2
S1
S0
reset

reset

S2

S1

S0
0 000
0

S2

S1

S0
1 001

1
000
1 010

0
001
B 3 4
011
010
0 100 Out
Q
0
011
1 101

1
100 Out
1 110
1
101
1 111
110
0 111
CLK 8:1 Multiplexer
8:1 Multiplexer

CLK
D Q
S0
S2
S1
S0

reset

reset
S2

S1

S0

1 000
1 001
0 010
B 011
1 100 Out
1 101
1 110
0 111

8:1 Multiplexer

(a) Write the Boolean equations for the next-state and output logic in sum-of-products form.
(b) Write the state transition and output tables given below.
Present State Input Next State Output

S2 S1 S0 B S’2 S’1 S’0 Q

0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1

(c) Draw the state transition diagram for this FSM. Disregard (don’t draw) any states that
cannot be entered.
(d) Analyze the finite state machine and in one or two sentences, tell what it does. You should
summarize the overall function of the FSM. Do not go into details like “when in this state,
if such-and-so happens, then this happens...”, etc.

CS223-Digital Design 2022 Spring – Alper SARIKAN

Q24. Design a Finite State Machine (FSM) using the state transiton diagram given below

(a) Using binary state encodings, write the state transition table and output table for the FSM.
Write Boolean equations for the next state and output logic.
(b) Sketch a schematic for your FSM circuit.

Q25. A register file has 16 registers each having 16 bits. The registers RF[0] to RF[15] contain
positive or negative integers. Design an HLSM which will find the sum of absolute values of
the 16 integers stored in RF[0] to RF[15]. The negative numbers are in 2’s complement form.
The sum is going to be stored in a separate SUM register. Upon reset, the HLSM will be in the
initial state waiting for the GO signal. When the operation is completed the HLSM will return
to its initial state and wait for a GO signal to start over again. Show your design clearly.
(a) Capture the system behavior as an HLSM and draw the state transition diagram.
(b) Design the datapath for this HLSM. Specify each component in the datapath clearly (i.e.
name of the component, input signals, output signals, number of bits, etc.).
(c) Connect the datapath to the controller (FSM) and show the signals between the controller
and the datapath.
(d) Derive the FSM and draw the state transition diagram.

CS223-Digital Design 2022 Spring – Alper SARIKAN