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Verilog_notes topper notes

The document explains the structure and components of a Verilog testbench, including module declaration, data types (reg and wire), and the connection of circuits using gates. It details how to apply test vectors, display outputs, and record signal changes during simulation. Additionally, it provides syntax for common format specifiers and the basic format for writing a testbench.

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nishitaraghvendra
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8 views

Verilog_notes topper notes

The document explains the structure and components of a Verilog testbench, including module declaration, data types (reg and wire), and the connection of circuits using gates. It details how to apply test vectors, display outputs, and record signal changes during simulation. Additionally, it provides syntax for common format specifiers and the basic format for writing a testbench.

Uploaded by

nishitaraghvendra
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Testbench Explained:

 module _name_;
This is written when we start a new section of the code and is like a small box where
we write our instructions. It can be named anything.
 reg a,b;
wire _exit_port_name, output_port_name;
a and b are given the datatype register which will get turned on and off. They act like
inputs.
The wire datatype will carry out the outputs from the gates/circuits. Both of these
things can be named anything.
Remember the wire is the output and reg is the register which is the input type.
 Then we connect our circuits/gates.
and_gate and1 (
.a(a),
.b(b),
.result(and_out)
);
Each block in this sample connects a specific type of gate, it can be a circuit as well.
The line inside tells the machine to take the input and process them through the logic
gate given and then send the result out through the specific wire name.
why are we writing .a(a), what if we write something else inside the bracket and why
is there a dot
the ‘.a(a)’ is used to connect the internal port of the module (‘a’) to a signal outside
the module. The dot indicates which specific port we are connecting it to.
‘.a(a)’ means "connect the module's internal port ‘a’ to the signal called ‘a’ in the
testbench."
The first ‘a’ after the dot is the name of the internal port defined in the module and the
‘a’ inside the bracket is the signal or wire in the testbench that we wish to connect to
the port.
The dot ‘(.)’ helps Verilog know that you are specifying which port inside the module
you want to connect to something in the testbench. Without it, Verilog would not
know which internal port you’re referring to.
 a = 0; b = 0;
#10;
$display("a=%b, b=%b, AND=%b, XOR=%b, NOR=%b, XNOR=%b", a, b, and_out,
xor_out, nor_out, xnor_out);
Here we are testing different combination of the switches to find out the outputs. The
#10 tells the amount of time the machine should wait before checing the result.
The thing inside the display tells what to print.
 $finish
End
This tells the machine that the test is complete and the block is now closed.
The Display syntax
$display("input1=%b, input2=%b, AND=%b, XOR=%b, NOR=%b, XNOR=%b", input1,
input2, and_output, xor_output, nor_output, xnor_output);
The things inside the inverted comma except the ‘%b’ will be printed out exactly in the
output. The first %b corresponds to input1, the second %b corresponds to input2, the third
%b corresponds to and_output, and so on.
Common Format Specifiers:
 %b: Binary format.
 %d: Decimal format.
 %h: Hexadecimal format.
 %o: Octal format.
 %s: String format.
 %c: Character format.

Basic format for writing in testbench:


module testbench_name;
// Declare reg and wire variables
reg input_signal1, input_signal2; // Input signals to DUT
wire [width-1:0] output_signal; // Output signal from DUT
// Instantiate the DUT (Design Under Test)
dut_module_name dut_instance ( #dut instance is the name of what to identify the module
with inside the testbench.
.input1(input_signal1),
.input2(input_signal2),
.output(output_signal)
);
// Initial block to apply stimulus to the inputs
initial begin
// Apply test vectors to input signals
input_signal1 = value1;
input_signal2 = value2;
// Wait for a certain time
#time_unit;
// More test vectors
input_signal1 = value3;
input_signal2 = value4;
// Wait for a certain time
#time_unit;
// Finish simulation
$finish;
end
// Optional: Monitor or display signals
initial begin
$monitor("time=%0t input1=%b input2=%b output=%b", $time, input_signal1,
input_signal2, output_signal);
end
endmodule
$dumpfile("dump.vcd");: Opens a file named dump.vcd for output. The .vcd (Value Change
Dump) file records all changes in the signals during simulation, which can be viewed using a
waveform viewer.
$dumpvars(1, test);: Specifies which signals to record in the dump.vcd file. The 1 specifies
that all signals in the test module should be recorded.
Module Explained:
 Module declaration is the first thing to write. Here we write the name of the module
and the inputs and outputs name.
 Next is we use the assign statement where we assign what logic the module has to use
or what function it has to use.
 Verilog uses operators like & for AND, | for OR, ^ for XOR, etc., to define logic
 And at the end we write endmodule.
module and_gate (
// Port declarations
input a, // First input
input b, // Second input
output result // Output of AND operation
);

// Logic description
assign result = a & b; // AND operation

endmodule

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