MODULE 4

1 What is the need for array multipliers (3) [June 2022]

Scheme: 3 points( 3 marks)

o Efficient Multiplication: Array multipliers provide a structured and efficient

way to perform binary multiplication, which is a fundamental operation in
many computing tasks.
o Regular and Scalable Design: Their structured layout allows for easy scaling
to handle larger bit-widths, facilitating multiplication of larger binary numbers
without a significant increase in complexity for hardware implementation.
o Wide Application in Digital Signal Processing and Computation: Array
multipliers are widely used in digital signal processing (DSP), graphics
processing units (GPUs), and other computational devices where fast and
reliable multiplication is crucial.

2 Mention the worst-case delay associated with Carry-Bypass adder, Linear Carry-Select adder,
Square- root carry select adder (3) [June 2022]
Scheme: Time delay equation Carry-Bypass adder (1 mark), Linear Carry- Select adder (1
mark), Square- root carry select adder (1 mark)
Carry bypass adder:

tsetup : the fixed overhead time to create the generate and propagate signals
tcarry : the propagation delay through a single bit. The worst case propagation delay through a
single stage of M bits is approximately M times larger.
tbypass : the propagation delay through the bypass multiplexer of a single stage.
tsum: the time to generate the sum of the final stage.
Linear Carry- Select adder

tsetup, tsum and tmux are fixed delays

N – total no. of bits
M- total no. of bits per stage
tcarry – delay of the carry through a single full adder cell
Square- root carry select adder
3 What is a carry-bypass adder? Write the expression for delay associated with carry-bypass
adder. (3) [ May 2023]
Scheme: Definition (1 mark) ,Delay equations of Carry-Bypass adder (1 mark) describing
each term (1 mark)
Definition: A carry-bypass adder is an adder implementation that improves on the delay of
a ripple-carry adder with little effort compared to other adders. The performance is increased with
only some of the combinations of input bits. If (P0P1P2P3 = 1 ) then a mux selects the input carry
to output thereby eliminating the waiting time for carry rippling through the circuit.

tsetup : the fixed overhead time to create the generate and propagate signals
tcarry : the propagation delay through a single bit. The worst case propagation delay through a
single stage of M bits is approximately M times larger.
tbypass : the propagation delay through the bypass multiplexer of a single stage.
tsum: the time to generate the sum of the final stage.

4 Describe the basic functions of an array multiplier (3) [ May 2023]

Scheme: Any three function (3 marks)

Generation of Partial Products: Each bit of one multiplicand is multiplied by each bit of the
other multiplicand to create intermediate partial products.

Organization and Summation of Partial Products: The partial products are arranged in a
matrix or array format, and a series of adders are used to sum these partial products column-
wise, including the carry from previous additions.

Propagation of Carries and Final Summation: Carries generated during the addition
process are propagated to the next higher bit position. The final summation of these adjusted
partial products results in the final binary product of the two input numbers.

5 What is the critical path and worst case delay in a 16 bit ripple carry adder? (3) [June 2023]
Scheme: Critical path -1.5 marks, worst case delay -1.5 marks
Critical path is from input to output.
Worst case delay:

Here N=16, tadder = 15tcarry+tsum

6 Compare the delay performance of ripple carry, linear select and square root carry select
adders as the number of bits increases. (3) [June 2023]
C input Scheme: Graph-2 marks, Explain-1 mark

Propagation delay tp is linear wit the number of bits N in both ripple carry adder and bypass
adder. The slope of delay function increases in a more gradual fashion in bypass adder than
for ripple carry adder. For lesser no of bits ripple carry adder is faster. (bypass multiplexer
delays the bypass adder) The crossover point depends on technology considerations and
normally between 4 and 8 bits. Delay is proportional to square root of N for square root carry
select adder. For large value of N, tadd become almost a constant for square root carry select
adder.
1. Derive the expression for Generate, Propagate and Delete signals from the truth table of a
full adder. (3) [Jan 2024]
 The sum and carry out can be defined as functions of some intermediate signals G
(generate), P (propagate) and D (delete).
G = 1 ensures that a carry bit will be generated at Co, independent of Ci
D = 1 ensures that a carry bit will be deletedat Co,independent of Ci
P = 1 guarantees that an incoming carry will propagate to Co

2. Explain the principle of carry select adder (3) [Jan 2024]

In ripple carry –full adder cell has to wait for incoming carry before outgoing carry can be
generated. Solution to reduce this delay by evaluating both possible value of carry input in
advance. Once the real value of the incoming carry is known ,correct result is easily selected
with a simple multiplexer stage. Implementation of this idea appropriately called the carry
select adder.

Essays:
9a) With diagram illustrate the principle of operation of an array multiplier (4) [June 2022]
Scheme: Array Multiplier representation (2 marks) operation (2 marks)

Generation of Partial Products: Each bit of one multiplicand is multiplied by each bit of the
other multiplicand to create intermediate partial products. This is implemented with the help
of AND gates.

Organization and Summation of Partial Products: The partial products are arranged in a
matrix or array format, and a series of adders are used to sum these partial products column-
wise, including the carry from previous additions.

Propagation of Carries and Final Summation: Carries generated during the addition
process are propagated to the next higher bit position. The final summation of these adjusted
partial products results in the final binary product of the two input numbers.

b) Design a 16-bit square-root carry select adder and indicate the worst-case delay (10) [June
2022]
Scheme: 16-bit square-root carry select adder block diagram (4 marks) principle of operation
(4 marks) expression for the worst-case delay (2 marks)
Or
12 b) Explain the working of 16-bit linear carry adder with a neat block diagram (6) [ May
2023]
Scheme: 16-bit linear-root carry select adder block diagram (3 marks) principle of operation
(3 marks)
Or
 b) With block diagram illustrate the principle of operation of a square root carry select
adder. Estimate the delay of an n bit adder.(7) [Jan2024]

In linear carry select adder a major mismatch between the arrival time of the signals can be
observed. The result of the carry chains are stable, long before the multiplexer signal can be
observed. So it make sense to equalize the delay through both paths. This can be achieved by
progressively adding more bits to the subsequent stages in the adder, requiring more time for
the generation the carry signals. For eg. first stage can add 2 bits, second contains 3, third has
4 and so forth as in fig. This implementation is the square root carry select adder. The annotated
arrival time shows that this adder topology is faster than the linear organization, even though
an extra stage is needed.
Worst case delay:

tsetup : the fixed overhead time to create the generate and propagate signals
tcarry : the propagation delay through a single bit.
tsum: the time to generate the sum of the final stage.
tmux: delay through the mux.

10 a) Design a 4X4 array multiplier. Show the critical path and also estimate the delay of the
multiplier. (10) [June 2022]
Scheme: 4X4 array multiplier diagram (3 marks) Explanation(3 marks) Partial product
generation(2 marks) expression for time delay (1 mark)
Or
a) With a diagram illustrate the principle of operation of an 4X4 array multiplier. Show the
critical path and also estimate the delay of the multiplier.(8) [ May 2023] [Jan2024]
Scheme: 4X4 array multiplier diagram (3 marks) Explanation (3 marks) expression for time
delay with critical path shown in figure (2 marks)
or b) Draw the implementation of a 4x4 array multiplier.(4) [June 2023]

Scheme: Figure-4 marks

An array multiplier combines the following three function:

partial product generation,
partial product accumulation
final addition
Design:
Inputs and Outputs:

• Inputs: Two 4-bit binary numbers, X=X3X2X1X0 and Y=Y3Y2Y1Y0.

• Output: An 8-bit binary product, Z=Z7Z6Z5Z4Z3Z2Z1Z0

Generation of Partial Products:

• Each bit of Y is multiplied by each bit of X to generate the partial products. This is
performed with the help of AND gates.

In hardware realisation of array multiplier – first two partial products are generated
and added. Then add the third partial product to the first sum.

Arrangement in Array:

• The partial products are arranged in an array, shifting each row to the left by one
position relative to the row above it. The shifting of the partial products for their
proper alignment is performed by simple routing and does not require any logic.
NOTE: You can mark the critical path in main figure itself.

tcarry is the propagation delay between input and output carry,

tsum is the delay between the input carry and sum bit of the full adder, and
tand is the delay of the AND gate.

b) Write the advantages of square-root carry select adder compared to linear carry select adder
(4) [June 2022]
Scheme: Any 4 advantages (4 marks)
1) Delay is proportional to √𝑁compared to N for linear carry select adder.
2) Time delay is reduced and 20-bit addition can be performed in the same time
required for 16-bit addition in linear carry select adder.
3) Require lesser area as number of logic components required for addition of same
number of bits is less.
4) Lesser power consumption as the number of components used is less.

11a) Design static CMOS full adder cell with not more than 28 transistors using logic level
optimisation (8) [ May 2023]
Scheme: Logic optimisation expression 2 marks static CMOS full adder cell circuit diagram
6 marks
Or
a) Draw and explain the circuit diagram using CMOS logic to generate sum and carry out
signals in a 2 bit binary full adder.(7) [June 2023]
Scheme: Circuit-5 mark, Explanation-2 marks
Or
16a) Design a full adder circuit with no more than 28 transistors in standard CMOS logic. (7) [Jan2024]

b) Explain the working of 16-bit carry bypass adder with a neat block diagram (6) [ May 2023]
Scheme: 16-bit carry bypass adder block diagram (3 marks) principle of operation (3 marks)
Or b) With block diagram explain the operation of a 16 bit carry bypass adder. (7) [June 2023]
Scheme: Diagram-4 marks, Explain-3 marks
or
15a) Design a 16 bit carry bypass adder and show the worst case delay path.(7) [Jan2024]

A carry-bypass adder is an adder implementation that improves on the delay of a ripple-carry

adder. In a four bit adder block, suppose the value of Ak and Bk (k=0.....3) are such that all
propagate signals Pk (k=0..3) are high, the incoming carry Ci,0=1 propagates under these
condition through this adder chain and causes an outgoing carry Co,3=1. If (P0P1P2P3 = 1 )
then a mux selects the input carry to output thereby eliminating the waiting time for carry rippling
through the circuit.

When mux select signal BP = P0P1P2P3 = 1, the incoming carry is forwarded immediately to
the next block through the bypass multiplexer Mb,-hence the name carry-bypass adder or carry-
skip adder. If this is not the case, the carry is obtained as in ripple carry adder.

Critical path is shown in grey.

Carry bypass adder:

tsetup : the fixed overhead time to create the generate and propagate signals
tcarry : the propagation delay through a single bit. The worst case propagation delay through a
single stage of M bits is approximately M times larger.
tbypass : the propagation delay through the bypass multiplexer of a single stage.
tsum: the time to generate the sum of the final stage.
From the expression for delay it can be observed that the critical path delay is still linear with
number of bits N.
14a) Explain the implementation of a 16 bit linear carry select adder with block diagram and
compare its delay performance with carry bypass adder.(10) [June 2023]
Scheme: Diagram-4 marks, Explain-3 marks, Delay comparison-3 marks

In ripple carry –full adder cell has to wait for incoming carry before outgoing carry can be
generated. Solution to reduce this delay by evaluating both possible value of carry input in
advance. Once the real value of the incoming carry is known, correct result is easily selected
with a simple multiplexer stage. Implementation of this idea appropriately called the carry
select adder.
Worst case delay of linear carry select adder:

where tsetup, tsum and tmux are fixed delays

N – total no. of bits
M- total no. of bits per stage
tcarry – delay of the carry through a single full adder cell.
The propagation delay of the adder is linearly proportional to N.
Carry bypass adder:

tsetup : the fixed overhead time to create the generate and propagate signals
tcarry : the propagation delay through a single bit. The worst case propagation delay through a
single stage of M bits is approximately M times larger.
tbypass : the propagation delay through the bypass multiplexer of a single stage.
tsum: the time to generate the sum of the final stage.
From the expression for delay it can be observed that the critical path delay is still linear with
number of bits N.
So, for both adders the delay is still linear with number of bits N.