Chapter Computer Architecture Instruction Set An instruction set also called Instruction Set Architecture (ISA) is a group of commands for a CPU in machine language. The term can refer to all possible instructions for a CPU or a subset of instructions to enhance its performance in certain situations. Ingeneral, ISA defines the supported instructions, data types, registers, the hardware support for managing main memory, fundamental features (such as the ‘memory consistency, addressing modes, virtual memory) and I/O model of family of implementations of the ISA. Following are the commonly known instruction sets : @ csc (i) RISC (ii) EPIC Complex Instruction Set Computing/Computer (CISC) Itisa computer architecture in which single instruction, can execute several low-level operations (such as load from memory, an arithmetic operation and a memory store) or are capable of multistep operations or addressing modes within single instructions. The CISC architecture contains a large set of computer instructions that range from very simple to very complex and specialised. The primary goal of CISC architecture is tocomplete a task in as few lines of assembly as possible. This is achieved by building processor hardware that is capable of understanding and executing a series of operations, e.g. we want to find the product of two numbers-one stored in location 2 : 3 and another stored in location 5 : 2 and then store the product back in location 2 : 3. For this particular task, a CISC processor would come prepared with a specific instruction (ie. MULT). When executed, this instruction loads the two values into separate registers, multiplies the operands in the execution unit and then stores the product in the appropriate registers. Thus, the entire task of multiplying two numbers can be completed with one instruction. MULT 2:3, 5:2 Some characteristics of CISC are given below : (@) A large number of instructions- typically from 100 to 250 instructions and of variable nature. (ii) A large variety of addressing modes- typically 5 to 20 different modes and more data type. (iii) Variable-length instruction formats. (iv) Some instructions that perform specialised tasks and are used infrequently. (v) It is used for instructions that manipulate operands in memory. (vi) A small number of general purpose registers. Examples of CISC processors are Intel 386, Intel 486, Pentium Pro, Pentium LI, Motorola's 68040 etc. Reduced Instruction Set Computing/Computer (RISC) RISC microprocessor has a relatively limited number of instructions. It is designed to perform a smaller number of types of computer instructions, so that it can operate ata higher speed (perform more million of instructions pper second). This concept was developed with the belief that a computer uses only 20% of the instructions, making the other 80% unnecessary. ‘A processor based on this concept would use few instructions, By reducing the number of instructions to only those most frequently used, the computer would get more work done in a shorter amount of time. RISC processors only use simple instructions that can be executed within one clock cycle. Thus, the MULT command described above could be divided into three& Separate commands: LOAD which moves data from the memory bank to register, PROD which finds the product of two operands located within the register and STORE which moves data from a register to the memory banks. In order to perform the exact series of steps described in the CISC approach, a programmer would need to code four lines of assembly : LOAD A, 2:3 LOAD B, 5:2 PROD A, B STORE 2:3, A ‘Some characteristics of RISC are given below : (j) Relatively few instructions and few addressing modes (ii) For executing each instruction in a computer, the RISC processors requires one CPI and each CPI includes fetch, decode and execute method applied {in computer instruction. (iii) Simple and limited instruction reduces the execution time of a process in a RISC. * Transistors used for storing complex instructions + small code sizes + Emphasies on Hardware «Instructions are of complex nature. Nature thus offers complex instruction decoding. ‘As size of instructions here is variable thus more than ‘one clock cycle may be used for instruction executing. (iv) The pipelining technique is used in the RISC processors to execute multiple parts or stages of instructions to perform more efficiently. (v) RISC processors are optimised with multiple registers that can be used to store instruction and quickly respond to the computer and minimise interaction with computer memory. (vi) Memory access limited to load and store instructions. (vii) All operations are done within the register of the CPU. (viii) Fixed-length and easily-decoded instruction set. (i) Single cycle instruction execution. (x) Spends more transistors on memory registers large code sizes. Emphasize on Software Examples of RISC processors are IBM RS 6000, MC88100, DEC's Alpha 21064, 21164, 21264 processors etc. Prep Guide MAH-MCA CET Explicitly Parallel Instruction Computing/Computer (EPIC) EPIC refers to architecture in which features are provided to facilitate compiler enhancements of Instruction Level Parallelism (ILP) in all programs, while keeping hardware complexity relatively low. Using ILP enhancement techniques such as speculation and prediction, the compiler identifies the operation that can execute in parallel in each cycle and communicates a plan of execution to the hardware. Some characteristics of EPIC are given below : (i) Uses parallel instructions. (ii) Programs must be written using sequential semantics with explicitly laid out parallelism. ii) Compiler plays the key role in designing the plan of execution. (iv) The architecture provides the requisite support to the compiler to design the plan of execution successfully. (v) The architecture provides the mechanisms to communicate the compiler’s plan of execution to the hardware. Examples of EPIC processors are Intel IA-64, Itanium processors etc. Interrupt An interrupt is a signal emitted by a device (either hardware or software) attached to a computer or from a program within the computer. It requires the operating system to stop and figure out what to do next. An interrupt temporarily stops or terminates a service or a current process Most I/O devices have a bus control line called Interrupt Service Routine (ISR) for this purpose. Today almost all computing system are interrupt driven. It means that they follow the list of computer instructions in a program and run the instructions until they get to the end or until they sense an interrupt signal. If the latter event happens, the computer either resumes running the current program or begins running another program. In either case, it must stop operations while deciding on the next action. To do this and to work on other programs, the OS uses pauses in operations. When the device processor handles interrupts, it informs the device sending the signal that the Interrupt Request (IRQ) has been recognised. Then the device stop sending the IRQ signal.Computer Concepts Computer Architecture Types of Interrupt ‘There are v0 types of interrupt as follows () Hardware interrupt ‘This interrupt is an electronic signal from an external hardware device that indicates it need attention from the 0S. For example, moving a mouse or pressing a keyboard key. In this example the processor must stop to read the mouse position or key stroke at that instant. In. this type interrupt, all devices are connected to the Interrupt Request Line (IRL). Typically, a hardware IRQ has a value that associates it with a particular device. This makes it possible for the processor to determine which device is requesting service by raising the IRQ and then provide service accordingly. Hardtware interrupt is classified into three types as : (a) Maskable Interrupt Ina processor, an internal interrupt mask register selectively enables and disables hardware requests. When the mask bit is set, the interrupt is enabled. When it is clear, the interrupt is disabled. Signals that are affected by the mask are maskable interrupts. (b) Non-maskable Interrupt In some cases, the interrupt mask cannot be disabled so it does not affect some interrupt signals. These are non-maskable interrupts and are usually high priority events that cannot be ignored. (©) Spurious Interrupt Also known as a phantom or ghost interrupt, a spurious interrupt is a type of hardware interrupt for which no source can be found. These interrupts are difficult to identify if a system misbehaves. If the ISR does not account for the possibility of such interrupts, it may result ina system deadlock. () Software Interrupt A software interrupt occurs when an application program terminates or requests certain services from the 0S. Usually, the processor requests a software interrupt when certain conditions are met by executing a special instruction. ‘This instruction invokes the interrupt and functions like a subroutine call, Software interrupts are commonly used when the system interacts with device drivers or when a program requests OS services. & Software interupts may also be unexpectedly triggered by program execution errors. These interrupts are typically called traps or exceptions. Communication between Processor and I/O Devices ‘The Communication between I/O devices and the processor of the computer system is implemented using an interface unit. In a computer system, data is transferred from an input device to the processor and from the processor to an output device. While transferring data from 1/O devices, some steps are performed follows as ‘© The data is to be transferred is placed on the data bus, by the input devices which transfer single byte of data ata time. ‘ The input devices then issue the data valid signal through the devices control bus to the data register, including that the data is available on the data bus. * As the data register, now holds the data for flag bit of the same register in the interface unit. * The processor now issue an I/O read signal to the data registers in the interface unit. © The data register then places the data on the data bus connected to the processor of the computer system. While transferring data to output devices, some steps are performed as # The processor laces the data that needs to be transferred on the data bus connected to the data register of the interface unit. © The CPU also places the address of the output devices on the devices address bus. © After placing the address and data on the appropriate buses, CPU issue the I/O write signal which writes the data on the data register. *# The data register of the interface unit issue a data accepted signal through the control bus to the processer. © The interface unit then places the data stored in the data register on to the data bus connected to the device controller of the output devices. ‘* The output devices then receive the data and sends acknowledgment signal to the processor.EXERCISES = Chapter Challenges 4. A/AM sesosesves 8 @ group of commands for a CPU in machine language. (a) Instruction set () Interrupt (PCL (@) Deadlock 2. Which of the following architecture contains a large set of computer instructions that range from very simple to very complex and specialised? (a) RISC @)cIsc (© EPIC (@) None of these 3. Example of ..........» processors are IBM RS 6000, MC 85100, DEC’s Alpha 21064, 21164, 21264 processors etc. (a) CISC (b) RISC (©) EPIC (@) None of these 4. It is designed to perform a smaller number of types of computer instructions, so that it can operate at a high speed. (a) CISC (b) RISC 5. RISC processors only use simple instructions that can be executed within (@) access time (©) one bit (©) one clock per cycle (d) All of these 6. Which of the following is a signal emitted by a device attached to a computer or from a program within the computer? (a) Instruction set (b) Scheduling (©) Paging (@) Interrupt 7. This interrupt is an electronic signal from an external hardware device that indicates it needs attention from the OS. (@) Software interrupt (©) Normal interrupt 8. Which of the following is/are type(s) of hardware interrupt? (a) Maskable interrupt (©) Non-maskable interrupt (©) Spurious interrupt (@) All of the above (©) Interrupt (4) Bus (b) Hardware interrupt (4) Driver interrupt 9, Signals that are affected by the mask are called (a) Maskable interrupt (@) Normal interrupt 10. If ISR does not account for the possibility of such interrupt. Which type of interrupt may result in a system deadlock? (@) Maskable interrupt (©) Non-maskable interrupt (©) Spurious interrupt (4) Normal interrupt 11. Which interrupt occurs when an application program terminates or request certain services from the operating system? (@) Maskable interrupt (©) Spurious interrupt (©) Hardware interrupt (@) Software interrupt 12, Software interrupt may also be unexpectedly triggered by program execution errors. These interrupt are typically called (@) traps () exceptions (©) Both (a) and (b) (@) None of these 13. The communication between I/O devices and the processor of the computer system is implemented using (a) interface unit (b) interrupt (©) instruction set (d) deadlock 14, Which of the following devices is having a highest priority while assigning interrupt? (@) Hard Disk (b) Printer (c) Key board (d) Floppy 15. In implementing interrupt, action that is done by the hardware include (a) souring all the register on stack (b) souring the interrupt vector into special register () fetching the address of the interrupt handler (@) Both (b) and (e)Computer Concepts Computer Architecture B Previous Years’ Questions (PYOs) 46. Ifa processor clock is rated as 2500 million cycles pet second, then its clock period is 022, (a) 20x 10° sec (b) 4.00% 10°" sec (0) 1.00 10°" see (a) None of these 47. The process when processor fetch or decode another instruction during the execution of current instruction is called (oan) {a) Supercomputing, () Pipelining (Cloud computing (4) Grid computing 48. Which of the following is used by ALU to store the intermediate results? rom (a) Stack (b) Heap (©) Registers (@) Accumulators 19. Consider a computer system with speed of 10° instructions per second. A program P, having 2n? steps is run on this system, where n is the input size. If n =10000, what is the execution time for P? (2021) @12s &)2s (100s (A) 200 20, The time required for fetching and execution of one simple machine instruction is known as [2020] (a) Delay time (b) CPU cycle (©) Real Time (d) Seek Time 3} 21, Let the memory access time is 10 milliseconds and cache access time is 10 microseconds. Assume the cache hit ratio 15%, The effective memory access time is (2018, 17) (a) 2 milliseconds (b) 15 milliseconds (©) 1.85 microseconds (d) 1.85 milliseconds 22, Consider a hard disk with 16 recording surfaces (0-15) having 16384 cylinders (0 -16383) and each cylinder contains 64 sectors (0 -63). Data storage capacity in each sector is 512 bytes. Data are organised cylinder-wise and the addressing format is < cylinder no., surface no,, sector no.>. A file of size 42797 KB is stored in the disk and the starting disk location of the file is <1200, 9, 40>. What is the cylinder number of the last sector of the file, if sX% Count Your Score Chapter Challenges L @ 20) | 3 ob) | 4 0) | 5%. © I (@) 12. (c) | 13. (a) 4 (0) 15. (d) Previous Years’ Questions (PYQs) 1 ) | i ® | 8 @ | 1% @ | 0 OH it is stored in a continuous manner? 01g) (a) 1284 (b) 1282 (©) 1286 (@) 1288, 23. A hard disk has a rotational speed of 6000 rpm. Its average latency time is (pov) (a) 5x 107 sec (b) 0.05 sec (©) 1 sec (a) 05 see | e@ | 20 | sa@ iam lwo Jau@ leo | |