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Clock divider-verilog codes

The document describes various digital circuit modules implemented in Verilog, including a binary up-down counter, JK flip-flop, T flip-flop, 3-bit ripple counter, and a universal shift register. Each module utilizes clock division to create a 2 Hz clock signal from a 100 MHz input clock and performs specific operations such as counting, toggling, and shifting. The document includes code snippets and explanations for the functionality of each module.

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2021ecshreyashkumarbsb
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6 views

Clock divider-verilog codes

The document describes various digital circuit modules implemented in Verilog, including a binary up-down counter, JK flip-flop, T flip-flop, 3-bit ripple counter, and a universal shift register. Each module utilizes clock division to create a 2 Hz clock signal from a 100 MHz input clock and performs specific operations such as counting, toggling, and shifting. The document includes code snippets and explanations for the functionality of each module.

Uploaded by

2021ecshreyashkumarbsb
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Binary up down counter using clock division

Module upcounter_4bit (clk, q, rst);

Input clk, rst;

output [3:0]q;

Reg[3:0]q=4’b0;

Reg newclk;

Reg[27:0]count=0;

always@(posedge clk)

begin

count=count+1;

newclk=count[26]; // clock division at bit 26 corresponds to 2hz

end

always@(posedge newclk)

begin

if(rst)

q=0;

else

q=q+1; // up counting operation

q=q-1; // down counting operation

end

endmodule

Note: the first always block corresponds to clock division operation


(100 MHz frequency divided to 2 Hz)
The second always block, which performs binary up and down
count operation…
JK flip flop using clock division (perform toggle operation)

Module jk_flipflop (jk, rst, q, qb, clk);

Input jk [1:0];

Input rst, clk;

Output q,qb;

Reg newclk;

Reg[27:0]count=0;

always@(posedge clk)

begin

count=count+1;

newclk=count[26]; // clock division at bit 26 corresponds to 2hz

end

initial

begin

q=1’b0; q=1’b1;

end

always@(posedge newclk) // new clk corresponds to 2 hz used for jk flip flop operation

begin

if(rst)

q=0;

else

case(jk)

2’b00: q=q;

2’b01:q=0;

2’b10:q=1;

2’b11:q=0;
endcase

Qb=~q;

end

endmodule

Note: the first always block corresponds to clock division operation


(100 MHz frequency divided to 2 Hz)
The second always block, which performs jk flip flop
operation…

T flip flop using clock division (perform toggle operation)

Module T_flipflop (t, q, qb, clk);

Input t;

Input, clk;

Output q,qb;

Reg newclk;

Reg[27:0]count=0;

always@(posedge clk)

begin

count=count+1;

newclk=count[26]; // clock division at bit 26 corresponds to 2hz


end

initial

begin

q=1’b0; q=1’b1;

end

always@(posedge newclk) // new clk corresponds to 2 hz used for T flip flop operation

begin

if(t=0)

q=0;

else

q=1;

end

qb=~t;

endmodule

Note: the first always block corresponds to clock division operation


(100 MHz frequency divided to 2 Hz)
The second always block, which performs T flip flop operation…

3-bit ripple counter

Module ripple_3bit (clk,q);

Input rst, clk;

Output q;

Output reg[2:0]q;

Reg newclk;

Reg[27:0]count=0;
always@(posedge clk)

begin

count=count+1;

newclk=count[26]; // clock division at bit 26 corresponds to 2hz

end

// body of the 3 bit ripple counter

always@(posedge newclk) // new clk corresponds to 2 hz used for ripple counter operation

begin

q[0]=~q[0];

q[1]=~q[1];

q[2]=~q[2];

end

endmodule

Universal shift register to perform shift right, shift left, parallel and
load operation

Module universal shift register (clk, rst, lsi,rsi,din,s0,s1,q);

Input rst, clk, lsi,rsi,s1,s0;

Input [N-1:0]din;

Parameter N=4; // define 4 bit shift register

Output reg[N-1:0]q;

Reg newclk;

Reg[27:0]count=0;

always@(posedge clk)

begin

count=count+1;

newclk=count[26]; // clock division at bit 26 corresponds to 2hz


end

//shift register body

always@(posedge newclk or reset) // new clk corresponds to 2 hz used for shift register operation

if(!rst)

q={N{1’b0}};

else

case({s1,s0})

2’b00:q=q; // no change

2’b01:q={lsi,q[N-1:1]}; //shift right

2’b10: q={q[N-2:0],rsi}; // shift left

2’b11:q=din; // parallel load

endcase

endmodule

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