EM78P468N

OTP ROM

EM78P468N
8-BIT MICRO-CONTROLLER

Version 1.0
 EM78P468N
OTP ROM

Specification Revision History

Version Content
1.0 Initial version 2004/4/10

Application Note

This specification is subject to change without prior notice. 2 04.10.2004 (V1.0)

 EM78P468N
OTP ROM

1. GENERAL DESCRIPTION

The EM78P468N is an 8-bit RISC type microprocessor with high speed CMOS technology and low
power consumption. Integrated onto a single chip are on chip watchdog (WDT), Data RAM, ROM,
programmable real time clock counter, internal/external interrupt, power down mode, LCD driver
IROUT function, and tri-state I/O. It provides a PROTECTION bit to protect against intrusion of user’s
code in the OTP memory and a 10-OPTION bit to accommodate user’s requirements. It also provides a
especial 13 bits customer ID option.

With its OTP-ROM feature, the EM78P468N offers a convenient way of developing and verifying user’s
programs. Moreover, user developed code can be easily programmed with the ELAN writer.

2. FEATURES

CPU
Operating voltage range : 2.2V 5.5V
Operating temperature range: -40°C ~ +85°C.
Dual clock operation
High frequency oscillator can select between Crystal, RC, or PLL (phase lock loop)
Low frequency oscillator can select between Crystal or RC mode
Totally 272 bytes SRAM
144 bytes general purpose register
128 bytes bits on chip data RAM
4K*13 bits on chip Electrical OTP-ROM (One Time Programmable Read Only Memory).
Up to 28 bi-directional tri-state I/O ports
Typically, 12 bi-directional tri-state I/O ports.
16 bi-directional tri-state I/O ports shared with LCD segment output pin.
8-level stack for subroutine nesting
8-bit real time clock/counter (TCC)
One IROUT/PWM generator
Four sets of 8 bit auto reload counter/timer can be used as interrupt sources
Counter 1: independent counter
Counter 2, High Pulse Width Timer (HPWT), and Low Pulse Width Timer (LPWT) shared with IR
function

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OTP ROM

Programmable free running on chip watchdog timer (WDT)

Low voltage detector (LVD)
Operation modes
Normal mode :CPU operate on high frequency oscillator
Green mode :CPU operate on low frequency oscillator
Idle mode :CPU idle, LCD display remains working
Sleep mode :whole chip stop working
Input port wake up function (PORT6, PORT8)
9 interrupt sources, 3 external, 6 internal
Internal: TCC; Counter1, 2; High pulse width timer; Low pulse width timer; & Low voltage detector
External: INT0, INT1, & Pin change wake-up (Port 6 and Port 8)
59 pin dice/ 64 pin QFP package

LCD
Common driver pins: 4
Segment driver pins: 32
1/3, 1/2 bias
1/4, 1/3, 1/2 duty

Applications
Remote control for air conditioner
Health care
Home appliances

This specification is subject to change without prior notice. 4 04.10.2004 (V1.0)

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OTP ROM

3. PIN ASSIGNMENTS

P5.7/ IROUT
SEG29/ P8.5

SEG30/ P8.6

SEG31/ P8.7

P5.5/ INT1
P5.6/ TCC
P6.7

P6.6

P6.5

P6.4

P6.3

P6.2

P6.1

P6.0
NC

NC

NC

NC

NC
37

36

35

34

33
51

50

49

48

47

46

45

44

43

42

41

40

39

38
SEG28/ P8.4 52 32 P5.4/ INT0

SEG27/ P8.3 53 31 XOUT

SEG26/P8.2 54 30 XIN

SEG25/P8.1 55 29 VDD

SEG24/P8.0 56 28 OSCO

SEG23/P7.7

SEG22/P7.6
57

58
EM78P468N 27

26
R-OSCI

GND

SEG21/P7.5 59 64 QFP 25 /RESET

SEG20/P7.4 60 24 VLCD 3

SEG19/P7.3 61 23 VLCD 2

SEG18/ P7.2 62 22 VA

SEG17/ P7.1 63 21 VB

SEG16/ P7.0 64 20 COM 0

10

11

12

13

14

15

16

17

18

19
1

9
SEG 9

SEG 8

SEG 7

SEG 6

SEG 5

SEG 4

SEG 3

SEG 2

SEG 1

SEG 0
SEG 15

SEG 14

SEG 13

SEG 12

SEG 11

SEG 10

COM 3

COM 2

COM 1

Fig. 1 EM78P468N Pin Configuration for 64 Pin QFP Package

Table 1 Pin Description

PIN PIN number I/O type Description
VDD 29 I * Power supply pin
GND 26 I * System ground pin
* In crystal mode: crystal input
* In RC mode: resistor pull high.
R-OSCI 27 I
* In PLL mode: connect 0.01 F capacitance to GND
* Must be pull high or low when high frequency is not use
* In crystal mode: crystal output
OSCO 28 O * In RC mode: instruction clock output
* Must be pull high or low when high frequency is not use.
*In crystal mode: Input pin for sub-oscillator. Connect to a
Xin 30 I 32.768KHz crystal
* RC mode: this pin is connected with a resistor to high level.
* In crystal: Connect to a 32.768KHz crystal
Xout 31 O
* In RC mode: instruction clock output
* Low active. If set as /RESET and remains at logic low, the
/RESET 25 I
devices will be reset

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OTP ROM

PIN PIN number I/O type Description

* General purpose I/O pin. /external interrupt.
* INT0 interruption source can be set to falling or rising edge by
P5.4/INT0 32 IOC81 register bit 7 (INT_EDGE).
I/O
P5.5/INT1 33 * INT1 interruption source is a falling edge signal.
* All pins wake up from sleep mode when the pin status
changes.
* General purpose I/O/ external counter input
P5.6/TCC 34 I/O
* This pin works in idle mode.
* General purpose I/O pin or IR mode output pin,
P5.7/IROUT 37 I/O
* Capable of sinking 20mA/5V.
* General purpose I/O pin.
P6.0
* Pull-high/ pull-low/ Open drain function support.
~ 38~45 I/O
* All pins can wake up from sleep and idle modes when the
P6.7
pin status changes.
COM3~0 17~20 O * LCD common output pin.
SEG0~SEG15 16~1 O * LCD segment output pin.
SEG16/P7.0 64
* LCD segment output pin. Can be shared with general purpose
~ ~ O/(I/O)
I/O pin
SEG23/P7.7 57
SEG24/P8.0 56 * LCD segment output pin. Can be shared with general I/O pin
~ ~ * For general purpose I/O use, can wake up from sleep mode
O/(I/O)
SEG30/P8.6 50 and idle mode when the pin status changes.
SEG31/P8.7 46 * For general purpose I/O use, supports pull-low function.
VB 21 * Connect capacitors for LCD bias voltage
VA 22 * Connect capacitors for LCD bias voltage
VLCD2 23 I/O (Power) * One of LCD bias voltage
VLCD3 24 I/O (Power) * One of LCD bias voltage

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4. FUNCTION DESCRIPTION

CPU Data RAM

Timing Control LCD driver LCD

ROM IO PORT IO

Oscillator
IR/PWM
PLL/Crystal/RC

Timer/ Counter
R-OSCI
OSCO

Xout
Xin

Oscillator Timing ROM R2 STACK

WDT timer
Control

Interruption
register
R1 (TCC)

Interruption
control
Control w ake-up General RAM
Instruction ALU
on I/O port
decoder
R3
R4
ACC

Data & Control BUS

128 byte
LCD RAM PORT5 PORT6 PORT7 PORT8
Data RAM
R R R R
IOC5 IOC6 IOC9 IOC9
5 6 7 8
Common Segment
driver driver

Fig. 2 System Block Diagram

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4.1 Operational Registers

1. R0 (Indirect Addressing Register)
R0 is not a physically implemented register. It is used as indirect addressing pointer. Any instruct-
tion using R0 as register actually accesses the data pointed by the RAM Select Register (R4).

2. R1 (Time Clock /Counter)

Increases by an external signal edge applied to TCC, or by the instruction cycle clock.
Written and read by the program as any other register.

3. R2 (Program Counter)
* The structure is depicted in Fig. 3
* Generates 4K × 13 on-chip ROM addresses to the relative programming instruction codes.
* "JMP" instruction allows direct loading of the low 10 program counter bits.
* "CALL" instruction loads the low 10 bits of the PC and PC+1, then push it into the stack.
* "RET'' ("RETL k", "RETI") instruction loads the program counter with the contents at the top of
stack.
* "MOV R2, A" allows the loading of an address from the A register to the PC. The contents of the
ninth and tenth bits do not change.
* "ADD R2, A" allows a relative address be added to the current PC. The contents of the ninth and
tenth bits do not change.
* The most significant bit (A10~A11) will be loaded with the content of bits PS0~PS1 in the Status
register (R3) upon execution of a "JMP'' or "CALL'' instruction.

PC
Reset v ector 000H
003H
CALL TCC ov erf low interrupt v ector
00 PAGE0 0000~03FF 006H
RET Exteral INT0 pin interrupt v ector
01 PAGE1 0400~07FF RETL Exteral INT1 pin interrupt v ector 009H
RETI STACK LEVEL 1 00CH
Counter 1 underf low interrupt v ector
10 PAGE2 0800~0BFF STACK LEVEL 2 00FH
Counter 2 underf low interrupt v ector
User Memory Space

STACK LEVEL 3
11 PAGE3 0C00~0FFF high pulse width timer underf low interrupt v ector 012H
STACK LEVEL 4
low pulse width timer underf low interrupt v ector 015H
STACK LEVEL 5
Port 6,Port8 pin change wake-up interrupt v ector 018H
STACK LEVEL 6 01BH
Low v oltage detector interrupt v ector
STACK LEVEL 7
STACK LEVEL 8

On-Chip Program memory

FFFH

Fig. 3 Program Counter Organization

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OTP ROM

ADDRESS
0 0 R0 (Indirect Addressing Register)
0 1 R1 (Time Clock Counter) R5 bit 0 -> 0 R5 bit 0 -> 1
0 2 R2 (P rogram Counter) control re giste r page 0 control re giste r page 1
0 3 R3 (Status Register)
0 4 R4 (RAM select register)
0 5 R5 (P ort5 & IOCP AGE ) IOC50 (P ort5 I/O control & LCD segment)
0 6 R6 (P ort6) IOC60 (P ort6 I/O control ) IOC61(Wake up & P 5.7 sink current)
0 7 R7 (P ort7) IOC70 (P ort7 I/O control ) IOC71(TCC & INT0 control register)
0 8 R8 (P ort8) IOC80 (P ort8 I/O control ) IOC81(WDT control register)
0 9 R9 (LCD control register) IOC90 (128 byte RAM addressl ) IOC91(Counter 1,2 control)
0 A RA (LCD address) IOCA0 (128 byte RAM data bufferl) IOCA1(high/low pulse width timer control)
0 B RB (LCD data buffer) IOCB0 (Counter 1 preset) IOCB1(P ort 6 pull-high control)
0 C RC (LVD control & Counter enable) IOCC0 (Counter 2 preset) IOCC1(P ort 6 open drain control)
0 D RD (system & P LL/Booster frequency ) IOCD0 (High-pulse width timer preset) IOCD1(P ort 8 pull-high control)
0 E RE (IR & INT0/1,TCC control) IOCE0 (Low-pulse width timer preset) IOCE1(P ort 6 pull-down control)
0 F RF (interrupt status register) IOCF0 (interrupt mask register) IOCF1 (interrupt mask register)

10
| 16 byte common register LCD RAM 4*32 bits
1F

20
bank 0 ~ bank 3
| 128 byte data RAM
32 byte common register
3F

Fig. 4 Data Memory Configuration

4. R3 (Status Register)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
-- PS1 PS0 T P Z DC C

Bit 7: Not used

Bit 6, 5 (PS1, 0): Page select bits

PS1 PS0 Program memory page (Address)
0 0 Page 0
0 1 Page 1
1 0 Page 2
1 1 Page 3
User can use PAGE instruction to change page and maintains the program page. Otherwise, user
can use “far jump” (FJMP) or “far call” (FCALL) MACRO to program user's code. The program
page is maintained by EMC's complier. It changes the user's program by inserting instructions
within the program.

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Bit 4 (T): Time-out bit. Set to 1 by the "SLEP" and "WDTC" commands or during power up and
reset to 0 by WDT timeout.
EVENT T P REMARK
WDT wake up from sleep mode 0 0
WDT time out (not sleep mode) 0 1
/RESET wake up from sleep 1 0
Power up 1 1
Low pulse on /RESET X X X: don't care

Bit 3 (P): Power down bit. Set to 1 during power on or by a "WDTC" command and reset to 0 by a
"SLEP" command.
Bit 2 (Z): Zero flag
Bit 1 (DC): Auxiliary carry flag
Bit 0 (C): Carry flag

5. R4 (RAM Select Register)

Bits 7 ~ 6 determine which bank is activated among the 4 banks. See the configuration of the
data memory in Fig.4. Use BANK instruction to change bank.
Bits 5 ~ 0 are used to select up to 64 registers in the indirect addressing mode.

6. R5 (PORT5 and Program Page Select Register)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R57 R56 R55 R54 -- -- -- IOCPAGE

Bit 7~4: 4-bit I/O registers of PORT5

Bit 3~1: Not used
Bit 0 (IOCPAGE): change IOC8 ~ IOCF to another page, 0/1 => page0 / page1

7. R6 (PORT6)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R67 R66 R65 R64 R63 R62 R61 R60

Bit 7~0: PORT 6 8-bit I/O registers

8. R7 (PORT7)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R77 R76 R75 R74 R73 R72 R71 R70

Bit 7~0: PORT 7 8-bit I/O registers

9. R8 (PORT8)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R87 R86 R85 R84 R83 R82 R81 R80

Bit 7~0: PORT 8 8-bit I/O registers

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10. R9 (LCD Control Register)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
BS DS1 DS0 LCDEN -- LCDTYPE LCDF1 LCDF0

Bit 7 (BS): LCD bias select bit, 0/1=>(1/2 bias) / (1/3 bias)

Bit 6,5 (DS1, 0): LCD duty select

DS1 DS0 LCD duty
0 0 1/2 duty
0 1 1/3 duty
1 X 1/4 duty

Bit 4 (LCDEN): LCD enable bit: 0/1 -> LCD circuit disable/enable. When LCD function is disabled,
all common/segment outputs are set to ground (GND) level.
Bit 3: Not used
Bit 2 (LCDTYPE): LCD drive waveform type select bit
0: A type waveform
1: B type waveform

Bit 1, 0(LCDF1, 0): LCD clock pre-scaler ratio control bit

LCD frame frequency (Fs=32.768KHz)
LCDF1 LCDF0
1/2 duty 1/3 duty 1/4 duty
0 0 Fs/(256*2)=64.0 Fs/(172*3)=63.5 Fs/(128*4) =64.0
0 1 Fs/(280*2)=58.5 Fs/(188*3)=58.0 Fs/(140*4) =58.5
1 0 Fs/(304*2)=53.9 Fs/(204*3)=53.5 Fs/(152*4) =53.9
1 1 Fs/(232*2)=70.6 Fs/(156*3)=70.0 Fs/(116*4) =70.6
Fs: sub-oscillator frequency

11. RA (LCD Address)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0 0 0 LCD_A4 LCD_A3 LCD_A2 LCD_A1 LCD_A0

Bit 7 ~ 5: Not used, fixed to “0”

Bit 4~0 (LCDA4~0): LCD RAM address

RB (LCD data buffer)
RA
Bit 3 Bit 2 Bit 1 Bit 0 Segment
(LCD address) Bit 7 Bit 6 Bit 5 Bit 4
(LCD_D3) (LCD_D2) (LCD_D1) (LCD_D0)
00H -- -- -- -- SEG0
01H -- -- -- -- SEG1
02H -- -- -- -- SEG2
| | |
-- -- -- -- SEG29
1EH -- -- -- -- SEG30
1FH -- -- -- -- SEG31
Common X X X X COM3 COM2 COM1 COM0

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12. RB (LCD Data Buffer)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
-- -- -- -- LCD_D 3 LCD_D 2 LCD_D 1 LCD_D 0

Bit 7 ~ 4: Not used

Bit 3~0 (LCD_D3~0): LCD RAM data transfer register

13. RC (LVD Control and Counter Enable Register)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
LVDEN /LV LVDF LVD0 LPWTEN HPWTEN CNT2EN CNT1EN

Bit 7(LVDEN): Enable low voltage detector.

1: enable LVD function.
0: disable LVD function.
Bit 6(/LV): Low voltage detector. This is a read only bit. When the VDD pin voltage is lower than
Vdet (selected by LVD0), this bit will be cleared.
0: the low voltage is detected.
1: the low voltage is not detected or LVD function is disabled.
Bit 5 (LVDF): interrupt flag of Low voltage detector.
Bit 4(LVD0): the low voltage detector select bits
LVD0 Vdet
0 2.1 V
1 2.3 V
LVD0=0: if Vdet voltage drops lower than 2.1V or rises higher than 2.3V, then interrupt occurs.
LVD0=1: if Vdet voltage drops lower than 2.3V or rises higher than 2.5V, then interrupt occur.
Bit 3(LPWTEN): low pulse width time enable bit, 0/1 => disable/enable
Bit 2(HPWTEN): high pulse width timer enable bit, 0/1 => disable/enable
Bit 1(CNT2EN): counter 2 enable bit, 0/1 => disable/enable
Bit 0(CNT1EN): counter 1 enable bit, 0/1 => disable/enable

14. RD (System Clock, Booster Frequency, and PLL Frequency Control

Registers)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
-- CLK2 CLK1 CLK0 IDLE BF1 BF0 CPUS

Bit 7: Not used

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Bit 6~4 (CLK2~0): main clock select bit for PLL mode (code option select)
CLK2 CLK1 CLK0 Main clock
0 0 0 32.768K*130=4.26 MHz
0 0 1 32.768K*65=2.13 MHz
0 1 0 2.13MHz/2
0 1 1 2.13MHz/4
1 -- -- 32.768K*244=8 MHz

Bit 3 (IDLE): idle mode enable bit. This bit will decide the intended mode of the SLEP instruction.
IDLE=”0”+SLEP instruction => sleep mode
IDLE=”1”+SLEP instruction => idle mode

Bit 2,1 (BF1, 0): LCD booster frequency select bit

BF1 BF0 Booster frequency
0 0 Fs
0 1 Fs/4
1 0 Fs/8
1 1 Fs/16

Bit 0 (CPUS): CPU oscillator source select, 0/1=> sub-oscillator (Fs)/ main oscillator (Fm)
When CPUS=0, the CPU oscillator select sub-oscillator and the main oscillator is stopped.

CPU Operation Mode

Code option
HLFS=1
RESET

Normal Mode
Code option
fm:oscillation HLFS=0
fs: oscillation
it must delay a little times for the main CPU: using fosc
oscillation stable w hile your system timing
control is conscientious

CPUS="0"
CPUS="1"

IDLE="0" IDLE="1"
SLEEP Mode SLEP
Green Mode SLEP
IDLE Mode
Fm:stop fm:stop fm:stop
Fs: stop fs: oscillation fs: oscillation
CPU: stop Wake up CPU: using fs w ake up CPU: stop

The w ake up time from sleep to green mode is The w ake up time from idle to green
approximately 18ms+16*1/fs mode is 16*1/fs

Fig. 5 CPU Operation Mode

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15. RE (IR Control and PORT5 Function Pins Set Register)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
IRE HF LGP -- IROUTE TCCE EINT1 EINT0

Bit 7 (IRE): Infrared Remote Enable bit

0: Disable IRE. Disable H/W Modulator Function. IROUT pin fixed to high level
1: Enable IRE. Enable H/W Modulator Function. Pin 6.7 defined as IROUT.
Bit 6 (HF): High frequency.
0: For PWM application, IROUT waveform is created according to high-pulse and low-pulse
width time as determined by the high pulse and low pulse width timers respectively.
1: For IR application mode, the low time sections of the generated pulse is modulated with
the frequency Fcarrier,
Bit 5 (LGP): long pulse.
0: the high-pulse timer register and low-pulse width timer is valid.
1: The high-pulse width timer register is ignored. So the IROUT waveform is dependent on
low-pulse width timer register only
Bit 4: Not used
Bit 3 (IROUTE): control bit is used to define the function of P5.7 (IROUT) pin.
0: P5.7, bi-directional I/O pin.
1: IROUT, in this case, the I/O control bit of P5.7 (bit 7 of IOC5) must be set to “0”
Bit 2 (TCCE): control bit is used to define the function of P5.6 (TCC) pin.
0: P5.6, bi-directional I/O pin.
1: TCC, external input pin of TCC. In this case, the I/O control bit of P5.6 (bit 6 of IOC5)
must be set to “1”
Bit 1 (EINT1): control bit is used to define the function of P5.5 (INT1) pin.
0: P5.5, bi-directional I/O pin.
1: INT1, external interrupt pin. In this case, the I/O control bit of P5.5 (bit 5 of IOC5) must be
set to “1”
Bit 0 (EINT0): control bit is used to define the function of P5.4 (INT0) pin.
0: P5.4, bi-directional I/O pin.
1: INT0, external interrupt pin. In this case, the I/O control bit of P5.4 (bit 4 of IOC5) must be
set to “1”

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16. RF (Interrupt Status Register)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
ICIF LPWTF HPWTF CNT2F CNT1F INT1F INT0F TCIF

Bit 7 (ICIF): Port 6, Port 8, input status changed interrupt flag. Set when PORT6, PORT8 input
changes.
Bit 6 (LPWTF): interrupt flag of internal low-pulse width timer underflow.
Bit 5 (HPWTF): interrupt flag of internal high-pulse width timer underflow.
Bit 4 (CNT2): interrupt flag of internal counter 2 under-flow.
Bit 3 (CNT1): interrupt flag of internal counter 1 underflow.
Bit 2 (INT1F): external INT1 pin interrupt flag.
Bit 1 (INT0F): external INT0 pin interrupt flag.
Bit 0 (TCIF): TCC timer overflow interrupt flag. Set when TCC timer overflows.

17. R10~R3F (General Purpose Register)

R10~R31F and R20~R3F (Banks 0~3) are general purposes register.

4.2 Special Purpose Registers

1. A (Accumulator)
* Internal data transfer, or instruction operand holding
* This is not an addressable register.

2. IOC50 (PORT5 I/O Control and PORT7, 8 for LCD Segment Control Register)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
IOC57 IOC56 IOC55 IOC54 P8HS P8LS P7HS P7LS

Bit 7~4(IOC57~4): PORT5 I/O direction control register

0: set the relative I/O pins as output
1: set the relative I/O pin into high impedance (input pin)
Bit 3(P8HS): Switch to high nibble I/O of Port8 or to LCD segment output as share pins
SEGxx/P8.x pins
0: select high nibble of PORT8 as normal P8.4~P8.7
1: select LCD SEGMENT output as SEG28~SEG31 output
Bit 2(P8LS): Switch to low nibble I/O of Port8 or to LCD segment output as share pins
SEGxx/P8.x pins
0: select low nibble of PORT8 as normal P8.0~P8.3
1: select LCD SEGMENT output as SEG24~SEG27 output

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Bit 1(P7HS): Switch to high nibble I/O of Port7 or to LCD segment output as share pins
SEGxx/P7.x pins
0: select high nibble of PORT7 as normal P7.4~P7.7
1: select LCD SEGMENT output as SEG20~SEG23 output

Bit 0(P7LS): Switch to low nibble I/O of PORT7 or to LCD segment output as share pins
SEGxx/P7.x pins
0: select low nibble of PORT7 as normal P7.0~P7.3
1: select LCD SEGMENT output as SEG16~SEG19 output

3. IOC60 (PORT6 I/O Control Register)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
IOC67 IOC66 IOC65 IOC64 IOC63 IOC62 IOC61 IOC60

Bit 7 (IOC67)~Bit 0(IOC60): PORT6 I/O direction control register

0: set the relative I/O pins as output
1: set the relative I/O pin into high impedance (input pin)

4. IOC70 (PORT7 I/O Control Register)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
IOC77 IOC76 IOC75 IOC74 IOC73 IOC72 IOC71 IOC70

Bit 7 (IOC77)~Bit 0(IOC70): PORT7 I/O direction control register

0: set the relative I/O pins as output
1: set the relative I/O pin into high impedance (input pin)

5. IOC80 (PORT8 I/O Control Register)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
IOC87 IOC86 IOC85 IOC84 IOC83 IOC82 IOC81 IOC80

Bit 7 (IOC87)~Bit 0(IOC80): PORT8 I/O direction control register

0: set the relative I/O pins as output
1: set the relative I/O pin into high impedance (input pin)

6. IOC90 (128 Bytes RAM Address)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0 RAM_A6 RAM_A5 RAM_A4 RAM_A3 RAM_A2 RAM_A1 RAM_A0

Bit 7: Not used, fixed at “0”

Bit 6~0: 128 bytes RAM address

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7. IOCA0 (128 Bytes RAM Data Buffer)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
RAM_D7 RAM_D6 RAM_D5 RAM_D4 RAM_D3 RAM_D2 RAM_D1 RAM_D0

Bit 7~0: 128 bytes RAM data transfer register

8. IOCB0 (Counter 1 Preset Register)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bit 7 ~ Bit 0: All are Counter 1 buffer that user can read and write. Counter 1 is an 8-bit
down-counter with 8-bit pre-scaler that is used as IOCB to preset the counter and read preset
value. After an interruption, it will auto reload the preset value.

9. IOCC0 (Counter 2 Preset Register)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bit 7 ~ Bit 0: All are Counter 2 buffer that user can read and write. The Counter 2 is an 8-bit
down-counter with 8-bit pre-scaler that is used as IOCC to preset the counter and read preset
value. After an interruption, it will reload the preset value.

When IR output is enabled, this control register can obtain carrier frequency output.
If the Counter 2 clock source is equal to FT–
Carrier frequency (Fcarrier) = FT/[2*(preset value+1)*prescaler]

10. IOCD0 (High-Pulse Width Timer Preset Register)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bit 7 ~ Bit 0: All are high-pulse width timer buffer that user can read and write. High-pulse width
timer preset register is an eight-bit down-counter with 8-bit pre-scaler that is used as IOCD to
preset the counter and read preset value. After an interruption, it will reload the preset value.

For PWM or IR application, this control register is set as high pulse width.
If the high-pulse width source clock is FT–
the high pulse width=prescaler*(high-pulse width preset value+1)/ FT

This specification is subject to change without prior notice. 17 04.10.2004 (V1.0)

 EM78P468N
OTP ROM

11. IOCE0 (Low-Pulse Width Timer Preset Register)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit 7 ~ Bit 0: All are low-pulse width timer buffer that user can read and write. Low-pulse width
timer preset is an eight-bit down-counter with 8-bit pre-scaler that is used as IOCE to preset the
counter and read preset value. After an interruption, it will reload the preset value.

For PWM or IR application, this control register is set as low pulse width.
If the low-pulse width timer source clock is FT–
the low pulse width=prescaler*(preset value+1)/ FT

12. IOCF0 (Interrupt Mask Register)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
ICIE LPWTE HPWTE CNT2E CNT1E INT1E INT0E TCIE

Bit 7~Bit 0: interrupt enable bit.

0: disable interrupt
1: enable interrupt
IOCF0 register is readable and writable.

13. IOC61 (Wake Up Register)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
IROCS -- -- -- /WUE8H /WUE8L /WUE6H /WUE6L
Bit 7: IROCS: IROUT/PORT5.7 output sink current set
P5.7/IROUT Sink current
IROCS VDD=5V VDD=3V
0 10 mA 7 mA
1 20 mA 14 mA

Bit 6,5,4: Not used

Bit 3 (/WUE8H): 0/1=> enable/disable P8.4~P8.7 pin change wake up function
Bit 2 (/WUE8L): 0/1=> enable/disable P8.0~P8.3 pin change wake up function
Bit 1 (/WUE8H): 0/1=> enable/disable P6.4~P6.7 pin change wake up function
Bit 0 (/WUE8L): 0/1=> enable/disable P6.0~P6.3 pin change wake up function

This specification is subject to change without prior notice. 18 04.10.2004 (V1.0)

 EM78P468N
OTP ROM

14. IOC71 (TCC Control Register)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
INT_EDGE INT TS TE PSRE TCCP2 TCCP1 TCCP0

Bit 7 (INT_EDGE):
0: P5.4 's (INT0) interruption source is a rising edge signal.
1: P5.4 's (INT0) interruption source is a falling edge signal.
Bit 6 (INT): INT enable flag, this bit is read only
0: interrupt masked by DISI or hardware interrupt
1: interrupt enabled by ENI/RETI instructions
Bit 5 (TS): TCC signal source
0: internal instruction cycle clock
1: transition on TCC pin, TCC period > internal instruction clock period
Bit 4 (TE): TCC signal edge
0: increment by TCC pin rising edge
1: increment by TCC pin falling edge
Bit 3 (PSRE): Prescaler Register enable bit
0: TCC rate 1:1
1: as indicated in the table below:
Bit 2~0 (TCCP2~0): TCC pre-scaler bits.
TCCP2 TCCP1 TCCP0 TCC rate
0 0 0 1:2
0 0 1 1:4
0 1 0 1:8
0 1 1 1:16
1 0 0 1:32
1 0 1 1:64
1 1 0 1:128
1 1 1 1:256

15. IOC81 (WDT Control Register)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
-- -- -- -- WDTE WDTP2 WDTP1 WDTP0

Bit 7 ~ 4:Not used

Bit 3 (WDTE): watchdog timer enable. This control bit is used to enable the Watchdog timer,
0: Disable WDT function.
1: enable WDT function.

This specification is subject to change without prior notice. 19 04.10.2004 (V1.0)

 EM78P468N
OTP ROM

Bit 2~0 (WDTP2~0): watchdog timer pre-scaler bits. The WDT source clock is sub-oscillation
frequency.
WDTP2 WDTP1 WDTP0 WDT rate
0 0 0 1:1
0 0 1 1:2
0 1 0 1:4
0 1 1 1:8
1 0 0 1:16
1 0 1 1:32
1 1 0 1:64
1 1 1 1:128

16. IOC91 (Counter 1, 2 Control Register)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
CNT2S CNT2P2 CNT2P1 CNT2P0 CNT1S CNT1P2 CNT1P1 CNT1P0

Bit 7(CNT2S): Counter 2 clock source select 0/1 => Fs/ Fm*
(*Fs: sub-oscillator clock, Fm: main-oscillator clock)
Bit 6~4(CNT2P2~0): Counter 2 prescaler select bits
CNT2P2 CNT2P1 CNT1P0 Counter 2 scale
0 0 0 1:2
0 0 1 1:4
0 1 0 1:8
0 1 1 1:16
1 0 0 1:32
1 0 1 1:64
1 1 0 1:128
1 1 1 1:256
Bit 3(CNT1S): Counter 1 clock source select 0/1 => Fs/ Fm*
(*Fs: sub-oscillator clock, Fm: main-oscillator clock)
Bit 2~0 (CNT1P2~0): Counter 1 prescaler select bits
CNT1P2 CNT1P1 CNT1P0 Counter 1 scale
0 0 0 1:2
0 0 1 1:4
0 1 0 1:8
0 1 1 1:16
1 0 0 1:32
1 0 1 1:64
1 1 0 1:128
1 1 1 1:256

This specification is subject to change without prior notice. 20 04.10.2004 (V1.0)

 EM78P468N
OTP ROM

17. IOCA1 (High-Pulse Width Timer, Low-Pulse Width Timer Control Register)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
LPWTS LPWTP2 LPWTP1 LPWTP0 HPWTS HPWTP2 HPWTP1 HPWTP0

Bit 7(LPWTS): low-pulse width timer clock source select 0/1 -> Fs/ Fm*
(*Fs: sub-oscillator clock, Fm: main-oscillator clock)

Bit 6~4 (LPWTP2~0): low-pulse width timer prescaler select bits

LPWTP2 LPWTP1 LPWTP0 Low--pulse width timer scale
0 0 0 1:2
0 0 1 1:4
0 1 0 1:8
0 1 1 1:16
1 0 0 1:32
1 0 1 1:64
1 1 0 1:128
1 1 1 1:256

Bit 3(HPWTS): high-pulse width timer clock source select 0/1 -> Fs/ Fm*
(*Fs: sub-oscillator clock, Fm: main-oscillator clock)

Bit 2~0(HPWTP2~0): high-pulse width timer prescaler select bits

HPWTP2 HPWTP1 HPWTP0 High-pulse width timer scale
0 0 0 1:2
0 0 1 1:4
0 1 0 1:8
0 1 1 1:16
1 0 0 1:32
1 0 1 1:64
1 1 0 1:128
1 1 1 1:256

18. IOCB1 (PORT 6 Pull High Control Register)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PH67 PH66 PH65 PH64 PH63 PH62 PH61 PH60

Bit 7 ~ Bit 0: The enable bits of Port 6 pull high function.

0: disable internal pull-high resistor function
1: enable internal pull-high resistor function

19. IOCC1 (PORT 6 Open Drain Control Register)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
OP67 OP66 OP65 OP64 OP63 OP62 OP61 OP60
Bit 7 ~ Bit 0: The enable bits of Port 6 open drain function.
0: disable open drain function
1: enable open drain function

This specification is subject to change without prior notice. 21 04.10.2004 (V1.0)

 EM78P468N
OTP ROM

20. IOCD1 (PORT 8 Pull High Control Register)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PH87 PH86 PH85 PH84 PH83 PH82 PH81 PH80

Bit 7 ~ Bit 0: The enable bits of Port 8 pull-high function.

0: disable internal pull-high resistor function
1: enable pull-high resistor function

21. IOCE1 (PORT 6 Pull-Down Control Register)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PL67 PL66 PL65 PL64 PL63 PL62 PL61 PL60

Bit 7 ~ Bit 0: The enable bits of port 6 pull low function.

0: disable internal pull-down resistor function
1: enable internal pull-down resistor function

22. IOCF1 (Interrupt Mask register)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
-- -- -- -- -- -- -- LVDE
Bit 7~1: Not used
Bit 0: interrupt enable bit for low voltage detector function.
0: disable interrupt
1: enable interrupt
IOCF1 register is readable and writable.

4.3 TCC and WDT Pre-scaler

Two 8-bit counters are available as pre-scalers for the TCC (Time Clock Counter) and WDT (Watch
Dog Timer). The TCCP2~TCCP0 bits of the IOC71 register are used to determine the ratio of the
TCC pre-scaler. Likewise, the WDTP2~WDTP0 bits of the IOC81 register are used to determine the
WDT pre-scaler. The TCC pre-scaler (TCCP2~TCCP0) is cleared by the instructions each time they
are written into TCC, while the WDT pre-scaler is cleared by the “WDTC” and “SLEP” instructions.
Fig.7 depicts the circuit diagram of TCC and WDT.

R1 (TCC) is an 8-bit timer/counter. The clock source of TCC can be selected by internal instruction
clock or external signal input (edge selectable from the TCC control register). If TCC signal source is
from internal instruction clock, TCC will increase by 1 at every instruction cycle (without pre-scaler).
If TCC signal source is from external clock input, TCC will increase by 1 at every falling edge or
rising edge of the TCC pin.

This specification is subject to change without prior notice. 22 04.10.2004 (V1.0)

 EM78P468N
OTP ROM

The watchdog timer is a free running on-chip RC oscillator. The WDT will keep on running even after
the oscillator driver has been turned off. During Normal mode, Green mode, or Idle mode operation,
a WDT time-out (if enabled) will cause the device to reset. The WDT can be enabled or disabled at
any time during the Normal mode and Green mode by software programming. Refer to WDTE bit of
IOC81 register. With no pre-scaler, the WDT time-out period is equal to (prescaler*256/ Fs)

Data Bus

Instruction Clock TCC (R1)

TCC
MUX Prescaler 8 to 1 MUX
Pin

PSRE TCCP2~0
TCC overflow interrupt
(IOC71)(IOC71)
TE (IOC71)

TS (IOC71)

Fig. 7(a) Block Diagram of TCC

WDT 8 bit counter

Fs
WDTE (IOC81) 8 to 1 MUX Prescaler
(Sub oscillator)

WDTP2~0
WDT Time out
(IOC81)
Fig. 7(b) Block Diagram of WDT

This specification is subject to change without prior notice. 23 04.10.2004 (V1.0)

 EM78P468N
OTP ROM

4.4 I/O Ports

The I/O registers, (Port 5, Port 6, Port 7, and Port 8), are bi-directional tri-state I/O ports. Port 6 and
Port 8 are pulled-high internally by software; Port 6 is also pulled-low internally by software.
Furthermore, Port 6 has its open-drain output also through software. Port 6 and Port 8 features an
input status changed interrupt (or wake-up) function and is pulled-high by software. Each I/O pin can
be defined as "input" or "output" pin by the I/O control register (IOC5 ~ IOC8). The I/O registers and
I/O control registers are both readable and writable. The I/O interface circuits are shown in Fig. 8

NOTE: Open-drain, pull high, and pull down are not shown in the figure.

Fig. 8 The Circuit of I/O Port and I/O Control Register for Port 5, Port 6, Port 7and Port 8

4.5 RESET and Wake-up

A RESET can be activated by
Power on reset
WDT timeout. (if enabled)
/RESET pin pull low
Note: The power on reset circuit is always enabled. It will reset CPU at about 1.9V and consumed
about 0.5uA.
Once RESET occurs, the following functions are performed
The oscillator is running, or will be started.
The Program Counter (R2) is set to all "0".
All I/O port pins are configured as input mode (high-impedance state).
The TCC/Watchdog timer and pre-scaler are cleared.
When power on, the Bit 6 of R3 and the upper 2 bits of R4 are cleared.
Bits of the IOC71 register are set to all "1" except for Bit 6 (INT flag).
For other registers, see Table 2 below.

This specification is subject to change without prior notice. 24 04.10.2004 (V1.0)

 EM78P468N
OTP ROM

Table 2 Summary of the Initialized Values for Registers

Address Name Reset Type Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit Name IOC57 IOC56 IOC55 IOC54 P8HS P8LS P7HS P7LS
Power-On 1 1 1 1 0 0 0 0
N/A IOC50 /RESET and WDT 1 1 1 1 0 0 0 0
Wake-Up from Pin
P P P P P P P P
Change
Bit Name IOC67 IOC66 IOC65 IOC64 IOC63 IOC62 IOC61 IOC60
Power-On 1 1 1 1 1 1 1 1
N/A IOC60 /RESET and WDT 1 1 1 1 1 1 1 1
Wake-Up from Pin
P P P P P P P P
Change
Bit Name IOC77 IOC76 IOC75 IOC74 IOC73 IOC72 IOC71 IOC70
Power-On 1 1 1 1 1 1 1 1
N/A IOC70 /RESET and WDT 1 1 1 1 1 1 1 1
Wake-Up from Pin
P P P P P P P P
Change
Bit Name IOC87 IOC86 IOC85 IOC84 IOC83 IOC82 IOC81 IOC80
Power-On 1 1 1 1 1 1 1 1
N/A IOC80 /RESET and WDT 1 1 1 1 1 1 1 1
Wake-Up from Pin
P P P P P P P P
Change
Bit Name X RAM_A6 RAM_A5 RAM_A4 RAM_A3 RAM_A2 RAM_A1 RAM_A0
Power-On 0 0 0 0 0 0 0 0
N/A IOC90 /RESET and WDT 0 0 0 0 0 0 0 0
Wake-Up from Pin
P P P P P P P P
Change
Bit Name RAM_D7 RAM_D6 RAM_D5 RAM_D4 RAM_D3 RAM_D2 RAM_D1 RAM_D0
Power-On 0 0 0 0 0 0 0 0
N/A IOCA0 /RESET and WDT 0 0 0 0 0 0 0 0
Wake-Up from Pin
P P P P P P P P
Change
Bit Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Power-On 0 0 0 0 0 0 0 0
N/A IOCB0 /RESET and WDT 0 0 0 0 0 0 0 0
Wake-Up from Pin
P P P P P P P P
Change
Bit Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Power-On 0 0 0 0 0 0 0 0
N/A IOCC0 /RESET and WDT 0 0 0 0 0 0 0 0
Wake-Up from Pin
P P P P P P P P
Change
Bit Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Power-On 0 0 0 0 0 0 0 0
N/A IOCD0 /RESET and WDT 0 0 0 0 0 0 0 0
Wake-Up from Pin
P P P P P P P P
Change
Bit Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Power-On 0 0 0 0 0 0 0 0
N/A IOCE0 /RESET and WDT 0 0 0 0 0 0 0 0
Wake-Up from Pin
P P P P P P P P
Change
Bit Name ICIE LPWTE HPWTE CNT2E CNT1E INT1E INT0E TCIE
Power-On 0 0 0 0 0 0 0 0
N/A IOCF0 /RESET and WDT 0 0 0 0 0 0 0 0
Wake-Up from Pin
P P P P P P P P
Change
Bit Name IROCS X X X /WUE8H /WUE8L /WUE6H /WUE6L
Power-On 0 U U U 0 0 0 0
N/A IOC61 /RESET and WDT 0 U U U 0 0 0 0
Wake-Up from Pin
P U U U P P P P
Change

This specification is subject to change without prior notice. 25 04.10.2004 (V1.0)

 EM78P468N
OTP ROM

Address Name Reset Type Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit Name INT_EDGE INT TS TE PSRE TCCP2 TCCP1 TCCP0
Power-On 1 0 1 1 1 1 1 1
N/A IOC71 /RESET and WDT 1 0 1 1 1 1 1 1
Wake-Up from Pin
P P P P P P P P
Change
Bit Name X X X X WDTE WDTP2 WDTP1 WDTP0
Power-On U U U U 0 1 1 1
N/A IOC81 /RESET and WDT U U U U 0 1 1 1
Wake-Up from Pin
U U U U P P P P
Change
Bit Name CNT2S CNT2P2 CNT2P1 CNT2P0 CNT1S CNT1P2 CNT1P1 CNT1P0
Power-On 0 0 0 0 0 0 0 0
N/A IOC91 /RESET and WDT 0 0 0 0 0 0 0 0
Wake-Up from Pin
P P P P P P P P
Change
Bit Name LPWTS LPWTP2 LPWTP1 LPWTP0 HPWTS HPWTP2 HPWTP1 HPWTP0
Power-On 0 0 0 0 0 0 0 0
N/A IOCA1 /RESET and WDT 0 0 0 0 0 0 0 0
Wake-Up from Pin
P P P P P P P P
Change
Bit Name PH67 PH66 PH65 PH64 PH63 PH62 PH61 PH60
Power-On 0 0 0 0 0 0 0 0
N/A IOCB1 /RESET and WDT 0 0 0 0 0 0 0 0
Wake-Up from Pin
P P P P P P P P
Change
Bit Name OP67 OP66 OP65 OP64 OP63 OP62 OP61 OP60
Power-On 0 0 0 0 0 0 0 0
N/A IOCC1 /RESET and WDT 0 0 0 0 0 0 0 0
Wake-Up from Pin
P P P P P P P P
Change
Bit Name PH87 PH86 PH85 PH84 PH83 PH82 PH81 PH80
Power-On 0 0 0 0 0 0 0 0
N/A IOCD1 /RESET and WDT 0 0 0 0 0 0 0 0
Wake-Up from Pin
P P P P P P P P
Change
Bit Name PL67 PL66 PL65 PL64 PL63 PL62 PL61 PL60
Power-On 0 0 0 0 0 0 0 0
N/A IOCE1 /RESET and WDT 0 0 0 0 0 0 0 0
Wake-Up from Pin
P P P P P P P P
Change
Bit Name X X X X X X X LVDE
Power-On U U U U U U U 0
N/A IOCF1 /RESET and WDT U U U U U U U 0
Wake-Up from Pin
U U U U U U U P
Change
Bit Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Power-On U U U U U U U U
0x00 R0(IAR) /RESET and WDT P P P P P P P P
Wake-Up from Pin
P P P P P P P P
Change
Bit Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Power-On 0 0 0 0 0 0 0 0
0x01 R1(TCC) /RESET and WDT 0 0 0 0 0 0 0 0
Wake-Up from Pin
P P P P P P P P
Change
Bit Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Power-On 0 0 0 0 0 0 0 0
0x02 R2(PC) /RESET and WDT 0 0 0 0 0 0 0 0
Wake-Up from Pin
Jump to address 0x0018 or continue to execute next instruction
Change

This specification is subject to change without prior notice. 26 04.10.2004 (V1.0)

 EM78P468N
OTP ROM

Address Name Reset Type Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit Name X PS1 PS0 T P Z DC C
Power-On U 0 0 1 1 U U U
0x03 R3(SR) /RESET and WDT U 0 0 t t P P P
Wake-Up from Pin
U P P t t P P P
Change
Bit Name Bank1 Bank0 -- -- -- -- -- --
Power-On 0 0 U U U U U U
0x04 R4(RSR) /RESET and WDT 0 0 P P P P P P
Wake-Up from Pin
P P P P P P P P
Change
Bit Name R57 R56 R55 R54 X X X IOCPAGE
Power-On 1 1 1 1 U U U 0
0x05 R5 /RESET and WDT 1 1 1 1 U U U 0
Wake-Up from Pin
P P P P U U U P
Change
Bit Name R67 R66 R65 R64 R63 R62 R61 R60
Power-On 1 1 1 1 1 1 1 1
0x06 R6 /RESET and WDT 1 1 1 1 1 1 1 1
Wake-Up from Pin
P P P P P P P P
Change
Bit Name R77 R76 R75 R74 R73 R62 R71 R70
Power-On 1 1 1 1 1 1 1 1
0x7 R7 /RESET and WDT 1 1 1 1 1 1 1 1
Wake-Up from Pin
P P P P P P P P
Change
Bit Name R87 R86 R85 R84 R83 R82 R81 R80
Power-On 1 1 1 1 1 1 1 1
0x8 R8 /RESET and WDT 1 1 1 1 1 1 1 1
Wake-Up from Pin
P P P P P P P P
Change
Bit Name BS DS1 DS0 LCDEN X LCDTYPE LCDF1 LCDF0
Power-On 1 1 0 0 U 0 0 0
0x9 R9 /RESET and WDT 1 1 0 0 U 0 0 0
Wake-Up from Pin
P P P P U P P P
Change
Bit Name X X X LCD_A4 LCD_A3 LCD_A2 LCD_A1 LCD_A0
Power-On 0 0 0 0 0 0 0 0
0xA RA /RESET and WDT 0 0 0 0 0 0 0 0
Wake-Up from Pin
P P P P P P P P
Change
Bit Name X X X X LCD_D 3 LCD_D 2 LCD_D 1 LCD_D 0
Power-On U U U U 0 0 0 0
0xB RB /RESET and WDT U U U U 0 0 0 0
Wake-Up from Pin
U U U U P P P P
Change
Bit Name LVDEN /LV LVDF LVD LPWTEN HPWTEN CNT2EN CNT1EN
Power-On 0 1 0 0 0 0 0 0
0xC RC /RESET and WDT 0 1 0 0 0 0 0 0
Wake-Up from Pin
P P 0 P P P P P
Change
Bit Name X CLK2 CLK1 CLK0 IDLE BF1 BF0 CPUS
Power-On U 0 0 0 1 0 0 *1
0xD RD /RESET and WDT U 0 0 0 1 0 0 *1
Wake-Up from Pin
U P P P P P P P
Change
Bit Name IRE HF LGP X IROUTE TCCE EINT1 EINT0
Power-On 0 0 0 U 0 0 0 0
0xE RE /RESET and WDT 0 0 0 U 0 0 0 0
Wake-Up from Pin
P P P U P P P P
Change

This specification is subject to change without prior notice. 27 04.10.2004 (V1.0)

 EM78P468N
OTP ROM

Address Name Reset Type Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit Name ICIF LPWTF HPWTF CNT2F CNT1F INT1F INT0F TCIF
RF Power-On 0 0 0 0 0 0 0 0
0xF /RESET and WDT 0 0 0 0 0 0 0 0
(ISR)
Wake-Up from Pin
N P P P P P P P
Change
Bit Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Power-On U U U U U U U U
0x10~0x3F R10~R3F /RESET and WDT U U U U U U U U
Wake-Up from Pin
P P P P P P P P
Change
X: not used. U: unknown or don’t care. P: previous value before reset. –: Not defined
t : check R3 register explain. N: Monitors interrupt operation status; 1=running; P=not running
Note 1: This bit is equal to code option HLFS bit data

The controller can be awakened from sleep mode and idle mode. The wake-up signals are listed as follows:
Wakeup signal Sleep mode Idle mode Green mode Normal mode
*2
TCC time out Wake-up
X Interrupt Interrupt
IOCF bit0=1 + interrupt
+ next instruction
Wake-up Wake-up
INT0 pin
+ interrupt + interrupt Interrupt Interrupt
IOCF bit1=1
+ next instruction + next instruction
Wake-up Wake-up
INT1 pin
+ interrupt + interrupt Interrupt Interrupt
IOCF bit2=1
+ next instruction + next instruction
Wake-up
Counter 1
X + interrupt Interrupt Interrupt
IOCF bit3=1
+ next instruction
Wake-up
Counter 2
X + interrupt Interrupt Interrupt
IOCF bit4=1
+ next instruction
Wake-up
High-pulse timer
X + interrupt Interrupt Interrupt
IOCF bit5=1
+ next instruction
Wake-up
Low-pulse timer
X + interrupt Interrupt Interrupt
IOCF bit6=1
+ next instruction
IOCF bit7=0 IOCF bit7=0
Wake-up Wake-up
+ next instruction + next instruction
Port6, Port 8
(input status IOCF bit7=1+ENI IOCF bit7=1+ENI X X
change wake-up) instruction instruction
Wake-up Wake-up
+ interrupt + interrupt
+ next instruction + next instruction
WDT time out X RESET RESET RESET
Note 2: Only external TCC pin can Wake-up from idle mode.

This specification is subject to change without prior notice. 28 04.10.2004 (V1.0)

 EM78P468N
OTP ROM

4.6 Oscillator
4.6.1. Oscillator Modes
The EM78P468N can operate in the three different oscillator modes from main oscillator (R-OSCI,
OSCO), such as RC oscillator with external resistor and Internal capacitor mode (IC); crystal
oscillator mode; and PLL operation mode. User can select one of them by programming FMMD1 and
FMMD0 in the CODE options register. The sub-oscillator can be operated in crystal mode and ERIC
mode. Table3 below shows how these three modes are defined.

Table 3 Oscillator Modes as defined by FSMD, FMMD1, FMMD0.

FSMD FMMD1 FMMD0 Main clock Sub-clock
0 0 0 RC type (ERIC) RC type (ERIC)
0 0 1 Crystal type RC type (ERIC)
0 1 X PLL type RC type (ERIC)
1 0 0 RC type (ERIC) Crystal type
1 0 1 Crystal type Crystal type
1 1 X PLL type Crystal type

Table 4 Summary of maximum operating speeds

Conditions VDD Fxt max.(MHz)
2.3 4
Two clocks 3.0 8
5.0 10

4.6.2. Crystal Oscillator/Ceramic Resonators (XTAL)

EM78P468N can be driven by an external clock signal through the R-OSCI pin as shown in Fig.9
below.

In most applications, the R-OSCI pin and the OSCO pin can be connected with a crystal or ceramic
resonator to generate oscillation. Fig. 10 depicts such circuit. Table 5 provides the recommended
values of C1 and C2. Since each resonator has its own attribute, user should refer to its specification
for appropriate values of C1 and C2. RS, a serial resistor, may be necessary for AT strip cut crystal
or low frequency mode.

R-OSCI

EM78P468N

OSCO

Fig.9 Circuit for External Clock Input

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R-OSCI Xin

EM78P468N EM78P468N

OSCO Xout

Fig. 10 Circuit for Crystal/Resonator

Table 5 Capacitor Selection Guide for Crystal Oscillator or Ceramic Resonators

Oscillator
Oscillator Type Frequency C1 (pF) C2(pF)
source
455 kHz 100~150 100~150
Ceramic Resonators 2.0 MHz 20~40 20~40
4.0 MHz 10~30 10~30
Main oscillator 455KHz 20~40 20~150
1.0MHz 15~30 15~30
Crystal Oscillator
2.0MHz 15 15
4.0MHz 15 15
Sub-oscillator Crystal Oscillator 32.768kHz 25 25

4.6.3. RC Oscillator Mode with Internal Capacitor

If both precision and cost are taken into consideration, EM78P468N also offers a special
oscillation mode, which is equipped with an internal capacitor and an external resistor connected
to VDD. The internal capacitor functions as temperature compensator. In order to obtain more
accurate frequency, a precise resistor is recommended.

R-OSCI
or Xin
EM78P468N

Fig. 11 Circuit for Internal C Oscillator Mode

Table 6 RC Oscillator Frequencies
Pin Rext Average Fosc 5V, 25°C Average Fosc 3V, 25°C
51k 2.2221 MHz 2.1972 MHz
R-OSCI 100k 1.1345 MHz 1.1203 MHz
300k 381.36KHz 374.77 KHz
Xin 2.2M 32.768KHz 32.768KHz
Note: Measured from QFP packages with frequency drift of about ±30%.
Values provided are for design reference only

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4.7 Power-on Considerations

Any microcontroller (as with i EM78P468N ) s not warranted to start operating properly before the
power supply stabilizes in steady state. The EM78P468N is equipped with Power On Reset (POR)
with detection level range of 1.9V to 2.1V. The circuitry eliminates the extra external reset circuit but
will work well only if the VDD rises quickly enough (50 ms or less). However, under critical
applications, extra devices are still required to assist in solving power-on problems.

4.7.1. External Power-on Reset Circuit

This circuit implements an external RC to produce a reset pulse (see Fig.12). The pulse width (time
constant) should be kept long enough to allow VDD to reach minimum operation voltage. This circuit
is used when the power supply rise time is slow. Because the current leakage from the /RESET pin
is about ±5µA, it is recommended that R should not be great than 40K. In this way, the voltage at Pin
/RESET is held below 0.2V. The diode (D) acts as a short circuit at power-down. The capacitor, C, is
discharged rapidly and fully. Rin, the current-limited resistor, prevents high current discharge or ESD
(electrostatic discharge) from flowing into Pin /RESET.

Fig. 12 External Power on Reset Circuit

7.7.2. Residue-Voltage Protection

When battery is replaced, device power (VDD) is disconnected but residue-voltage remains. The
residue-voltage may trips below minimum VDD, but above zero. This condition may cause poor
power on reset. Fig.13 and Fig.14 show how to build a residue-voltage protection circuit

Fig. 13 Circuit 1 for the Residue Voltage Protection

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Fig. 14 Circuit 2 for the Residue Voltage Protection

4.8 Interrupt
The EM78P468N has nine interrupt sources as listed below:
TCC overflow interrupt.
External interrupt P5.4/INTO pin
External interrupt P5.5/INT1 pin
Counter 1 underflow interrupt
Counter 2 underflow interrupt
High-pulse width timer underflow interrupt
Low-pulse width timer underflow interrupt
Port 6, Port 8 input status change wake-up
Low voltage detector

This IC has internal interrupts which are falling edge triggered or as follows:
TCC timer overflow interrupt,
Four 8-bits down counter/timer underflow interrupt
VDD level down to less than LVD setting level

If these interrupt sources change signal from high to low, the RF register will generate “1” flag to
corresponding register if the IOCF0 or IOCF1 register is enabled.

RF is the interrupt status register. It records the interrupt request in flag bit. IOCF is the interrupt
mask register. Global interrupt is enabled by ENI instruction and disabled by DISI instruction. When
one of the interrupts (when enabled) is generated, it will cause the next instruction to be fetch from
address 0003H~001BH according to interrupt source.

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With EM78P468N, each individual interrupt source has its own interrupt vector as depicted in Table 3.
Before the interrupt subroutine is executed, the contents of ACC and the R3 register are initially
saved by hardware. After the interrupt service routine is completed, ACC and R3 are restored. The
existing interrupt service routine does not allow other interrupt service routine to be executed. So if
other interrupts occur while the existing interrupt service routine is being executed, the hardware will
save the later interrupts. Only after the existing interrupt service routine is completed that the next
interrupt service routine is executed.

Fig. 15. Interrupt Backup Diagram

Table 3 Interrupt Vector
Interrupt Vector Interrupt Status
0003H TCC overflow interrupt.
0006H External interrupt P5.4/INT0 pin
0009H External interrupt P5.5/INT1 pin
000CH Counter 1 underflow interrupt
000FH Counter 2 underflow interrupt
0012H High-pulse width timer underflow interrupt
0015H Low-pulse width timer underflow interrupt
0018H Port 6, Port 8 input status change wake-up
001BH Low voltage detector

4.9 LCD Driver

The EM78P468N can drive LCD of up to 32 segments and 4 commons that can drive a total of 4*32
dots. LCD block is made up of LCD driver, display RAM, segment output pins, common output pins,
and LCD operating power supply pins. This circuit works on normal mode, green mode, and idle
mode. The LCD duty, bias, the number of segment, the number of common, and frame frequency
are determined by the LCD controller register.

The basic structure contains a timing control that uses a subsystem clock to generate the proper
timing for different duty and display accesses. The R9 register is a command register for LCD driver
which includes LCD enable/disable, bias (1/2 and 1/3), duty (1/2, 1/3, 1/4), and LCD frame frequency
control. The register RA is an LCD contrast and LCD RAM address control register. The register RB
is an LCD RAM data buffer. LCD booster circuit can change operation frequency to improve VLCD2
and VLCD3 drive capability. The control register is explained as follows.

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R9 (LCD Control Register)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
BS DS1 DS0 LCDEN -- LCDTYPE LCDF1 LCDF0

Bit 7 (BS): LCD bias select bit, 0/1=>(1/2 bias) / (1/3 bias)

Bit 6, 5 (DS1, 0): LCD duty select

DS1 DS0 LCD Duty
0 0 1/2 duty
0 1 1/3 duty
1 X 1/4 duty

Bit 4 (LCDEN): LCD enable bit: 0/1 -> LCD circuit disable/enable
When LCD function is disabled, all common/segment output is set to ground (GND) level
Bit 3: Not used
Bit 2 (LCDTYPE): LCD drive waveform type select bit
0: “A” type waveform
1: “B” type waveform

Bit 1, 0(LCDF1, 0): LCD clock pre-scaler ratio control bits

LCD frame frequency (Fs=32.768KHz)
LCDF1 LCDF0
1/2 duty 1/3 duty 1/4 duty
0 0 Fs/(256*2)=64.0 Fs/(172*3)=63.5 Fs/(128*4) =64.0
0 1 Fs/(280*2)=58.5 Fs/(188*3)=58.0 Fs/(140*4) =58.5
1 0 Fs/(304*2)=53.9 Fs/(204*3)=53.5 Fs/(152*4) =53.9
1 1 Fs/(232*2)=70.6 Fs/(156*3)=70.0 Fs/(116*4) =70.6
Fs: sub-oscillator frequency

RA (LCD Address)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0 0 0 LCD_A4 LCD_A3 LCD_A2 LCD_A1 LCD_A0

Bit 7 ~ 5: Not used, fixed to “0”

Bit 4~0 (LCDA4~0): LCD RAM address
RB (LCD Data Buffer)
RA
Bit 3 Bit 2 Bit 1 Bit 0 Segment
(LCD Address) Bit 7 Bit 6 Bit 5 Bit 4
(LCD_D3) (LCD_D2) (LCD_D1) (LCD_D0)
00H -- -- -- -- SEG0
01H -- -- -- -- SEG1
02H -- -- -- -- SEG2
| | |
-- -- -- -- SEG29
1EH -- -- -- -- SEG30
1FH -- -- -- -- SEG31
Common X X X X COM3 COM2 COM1 COM0

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RB (LCD Data Buffer)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
-- -- -- -- LCD_D 3 LCD_D 2 LCD_D 1 LCD_D 0

Bit 7 ~ 4: Not used

Bit 3~0 (LCD_D3~0): LCD RAM data transfer registers

RD (System Clock, Booster Frequency and PLL Frequency Control Register)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
-- CLK2 CLK1 CLK0 IDLE BF1 BF0 CPUS

Bit 2, 1 (BF1, 0): LCD booster frequency select bits

BF1 BF0 Booster frequency
0 0 Fs
0 1 Fs/4
1 0 Fs/8
1 1 Fs/16

The initial setting flowchart for LCD function

IC RESET occur

*Set Port 7 snd Port 8 for general I/O or LCD segment ( IOC50 )
*it must be set to output port when the pin of port 7 and the pin of port 8 for
LCD segemnt (IOC70 and IOC80 )

Set LCD Type, duty, bias, LCD frame frequency ( R9 )

Set LCD Booster Frequency ( RD)

Clear all LCD RAM (RA and RB )

Enable LCD function (R9 )

Use LCD address and LCD data buffer to implment user's applications.
(RA and RB )

END

Fig.16. The Initial Setting Flowchart for LCD Function

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The connecting of boosting circuits for LCD voltage is as below:

1/3 Bias

VDD(3V) VDD(4.5V)

VLCD2(2V) VLCD2(3V)

VA VA
VLCD3(1V) VLCD3(1.5V)

VB GND VB GND

1/2 Bias

VDD(3V) VDD(4.5V)

VLCD2(1.5V) VLCD2(2.2.5V)

VA VA
VLCD3(1.5V) VLCD3(2.25V)

VB GND VB GND

Fig. 17 The Connection of Charge Bump Circuit

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Fig. 18 LCD Waveform for 1/2 Bias, 1/2 Duty

Fig. 19 LCD Waveform for 1/2 Bias, 1/3 Duty

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Fig. 20 LCD Waveform for 1/3 Bias, 1/3 Duty

Fig. 21 LCD Waveform for 1/3 Bias, 1/4 Duty

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4.10 Infrared Remote Control Application / PWM Waveform Generate

This LSI can output infrared carrier in a friendly manner or in PWM standard waveform. The IR and
PWM waveform generated functions include an 8-bit down count timer/counter, high-pulse width
timer, low-pulse width timer, and IR control register. The IR system block diagram is show in Fig.21,
The IROUT pin waveform is determined by IR control register (RE), IOC90 (Counter 1, 2 control
register), IOCA0 (high-pulse width timer, low-pulse width timer control register), IOCC0 (Counter 2
preset), IOCD0 (high-pulse width timer preset register), and IOCE0 (low-pulse width timer preset
register). Details on Fcarrier, high-pulse time, and low pulse time are explained as follows:

If Counter 2 source clock is FT (this clock source can set by IOC91);

Fcarrier= FT/(2* [1+decimal counter 2 preset value (IOCC0)*prescaler])

If high-pulse width timer source clock is FT (this clock source can set by IOCA1);
High-pulse time= prescaler*[1+decimal high-pulse width timer value (IOCD0)]/ FT

If low-pulse width timer source clock is FT (this clock source can set by IOCA1);
Low-pulse time= prescaler*[1+decimal low-pulse width timer value (IOCE0)]/ FT

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Fs Fm Pre-scaler

Auto-reload buffer Auto-reload buffer

8
8

8 bit binary dow n counter 8 bit binary dow n counter

Pre-scaler
Pre-scaler (high-pulse w idth timer) (low -pulse w idth timer)

8 8

8 bit binary
down counter H/W Modulator
(counter 2)

8
HF LGP IRE
Auto-reload
IROUT pin
buffer

Fm: Internal instruction cycle clock; Fs: sub-oscillator frequency

Fig. 21 IR/PWM System Block Diagram

The IROUT output waveform is further explained in the following figures:

Fig. 22 LGP=0, HF=1, the IROUT waveform can modulate Fcarrier waveform when in low-pulse
width time.

Fig. 23 LGP=0, HF=0, the IROUT waveform cannot modulate Fcarrier waveform when in low-pulse
width time. So IROUT waveform is determined by high-pulse time and low-pulse time. This
mode can produce standard PWM waveform

Fig. 24 LGP=0, HF=1, the IROUT waveform can modulate Fcarrier waveform when in low-pulse
width time. When IRE goes from high to low, the output waveform of IROUT will keep on
transmitting till high-pulse width timer interrupt occurs.

Fig. 25 LGP=0, HF=0, the IROUT waveform can not modulate Fcarrier waveform when in low-pulse
width time. So IROUT waveform is determined by high-pulse time and low-pulse time. This
mode can produce standard PWM waveform. When IRE goes from high to low, the output
waveform of IROUT will keep on transmitting till high-pulse width timer interrupt occurs.

Fig.26 LGP=1, when this bit is set to high level, the high-pulse width timer is ignored. So IROUT
waveform output from low-pulse width timer is established.

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Fcarrier

low-pulse width high-pulse width low-pulse width high-pulse width

HF
start
IRE

IROUT

Fig. 22 LGP=0, IROUT Pin Output Waveform

Fcarrier

low-pulse width high-pulse width low-pulse width high-pulse width

HF
start
IRE

IROUT

Fig. 23 LGP=0, IROUT Pin Output Waveform

Fcarrier

low-pulse width high-pulse width low-pulse width high-pulse width

HF
start
IRE IR disable

IROUT
Always high-level

Fig. 24 LGP=0, IROUT Pin Output Waveform

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Fcarrier

low-pulse width high-pulse width low-pulse width high-pulse width

HF
start
IRE IR disable

IROUT
Always high-level

Fig. 25 LGP=0, IROUT Pin Output Waveform

Fcarrier

low-pulse width Low-pulse width low-pulse width high-pulse width

HF
start
IRE IR disable

IROUT
Always high-level

Fig. 26 LGP=1, IROUT Pin Output Waveform

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IR/PWM function enable flowchart

STRAT STRAT

SET P5.7 to OUTPUT state (IOC 50)

SET P5.7 to OUTPUT state (IOC 50)

SET P5.7 for IR/PW M Function

Output Pin (RE) SET P5.7 for IR/PWM Function
Output Pin (RE)

SET Counter 2 clock source and

prescaler (IOC91)
SET High pulse width timer, Low
pulse width timer source clock and
prescaler (IOCA1)
SET High pulse width tim er, Low
pulse width tim er source clock and
prescaler (IOCA1)
High pulse width timer (IOD0), Low
pulse width timer (IOCE0)preset
SET Counter 2 (IOC0), High pulse value
width tim er (IOD0), Low pulse width
tim er (IOCE0)preset value

Enable IR (RE)
HF="0", and IRE="1"
Enable IR (RE)
HF="1", and IRE="1"

Enable HPWT and LPWT Interrupt

Enable HPW T and LPW T Interrupt Set IOCF0 and ENI instruction
Set IOCF0 and ENI instruction

Enable high pulse width timer and

Enable counter 2, high pulse width
Low pulde width timer (RC)
tim er and Low pulde width tim er (RC)

END END

(a) IR application (b) PWM application

Fig. 27 IR/PWM Function Enable Flowchart

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OTP ROM

4.11 Code Options

The EM78P468N has one CODE option word that is not a part of the normal program memory. The
option bits cannot be accessed during normal program execution.
Code Option Register and Customer ID Register arrangement distribution:
Word1 of code options is for customer ID code application.
Word 1
Bit12~Bit 0

Word0 of Code Options is for IC function setting. The following are the settings for OTP IC
programming:
Word 0
Bit12~10 Bit9 Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
1 CYES HLFS ENWDTB FSMD FMMD1 FMMD0 HLP PR2 PR1 PR0

• Bit 12 ~ 10: Not used.

These bits are set to “1” all the time.

• Bit 9 (CYES): Cycle select for JMP and CALL instructions

0: only one instruction cycle (JMP or CALL) can be executed
1: two instructions cycles (JMP and CALL) can be executed

• Bit 8 (HLFS): main or sub-oscillator select

0: CPU is set to select sub-oscillator when reset occurred.
1: CPU is set to select main-oscillator when reset occurred.

• Bit 7(ENWDTB): Watchdog timer enable/disable bit.

0: Enable
1: Disable

• Bit 6 (FSMD): sub-oscillator type selection.

0: RC type (internal C)
1: XTAL type (Xin and Xout)

• Bit 5, 4 (FMMD1, 0): main Oscillator type selection.

FMMD1 FMMD0 Main Oscillator Type
0 0 RC type (external R, internal C)
0 1 XTAL type (R-OSCI, OSCO)
1 X PLL type

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• Bit 3 (HLP): Power consumption selection. If your system usually runs in green mode, it must be
set to low power consumption. Take note and help support the energy saving issue. We recommend
that low power consumption mode is selected.
0: Low power consumption mode
1: High power consumption mode

• Bit 2~0 (PR2~PR0): Protect Bit

PR2~PR0 are protect bits as explained below:
PR2 PR1 PR0 Protect
1 1 1 Disable
others Enable

4.12 Instruction Set

Each instruction in the instruction set is a 13-bit word divided into an OP code and one or more
operands. Normally, all instructions are executed within one single instruction cycle (one instruction
consists of 2 oscillator periods), unless the program counter is changed by instruction "MOV R2,A",
"ADD R2,A", or by instructions of arithmetic or logic operation on R2 (e.g. "SUB R2,A", "BS(C) R2,6",
"CLR R2", ⋅⋅⋅⋅). In this case, the execution takes two instruction cycles.

If for some reasons, the specification of the instruction cycle is not suitable for certain applications,
try modifying the instruction as follows:
Execute within two instruction cycles the "JMP", "CALL", "RET", "RETL", & "RETI" instructions, or
the conditional skip instructions ("JBS", "JBC", "JZ", "JZA", "DJZ", "DJZA") which were tested to be
true. Also execute within two instruction cycles the instructions that are written to the program
counter.

Additionally, the instruction set offers the following features:

(1) Every bit of any register can be set, cleared, or tested directly.
(2) The I/O register can be regarded as general register. That is, the same instruction can operate
on I/O register.
The symbol "R" represents a register designator that specifies which one of the registers (including
operational registers and general purpose registers) is to be utilized by the instruction. "b" represents
a bit field designator that selects the value for the bit that is located in the register "R", and affects
operation. "k" represents an 8 or 10-bit constant or literal value.

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INSTRUCTION STATUS
HEX MNEMONIC OPERATION
BINARY AFFECTED
0 0000 0000 0000 0000 NOP No Operation None
0 0000 0000 0001 0001 DAA Decimal Adjust A C
0 0000 0000 0011 0003 SLEP 0 → WDT, Stop oscillator T, P
0 0000 0000 0100 0004 WDTC 0 → WDT T, P
0 0000 0000 rrrr 000r IOW R A → IOCR None <Note1>
0 0000 0001 0000 0010 ENI Enable Interrupt None
0 0000 0001 0001 0011 DISI Disable Interrupt None
0 0000 0001 0010 0012 RET [Top of Stack] → PC None
[Top of Stack] → PC,
0 0000 0001 0011 0013 RETI None
Enable Interrupt
0 0000 0001 rrrr 001r IOR R IOCR → A None <Note1>
0 0000 01rr rrrr 00rr MOV R, A A→R None
0 0000 1000 0000 0080 CLRA 0→A Z
0 0000 11rr rrrr 00rr CLR R 0→R Z
0 0001 00rr rrrr 01rr SUB A, R R-A → A Z, C, DC
0 0001 01rr rrrr 01rr SUB R, A R-A → R Z, C, DC
0 0001 10rr rrrr 01rr DECA R R-1 → A Z
0 0001 11rr rrrr 01rr DEC R R-1 → R Z
0 0010 00rr rrrr 02rr OR A, R A∨R→A Z
0 0010 01rr rrrr 02rr OR R, A A∨R→R Z
0 0010 10rr rrrr 02rr AND A, R A&R→A Z
0 0010 11rr rrrr 02rr AND R, A A&R→R Z
0 0011 00rr rrrr 03rr XOR A, R A⊕R→A Z
0 0011 01rr rrrr 03rr XOR R, A A⊕R→R Z
0 0011 10rr rrrr 03rr ADD A, R A+R→A Z, C, DC
0 0011 11rr rrrr 03rr ADD R, A A+R→R Z, C, DC
0 0100 00rr rrrr 04rr MOV A, R R→A Z
0 0100 01rr rrrr 04rr MOV R, R R→R Z
0 0100 10rr rrrr 04rr COMA R /R → A Z
0 0100 11rr rrrr 04rr COM R /R → R Z
0 0101 00rr rrrr 05rr INCA R R+1 → A Z
0 0101 01rr rrrr 05rr INC R R+1 → R Z
0 0101 10rr rrrr 05rr DJZA R R-1 → A, skip if zero None
0 0101 11rr rrrr 05rr DJZ R R-1 → R, skip if zero None
R(n) → A(n-1),
0 0110 00rr rrrr 06rr RRCA R C
R(0) → C, C → A(7)
R(n) → R(n-1),
0 0110 01rr rrrr 06rr RRC R C
R(0) → C, C → R(7)
R(n) → A(n+1),
0 0110 10rr rrrr 06rr RLCA R C
R(7) → C, C → A(0)
R(n) → R(n+1),
0 0110 11rr rrrr 06rr RLC R C
R(7) → C, C → R(0)
R(0-3) → A(4-7),
0 0111 00rr rrrr 07rr SWAPA R None
R(4-7) → A(0-3)
0 0111 01rr rrrr 07rr SWAP R R(0-3) ↔ R(4-7) None
0 0111 10rr rrrr 07rr JZA R R+1 → A, skip if zero None
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INSTRUCTION STATUS
HEX MNEMONIC OPERATION
BINARY AFFECTED
0 0111 11rr rrrr 07rr JZ R R+1 → R, skip if zero None
0 100b bbrr rrrr 0xxx BC R, b 0 → R(b) None <Note2>
0 101b bbrr rrrr 0xxx BS R, b 1 → R(b) None <Note3>
0 110b bbrr rrrr 0xxx JBC R, b if R(b)=0, skip None
0 111b bbrr rrrr 0xxx JBS R, b if R(b)=1, skip None
PC+1 → [SP],
1 00kk kkkk kkkk 1kkk CALL k None
(Page, k) → PC
1 01kk kkkk kkkk 1kkk JMP k (Page, k) → PC None
1 1000 kkkk kkkk 18kk MOV A, k k→A None
1 1001 kkkk kkkk 19kk OR A, k A∨k→A Z
1 1010 kkkk kkkk 1Akk AND A, k A&k→A Z
1 1011 kkkk kkkk 1Bkk XOR A, k A⊕k→A Z
1 1100 kkkk kkkk 1Ckk RETL k k → A, [Top of Stack] → PC None
1 1101 kkkk kkkk 1Dkk SUB A, k k-A → A Z, C, DC
1 1110 1000 00kk 1E8k PAGE k k->R5(1:0) None
1 1110 1001 00kk 1E9K BANK k k->R4(7:6) None
1 1111 kkkk kkkk 1Fkk ADD A, k k+A → A Z, C, DC
<Note1> This instruction is applicable to IOC5 ~ IOCF
<Note2> This instruction is not recommended for R3F operation.
<Note3> This instruction cannot operate under R3F.

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4.13 Timing Diagram

AC Test Input/Output Waveform

2.4
2.0 2.0
TEST POINTS
0.8 0.8
0.4

AC Testing : Input is driven at 2.4V for logic "1",and 0.4V for logic "0".Tim ing m easurem ents are
m ade at 2.0V for logic "1",and 0.8V for logic "0".

RESET Timing (CLK="0")

Instruction 1
NOP
Executed

CLK

/RESET

Tdrh

TCC Input Timing (CLKS="0")

Tins

CLK

TCC

Ttcc

*n=0 2 4 6

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OTP ROM

5. ABSOLUTE MAXIMUM RATINGS

Rating
Items Symbol Condition Unit
Min. Max.
Supply voltage VDD GND-0.3 +7.0 V
Input voltage VI Port5, Port6, Port7, Port8 GND-0.3 VDD+0.3 V
Output voltage VO Port5, Port6, Port7, Port8 GND-0.3 VDD+0.3 V
Operation temperature TOPR -40 85
Storage temperature TSTG -65 150
Power dissipation PD 500 mW
Operating Frequency 32.768K 10M Hz

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OTP ROM

6. ELECTRICAL CHARACTERISTIC

6.1 DC ELECTRICAL CHARACTERISTICS

(Ta= 25 °C, VDD= 5.0V, GND= 0V)
Symbol Parameter Condition Min. Typ. Max. Unit
FXT XTAL: VDD to 5V Two cycle with two clocks 32.768K 8M 10M Hz
Fs Sub-oscillator Two cycle with two clocks 32.768 KHz
External R, internal C for
R: 300KΩ, internal capacitance 270 384 500 KHz
sub-oscillator
ERIC
External R, internal C for
R: 2.2MΩ, internal capacitance 29.5 32.768 42.6 KHz
sub-oscillator
Input Leakage Current for input
IIL VIN = VDD, GND -1 0 1 µA
pins
VIH1 Input High Voltage Ports 5, 6, 7, 8 2.0 V
VIL1 Input Low Voltage Ports 5, 6, 7, 8 0.8 V
Input High Threshold Voltage
VIHT1 /RESET 2.0 V
(Schmitt trigger)
Input Low Threshold Voltage
VILT1 /RESET 0.8 V
(Schmitt trigger)
Input High Threshold Voltage
VIHT2 TCC, INT0, INT1 2.0 V
(Schmitt trigger)
Input Low Threshold Voltage
VILT2 TCC, INT0, INT1 0.8 V
(Schmitt trigger)
The voltage of Vdet is determined by RC
Vdet Low voltage detector voltage Vdet-0.2 Vdet Vdet+0.2 V
control register
Output High Voltage
IOH1 VOH = 2.4V -10 mA
(Ports 5, 6, 7, 8)
Output Low Voltage
IOL1 VOL = 0.4V 10 mA
(Ports 5, 6, 7, 8)
Output high voltage
IOH1 VOH = 2.4V -20 mA
(IROUT pin)
Output Low Voltage
IOL2 VOL = 0.4V 20 mA
(IR OUT pin)
IPH Pull-high current Pull-high active, input pin at GND -55 -75 -95 µA
IPL Pull-low current Pull-low active, input pin at VDD 55 75 5 µA
All input and I/O pins at VDD, output pin
ISB Sleep mode current 0.3 1 µA
floating, WDT disabled
/RESET= 'High', CPU OFF, sub-oscillator
ICC1 Idle mode current clock (32.768KHz) ON, output pin floating, 12 16 µA
LCD enable, no load
/RESET= 'High', CPU ON, used
ICC2 Green mode current sub-oscillator clock (32.768KHz), output pin 22 30 µA
floating, WDT enabled, LCD enable
/RESET= 'High', Fosc=4MHz (Crystal type,
ICC3 Normal mode 2.2 2.5 mA
CLKS="0"), output pin floating
/RESET= 'High', Fosc=10MHz (Crystal type,
ICC4 Normal mode 3.1 3.5 mA
CLKS="0"), output pin floating

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(Ta= 25 °C, VDD= 3.0V, GND= 0V)

Symbol Parameter Condition Min. Typ. Max. Unit
FXT XTAL: VDD to 5V Two cycle with two clocks 32.768K 8M 10M Hz
Fs Sub-oscillator Two cycle with two clocks 32.768 KHz
External R, internal C for
ERIC R: 300KΩ, internal capacitance 270 384 500 KHz
sub-oscillator
External R, internal C for
R: 2.2MΩ, internal capacitance 29.5 32.768 42.6 KHz
sub-oscillator
Input Leakage Current for input
IIL VIN = VDD, GND -1 0 1 µA
pins
VIH1 Input High Voltage Ports 5, 6, 7, 8 1.6 V
VIL1 Input Low Voltage Ports 5, 6, 7, 8 0.6 V
Input High Threshold Voltage
VIHT1 /RESET 1.6 V
(Schmitt trigger)
Input Low Threshold Voltage
VILT1 /RESET 0.6 V
(Schmitt trigger)
Input High Threshold Voltage
VIHT2 TCC, INT0, INT1 1.6 V
(Schmitt trigger)
Input Low Threshold Voltage
VILT2 TCC, INT0, INT1 0.6 V
(Schmitt trigger)
The voltage of Vdet is determined by RC
Vdet Low voltage detector voltage Vdet-0.2 Vdet Vdet+0.2 V
control register
Output High Voltage
IOH1 VOH = 2.4V -1.8 mA
(Ports 5, 6, 7, 8)
Output Low Voltage
IOL1 VOL = 0.4V 7 mA
(Ports 5, 6, 7, 8)
Output high voltage
IOH1 VOH = 2.4V -3.5 mA
(IROUT pin)
Output Low Voltage
IOL2 VOL = 0.4V 14 mA
(IR OUT pin)
IPH Pull-high current Pull-high active, input pin at GND -16 -23 -30 µA
IPL Pull-low current Pull-low active, input pin at VDD 16 23 30 µA
All input and I/O pins at VDD, output pin
ISB Sleep mode current 0.1 1 µA
floating, WDT disabled
/RESET= 'High', CPU OFF, sub-oscillator
ICC1 Idle mode current clock (32.768KHz) ON, output pin floating, 4 8 µA
LCD enable, no load
/RESET= 'High', CPU ON, used
ICC2 Green mode current sub-oscillator clock (32.768KHz), output pin 10 20 µA
floating, WDT enabled, LCD enable
/RESET= 'High', Fosc=4MHz (Crystal type,
ICC3 Normal mode 0.73 1.2 mA
CLKS="0"), output pin floating

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6.2 AC Electrical Characteristics

(Ta=- 40°C ~ 85 °C, VDD=5V±5%, GND=0V)
Symbol Parameter Conditions Min Typ Max Unit
Dclk Input CLK duty cycle 45 50 55 %
Instruction cycle time Crystal type 100 DC ns
Tins
(CLKS="0") RC type 500 DC ns
Ttcc TCC input period (Tins+20)/N* ns
Tdrh Device reset hold time Ta = 25°C 11.3 16.2 21.6 ms
Trst /RESET pulse width Ta = 25°C 2000 ns
Twdt Watchdog timer period Ta = 25°C 11.3 16.2 21.6 ms
Tset Input pin setup time 0 ns
Thold Input pin hold time 20 ns
Tdelay Output pin delay time Cload=20pF 50 ns
Tiod I/O delay for EMI enable Cload=150pF 4 5 6 ns
Through rate for EMI
Ttrr1 Cload=150pF 45 50 55 ns
enable(rising)
Through rate for EMI
Ttrf1 Cload=150pF 45 50 55 ns
enable(falling)
Through rate for EMI
Ttrr2 Cload=300pF 90 100 110 ns
enable(rising)
Through rate for EMI
Ttrf2 Cload=300pF 90 100 110 ns
enable(falling)
* N= selected pre-scaler ratio.

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 EM78P468N
OTP ROM

7. Application Circuit

IROUT control external BJT circuit to drive infrared emitting diodes

IROUT direct drive infrared emitting diodes

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 EM78P468N
OTP ROM

APPENDIX A:
Package information

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OTP ROM

APPENDIX B:
EM78P468N Program Pin List
It uses DWRT to program EM78P468N IC’s. The DWTR connector is selected by CON4 (EM78P451), and
software is selected by EM78P468N.
Program Pin Name QFP Pin Number IC Pin Name
VPP 25 /RESET
ACLK 32 P54/INT0
DINCLK 33 P55/INT1
DATAIN 34 P56/TCC
/PGMB 38 P60
/OEB 39 P61
VDD 29 VDD
GND 26 GND

Wiring diagram for DWTR (Display writer).

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 EM78P468N
OTP ROM

ELAN (HEADQUARTER) MICROELECTRONICS CORP., LTD.

Address : No. 12, Innovation 1st. Rd. Science-Based Industrial Park, Hsinchu City, Taiwan.
Telephone: 886-3-5639977
Facsimile : 886-3-5639966

ELAN (H.K.) MICROELECTRONICS CORP., LTD.

Address : Rm. 1005B, 10/F, Empire Centre, 68 Mody Road, Tsimshatsui, Kowloon, Hong Kong.
Telephone: 852-27233376
Facsimile : 852-27237780
E-mail : [email protected]

ELAN MICROELECTRONICS SHENZHEN, LTD.

Address : SSMEC Bldg. 3F , Gaoxin S. Ave. 1st , South Area , Shenzhen High-tech Industrial Park., Shenzhen
Telephone: 86-755-26010565
Facsimile : 86-755-26010500

ELAN MICROELECTRONICS SHANGHAI, LTD.

Address : #23 Building No.115 Lane 572 BiBo Road. Zhangjiang, Hi-tech Park, Shanghai
Telephone: 86-21-50803866
Facsimile : 86-21-50804600

Elan Information Technology Group.

Address: 1821 Saratoga Avenue, suite 250, Saratoga, CA 95070, USA
Telephone: 1-408-366-8225
Facsimile : 1-408-366-8220

Elan Microelectronics Corp. (Europe)

Address: Dubendorfstrasse 4, 8051 Zurich, Switzerland
Telephone: 41-43-2994060
Facsimile : 41-43-2994079
Email : [email protected]
Web-Site : www.elan-europe.com

Copy © 2004 by Elan Microelectronics Corp.

Elan is the owner of the intellectual property rights of the information and technology
mentioned above, as may exist now and hereafter come into exist, and all renewals and
extensions thereof. However, there is no warranty for the use of the specifications described,
either expressed or implied, including, but not limited to ,the implied warranties of
merchantability and fitness for particular purpose. The entire risk as to the quality and
performance of the application is with the user, therefore, the user will be liable for damages
including any general, special, incidental or consequential damages arising out of the use or
inability to use the information and technology. Elan reserves the right to modify the
information without prior notification. The most up-to-day information will be available on the
web site (http://www.emc.com.tw)

This specification is subject to change without prior notice. 56 04.10.2004 (V1.0)