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8086 Architecture

The 8086 architecture consists of two main units: the Execution Unit (EU) and the Bus Interface Unit (BIU), which work together to enhance processing speed. The EU is responsible for decoding and executing instructions using components like the ALU, control circuitry, and various registers, while the BIU manages data and address transfers, including an instruction queue for pipelining. The architecture supports a 20-bit addressing scheme through segment and offset calculations, allowing access to up to 1MB of memory organized into segments.

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22 views6 pages

8086 Architecture

The 8086 architecture consists of two main units: the Execution Unit (EU) and the Bus Interface Unit (BIU), which work together to enhance processing speed. The EU is responsible for decoding and executing instructions using components like the ALU, control circuitry, and various registers, while the BIU manages data and address transfers, including an instruction queue for pipelining. The architecture supports a 20-bit addressing scheme through segment and offset calculations, allowing access to up to 1MB of memory organized into segments.

Uploaded by

neelu kumari
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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8086 Architecture

The 8086 is mainly divided into mainly two blocks


1. Execution Unit (EU)
2.Bus interface Unit (BIU)
Dividing the work between these two will speedup the processing
1) EXECUTION UNIT( EU)

The Execution unit tells the BIU where to fetch instructions or data
from
 decodes instructions and

 Executes instructions

The Execution unit contains:


1) Control circuitry
2) ALU
3) FLAGS
4) General purpose Registers
5) Pointer and Index Registers

Control Circuitry:
 It directs internal operations.
 A decoder in the EU translates instructions fetched from memory
Into series of actions which the EU carries out

Arithmetic Logic Unit:


16 bit ALU
Used to carry the operations
 ADD

 SUBTRACT

 XOR

 INCREMENT

 DECREMENT

 COMPLEMENT

 SHIFT BINARY NUMBERS

FLAG REGISTERS:
 A flag is a flip flop that indicates some condition produced by
execution of an instruction or controls certain operation of the EU.

 It is 16 bit

 It has nine active flags

Divided into two types


1. Conditional flags

2. Control flags

Conditional Flags

Carry Flag (CY): This flag indicates an overflow condition for unsigned
integer arithmetic. It is also used in multiple-precision arithmetic.

Auxiliary Flag (AC): If an operation performed in ALU generates a


carry/barrow from lower nibble (i.e. D0 – D3) to upper nibble (i.e. D4 – D7),
the AC flag is set i.e. carry given by D3 bit to D4 is AC flag. This is not a
general-purpose flag, it is used internally by the Processor to perform Binary
to BCD conversion.

Parity Flag (PF):This flag is used to indicate the parity of result. If lower
order 8-bits of the result contains even number of 1’s, the Parity Flag is set
and for odd number of 1’s, the Parity flag is reset.
Zero Flag (ZF):It is set; if the result of arithmetic or logical operation is zero
else it is reset.

Sign Flag (SF):In sign magnitude format the sign of number is indicated by
MSB bit. If the result of operation is negative, sign flag is set.

Control Flags

Control flags are set or reset deliberately to control the operations of the
execution unit. Control flags are as follows:

Trap Flag (TF): It is used for single step control. It allows user to execute one
instruction of a program at a time for debugging. When trap flag is set,
program can be run in single step mode.

Interrupt Flag (IF):It is an interrupt enable/disable flag. If it is set, the


maskable interrupt of 8086 is enabled and if it is reset, the interrupt is
disabled. It can be set by executing instruction sit and can be cleared by
executing CLI instruction.

Direction Flag (DF):It is used in string operation. If it is set, string bytes are
accessed from higher memory address to lower memory address. When it is
reset, the string bytes are accessed from lower memory address to higher
memory address.

General Purpose Registers:


The 8086 general purpose registers are similar to those of earlier
generations 8080 and 8085 .It was designed in such a way that many
programs written for 8080 and 8085 could easily be translated to run on
8086.The advantage of using internal registers for the temporary storage of
data is that since data already in the EU ., it can be accessed much more
quickly than it could be accessed from external memory.
General Purpose Registers
The registers AX, BX, CX, and DX are the general 16-bit registers.
AX Register: Accumulator register consists of two 8-bit registers AL and AH,
which can be combined together and used as a 16- bit register AX. AL in this
case contains the low-order byte of the word, and AH contains the high-
order byte. Accumulator can be used for I/O operations, rotate and string
manipulation.
BX Register: This register is mainly used as a base register. It holds the
starting base location of a memory region within a data segment. It is used
as offset storage for forming physical address in case of certain addressing
mode.
CX Register: It is used as default counter or count register in case of string
and loop instructions.
DX Register: Data register can be used as a port number in I/O operations
and implicit operand or destination in case of few instructions. In integer
32-bit multiply and divide instruction the DX register contains high-order
word of the initial or resulting number.
2) BUS INTERFACE UNIT (BIU)

The BIU sends out


 Addresses
 Fetches instructions from memory
 Read data from ports and memory
Or
The BIU handles all transfer of data and addresses on the buses for
the Execution Unit
The Bus interface unit contains
1) Instruction Queue
2) Instruction pointer
3) Segment registers
4) Address Generator

Instruction Queue:
BIU gets upto 6 bytes of next instructions and stores them in the
instruction queue. When EU executes instructions and is ready for its next
instruction, then it simply reads the instruction from this instruction queue
resulting in increased execution speed. Fetching the next instruction while
the current instruction executes is called pipelining.( based on FIFO) .This is
much faster than sending out an addresses to the system memory and
waiting for memory to send back the next instruction byte or bytes .Here
the Queue will be dumped and then reloaded from the new Address.
Segment Register:
The 8086 20 bit addresses So it can address upto 220 in memory ( 1 Mbyte)
but at any instant it can address upto 4 64 KB segments. This four segments
holds the upper 16 bits of the starting address of four memory segments
that the 8086 is working with it at particular time .The BIU always inserts
zeros for the lowest 4 bits of the 20 bit starting address
Example : If the code segment register contains 348AH then the code
segment starts at 348A0H .In other words a 64Kbyte segment can be
located anywhere within 1MByte address Space but the segment will
always starts at an address with zeros in the lowest 4 bits
Stack: is a section of memory set aside to store addresses and data while
subprogram executes is often called segment base . The stack segment
register always holds the upper 16 bit starting address of program stack.
The extra segment register and data segment register is used to hold the
upper 16 bit starting addresses of two memory segments that are used for
data .
Instruction Pointer holds the 16 bit address or offset of the next code byte
within the code segment. The value contained in the Instruction Pointer
called as Offset because the value must be added to the segment base
address in CS to produce the required 20 bit address.

CS register contains the Upper 16 bit of the starting address of the


code segment in the 1 Mbyte address range the instruction pointer contains
a 16 bit offset which tells wherein that 64 Kbyte code segment the next
instruction byte has to be fetched from.
Stack Register and Stack Pointer:
Stack: is a section of memory set aside to store addresses and data
while subprogram executes is often called segment base . The stack
segment register always holds the upper 16 bit starting address of program
stack. The Stack pointer (SP) holds the 16 bit offset from the starting of the
segment to the memory location where a word was most recently stored
.The memory location where the word is stored is called as top of the stack
Pointer and Index registers:
In addition to stack pointer register EU has
Base pointer Register (BP)
Source Pointer Register(SP)
Destination Pointer Register(DP)

These three registers are used to store temporary storage of data like
general purpose registers .They hold the 16 bit offset data of the data word
in one of the segment

Programming model

How can a 20-bit address be obtained, if there are only 16-bit


registers?
However, the largest register is only 16 bits (64k); so physical addresses
have to be calculated. These calculations are done in hardware within the
microprocessor.
The 16-bit contents of segment register gives the starting/ base address of
particular segment. To address a specific memory location within a segment
we need an offset address. The offset address is also 16-bit wide and it is
provided by one of the associated pointer or index register.

To be able to program a microprocessor, one does not need to know


all of its hardware architectural features. What is important to the
programmer is being aware of the various registers within the device and to
understand their purpose, functions, operating capabilities, and limitations.

The above figure illustrates the software architecture of the 8086


microprocessor. From this diagram, we see that it includes fourteenl6-bit
internal registers: the instruction pointer (IP), four data registers (AX, BX,
CX, and DX), two pointer registers (BP and SP), two index registers (SI and
DI), four segment registers (CS, DS, SS, and ES) and status register (SR), with
nine of its bits implemented as status and control flags.

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