L6230

Datasheet

DMOS driver for three-phase brushless DC motor

Features
• Operating supply voltage from 8 to 52 V
• 2.8 A output peak current (1.4 A RMS)
• RDS(ON) 0.73 Ω typ. value at TJ = 25 °C
• Integrated fast freewheeling diodes
• Operating frequency up to 100 kHz
• Non-dissipative overcurrent detection and protection
PowerS036
• Cross conduction protection
• Diagnostic output
• Uncommited comparator
• Thermal shutdown
• Undervoltage lockout

Applications
• BLDC motor driving
VFQFPN32
• Sinusoidal / six-step driving
• Field oriented control driving system

Description

Product status link The L6230 is a DMOS fully integrated 3-phase motor driver with overcurrent
protection optimized for FOC application thanks to the independent current senses.
L6230
Realized in BCD technology, the device combines isolated DMOS power transistors
with CMOS and bipolar circuits on the same chip.
Product label An uncommitted comparator with open-drain output is available.
Available in Power SO36 and VFQFPN32 packages, the L6230 features a non-
dissipative overcurrent protection on the high-side power MOSFET and thermal
shutdown.

DS6996 - Rev 4 - November 2024 www.st.com

For further information contact your local STMicroelectronics sales office.
 L6230
Block diagram

1 Block diagram

Figure 1. Block diagram

VBOOT VSA
VBOOT VBOOT
VCP CHARGE THERMAL
PUMP PROTECTION

OCD1
OUT1
OCD1 10V

OCD OCD2
OCD3
SENSE1
DIAG-EN VBOOT

OCD2
OUT2
IN1 GATE 10V
EN1 LOGIC

IN2
EN2 SENSE2
IN3 VBOOT VSB
EN3

10V 5V OCD3
OUT3
10V
VOLTAGE
REGULATOR

SENSE3

CPOUT
+ CP+
- CP-
COMPARATOR

DS6996 - Rev 4 page 2/26

 L6230
Electrical data

2 Electrical data

2.1 Absolute maximum ratings

Table 1. Absolute maximum ratings

Symbol Parameter Test conditions Value Unit

VS Supply voltage VSA = VSB = VS 60 V

Differential voltage between: VSA = VSB = VS = 60 V

VOD 60 V
VSA, OUT1, OUT2, SENSE1, SENSE2 and VSB, OUT3, SENSE3 VSENSEx = GND

VBOOT Bootstrap peak voltage VSA = VSB = VS VS + 10 V

VIN, VEN Logic inputs voltage range - -0.3 to 7 V

VCP-, VCP+ Voltage range at CP- and CP+ pins - -0.3 to 7 V

VSENSE Voltage range at SENSEx pins - -1 to 4 V

VSA = VSB = VS
IS(peak) Pulsed supply current (for each VS pin) 3.55 A
tPULSE < 1 ms

IS RMS supply current (for each VS pin) VSA = VSB = VS 1.4 A

Tstg, TOP Storage and operating temperature range - -40 to 150 °C

2.2 Recommended operating condition

Table 2. Recommended operating condition

Symbol Parameter Test conditions Min. Max. Unit

VS Supply voltage VSA = VSB = VS 8 52 V

Differential voltage between: VSA = VSB = VS

VOD VSA, OUT1, OUT2, SENSE1, SENSE2 and VSB, OUT3, - 52 V
VSENSE1 = VSENSE2 = VSENSE3
SENSE3
VCP-, VCP+ Voltage range at pin VREF - -0.1 5 V

VCPM Common mode voltage at the comparator inputs - 0 3 V

pulsed tW < trr -6 6 V

VSENSE Voltage range at SENSEx pins
DC -1 1 V
IOUT RMS output current - - 1.4 A

fSW Switching frequency - - 100 kHz

TJ Operating junction temperature - -25 125 °C

DS6996 - Rev 4 page 3/26

 L6230
Electrical data

2.3 Thermal data

Table 3. Thermal data

Value
Symbol Description Unit
PowerSO36 VFQFPN32

Rth(j-amb)1 Maximum thermal resistance junction ambient (1) 36 - °C/W

Rth(j-amb)1 Maximum thermal resistance junction ambient (2) 16 - °C/W

Rth(j-amb)2 Maximum thermal resistance junction ambient (3) 63 - °C/W

Rth(j-amb)3 Maximum thermal resistance junction ambient (4) - 42 °C/W

1. Mounted on a multilayer FR4 PCB with a dissipating copper surface on the bottom side of 6 cm2 (with a thickness of 35 μm).
2. Mounted on a multilayer FR4 PCB with a dissipating copper surface on the top side of 6 cm2 (with a thickness of 35 μm), 16
via holes and a ground layer.
3. Mounted on a multilayer FR4 PCB without any heat-sinking surface on the board.
4. Mounted on a double-layer FR4 PCB with a dissipating copper surface of 0.5 cm2 on the top side plus 6 cm2 ground layer
connected through 18 via holes (9 below the IC).

DS6996 - Rev 4 page 4/26

 L6230
Pin connections

3 Pin connections

Figure 2. Pin connection PowerSO36 (top view)

GND 1 36 GND
N.C. 2 35 N.C.
N.C. 3 34 N.C.
VSA 4 33 VSB
OUT2 5 32 OUT3
N.C. 6 31 N.C.
VCP 7 30 VBOOT
SENSE2 8 29 EN3
IN1 9 28 CP-
EN1 10 27 EN2
IN3 11 26 IN2
SENSE1 12 25 SENSE3
CP+ 13 24 CPOUT
N.C. 14 23 N.C.
OUT1 15 22 DIAG-EN
N.C. 16 21 N.C.
N.C. 17 20 N.C.
GND 18 19 GND

Note: The slug is internally connected to pins 1, 18, 19, and 36 (GND pins).

Figure 3. Pin connection VFQFPN32 (top view)

SENSE1

SENSE2
OUT1

CP+

EN1
IN3

IN1
NC

32 31 30 29 28 27 26 25

GND 1 24 VCP

NC 2 23 OUT2

NC 3 22 VSA

NC 4 21 GND

NC 5 20 VSB

NC 6 19 OUT3

NC 7 18 NC

NC 8 17 VBOOT

9 10 11 12 13 14 15 16
DIAG-EN

EN2
IN2
SENSE3

EN3
NC

CP-
CPOUT

Note: The pins 2 to 8 are connected to the die PAD.

The die PAD must be connected to the GND pin.

DS6996 - Rev 4 page 5/26

 L6230
Pin connections

Table 4. Pin description

PowerSO36 VFQFPN32 Pin name Type Function

Bootstrap voltage needed for driving the upper power

30 17 VBOOT Power supply
MOSFETs.
7 24 VCP Output Charge pump oscillator output.
Double function: chip Enable as input and overcurrent/
overtemperature indication as output.
LOW logic level switches OFF all power MOSFETs, putting
Logic output/
22 9 DIAG-EN the power stages in high impedance status.
input
An internal open-drain transistor pulls to GND the pin
when an overcurrent on one of the high-side MOSFETs is
detected or during thermal protection.
9 26 IN1 Logic input Driving input half-bridge 1.
10 27 EN1 Logic input Enable input half-bridge 1.
26 13 IN2 Logic input Driving input half-bridge 2.
27 14 EN2 Logic input Enable input half-bridge 2.
11 28 IN3 Logic input Driving input half-bridge 3.
29 16 EN3 Logic input Enable input half-bridge 3.
28 15 CP- Analog input Inverting input of internal comparator.
13 30 CP+ Analog input Non-inverting input of internal comparator.
24 11 CPOUT Output Open-drain output of internal comparator.
Half-bridge 3 source pin. This pin must be connected to
25 12 SENSE3 Power supply
power ground through a sensing power resistor.
32 19 OUT3 Power output Output half-bridge 3.
Half-bridge 3 power supply voltage. It must be connected
33 20 VSB Power supply
to the supply voltage together with pin VSA.
Half-bridge 2 source pin. This pin must be connected to
8 25 SENSE2 Power supply
power ground through a sensing power resistor.
5 23 OUT2 Power output Output half-bridge 2.
Half-bridge 1 source pin. This pin must be connected to
12 29 SENSE1 Power supply
power ground through a sensing power resistor.
15 31 OUT1 Power output Output half-bridge 1.
Half-bridge 1 and half-bridge 2 power supply voltage. It
4 22 VSA Power supply must be connected to the supply voltage together with pin
VSB.
1, 18, 19, 36 1 GND Ground Ground terminal.
These pins are connected to the die PAD.
- 2, 3, 4, 5, 6, 7, 8 NC -
The die PAD must be connected to the GND pin.
2, 3, 6, 14, 16, 17,
20, 21, 23, 31, 34, 10, 18, 32 NC - Not connected.
35

DS6996 - Rev 4 page 6/26

 L6230
Electrical characteristics

4 Electrical characteristics

Test conditions: VS = 48 V, Tamb = 25 °C , unless otherwise specified.

Table 5. Electrical characteristics

Symbol Parameter Test condition Min. Typ. Max. Unit

VSth(ON) Turn ON threshold 5.8 6.3 6.8 V

VSth(OFF) Turn OFF threshold 5 5.5 6 V

All bridges OFF;

IS Quiescent supply current - 5 10 mA
TJ = -25 to 125 °C (1)

TJ(OFF) Thermal shutdown temperature - 165 - °C

Output DMOS transistors

TJ = 25 °C - 0.73 0.85 Ω
RDS(ON) High-side / low-side switch ON resistance
TJ = 125 °C (1)
- 1.18 1.35 Ω

DIAG-EN = LOW; OUT = VS - - 2 mA

IDSS Leakage current
DIAG-EN = LOW; OUT = GND -0.3 - - mA
Source drain diodes
VSD Forward ON voltage ISD = 1.4 A, DIAG-EN = LOW - 1.15 1.3 V

trr Reverse recovery time If = 1.4 A - 300 - ns

tfr Forward recovery time - 200 - ns

Logic input (INx, ENx, DIAG-EN)

VIL Low level logic input voltage - - 0.8 V

VIH High level logic input voltage 2 - - V

IIL Low level logic input current 0 V logic input voltage -10 - - μA

IIH High level logic input current 7 V logic input voltage - - 10 μA

Switching characteristics
tD(ON)EN Enable to out turn-on delay time (2) 500 650 800 ns

tD(OFF)EN Enable to out turn-off delay time(2) 500 - 1000 ns

tD(ON)IN Other logic inputs to output turn-on delay time - 1.6 - µs

ILOAD = 1.4 A, resistive load
tD(OFF)IN Other logic inputs to out turn-off delay time - 800 - ns

tRISE Output rise time (2) 40 - 250 ns

tFALL Output fall time (2) 40 - 250 ns

tDT Dead time 0.5 1 - µs

fCP Charge pump frequency TJ = -25 to 125 °C(1) - 0.6 1 MHz

Comparator
VOFFSET Offset voltage VCP- = 0.5 V -14 - +14 mV

tprop Turn OFF propagation delay (3) - 500 - ns

IBIAS Input bias current - - 10 µA

RCPOUT Open-drain ON resistance - 40 60 Ω

DS6996 - Rev 4 page 7/26

 L6230
Electrical characteristics

Symbol Parameter Test condition Min. Typ. Max. Unit

Overcurrent detection and protection

ISOVER Supply overcurrent protection threshold TJ = -25 to 125 °C(1) 2 2.8 3.55 A

RDIAG Open drain ON resistance IDIAG = 4 mA - 40 60 Ω

tOCD(ON) OCD turn-ON delay time(4) IDIAG = 4mA; CDIAG < 100 pF - 200 - ns

tOCD(OFF) OCD turn-OFF delay time(4) IDIAG = 4mA; CDIAG < 100 pF - 100 - ns

1. Tested at 25 °C in a restricted range and guaranteed by characterization.

2. See Figure 4: Switching characteristic definition.
3. Measured applying a voltage of 1 V to pin CP- and a voltage drop from 2 V to 0 V to pin CP+.
4. See Figure 5.

Figure 4. Switching characteristic definition

DIAG-EN

V th(ON)

V th(OFF)

t
I OUT

90%

10%
t
tFALL t RISE
t D(OFF)EN t D(ON)EN

Figure 5. Overcurrent detection timing definition

IOUT

I SOVER

ON
BRIDGE
OFF

VDIAG-EN

90%

10%

t OCD(ON) t OCD(OFF)

DS6996 - Rev 4 page 8/26

 L6230
Circuit description

5 Circuit description

5.1 Power stages and charge pump

The L6230 device integrates a triple half-bridge bridge, which consists of 6 power MOSFETs connected as shown
in the block diagram (see Figure 1), each power MOSFET has an RDS(ON) = 0.73 Ω (typical value at 25 °C) with
intrinsic fast free-wheeling diode. Cross conduction protection is implemented by using a deadtime (tDT = 1 μs
typical value) set by internal timing circuit between the turn off and turn on of two power MOSFETs in one leg of a
bridge.
Pins VSA and VSB must be connected together to the supply voltage (VS).
Using N-channel power MOSFET for the upper transistors in the bridge requires a gate drive voltage above the
power supply voltage. The bootstrapped supply (VBOOT) is obtained through an internal oscillator and few
external components to realize a charge pump circuit as shown in Figure 6. The oscillator output (pin VCP) is a
square wave at 600 kHz (typically) with 10 V amplitude. Recommended values/part numbers for the charge pump
circuit are shown in Table 6.

Table 6. Charge pump external component values

Component Value

CBOOT 220 nF

CP 10 nF

D1 1N4148

D2 1N4148

Figure 6. Charge pump circuit

VS

D1 CBOOT
D2

CP

VCP VBOOT VSA VSB

DS6996 - Rev 4 page 9/26

 L6230
Circuit description

5.2 Logic inputs

Pins INx and ENx are TTL/CMOS and microcontroller compatible logic inputs. The internal structure is shown in
Figure 7. Typical value for turn-ON and turn-OFF thresholds are respectively Vth(ON) = 1.8 V and Vth(OFF) = 1.3 V.
The pin DIAG-EN has identical input structure with the exception that the drain of the overcurrent and thermal
protection MOSFET is also connected to this pin. Due to this connection some care needs to be taken in driving
this pin. The EN input may be driven in one of two configurations as shown in Figure 8 or Figure 9. If driven by an
open-drain (collector) structure, a pull-up resistor REN and a capacitor CEN are connected as shown in Figure 8. If
the driver is a standard push-pull structure the resistor REN and the capacitor CEN are connected as shown in
Figure 9.
The resistor REN should be chosen in the range from 2.2 kΩ to 180 kΩ. Recommended values for REN and CEN
are respectively 100 kΩ and 5.6 nF. More information for selecting the values can be found in Section 5.3.

Figure 7. Logic input internal structure

5V

ESD
PROTECTION

Figure 8. Pin DIAG-EN open collector driving

Figure 9. Pin DIAG-EN push-pull driving
5V
5V 5V
REN
REN DIAG-EN
OPEN DIAG-EN P USH-PULL
C OLLECTOR OUTPUT
OUTPUT CEN
CEN ESD
ESD PROTECTION
PROTECTION

Table 7. Truth table

Inputs Outputs

DIAG-EN ENx INx OUTx

L X (1) X (1) High-Z (2) (3)

H L X (1) High-Z (2)

H H L Low-side MOSFET on
H H H High-side MOSFET on

1. X: don't care.
2. High impedance output (both high-side and low-side MOSFETs off).
3. All half-bridges disabled.

DS6996 - Rev 4 page 10/26

 L6230
Circuit description

5.3 Non-dissipative overcurrent detection and protection

The L6230 device integrates an “Overcurrent Detection” circuit (OCD) for full protection. This circuit provides
output to output and output to ground short-circuit protection as well.
With this internal overcurrent detection, the external current sense resistor normally used and its associated
power dissipation are eliminated. Figure 10 shows a simplified schematic for the overcurrent detection circuit.
To implement the overcurrent detection, a sensing element that delivers a small but precise fraction of the output
current is implemented with each high-side power MOSFET. Since this current is a small fraction of the output
current there is very little additional power dissipation. This current is compared with an internal reference current
IREF. When the output current reaches the detection threshold (typically ISOVER = 2.8 A) the OCD comparator
signals a fault condition. When a fault condition is detected, an internal open-drain MOSFET with a pull down
capability of 4 mA connected to pin DIAG is turned on.
The pin DIAG-EN can be used to signal the fault condition to a microcontroller or to shut down the 3-phase bridge
simply by connecting it to pin EN and adding an external R-C (see REN, CEN).

Figure 10. Overcurrent protection simplified schematic

Figure 11 shows the overcurrent detection operation. The disable time tDISABLE before recovering normal
operation can be easily programmed by means of the accurate thresholds of the logic inputs. It is affected
whether by CEN and REN values and its magnitude is reported in Figure 12. The delay time tDELAY before turning
off the bridge when an overcurrent has been detected depends only by CEN value. Its magnitude is reported in
Figure 13.
The CEN is also used for providing immunity to pin DIAG-EN against fast transient noises. Therefore the value of
CEN should be chosen as big as possible according to the maximum tolerable delay time and the REN value
should be chosen according to the desired disable time.
The resistor REN should be chosen in the range from 2.2 kΩ to 180 kΩ. Recommended values for REN and CEN
are respectively 100 kΩ and 5.6 nF that allow obtaining 200 μs disable time.

DS6996 - Rev 4 page 11/26

 L6230
Circuit description

Figure 11. Overcurrent protection waveforms

IOUT

ISOVER

DIAG-EN
V DD

V th(ON)
V th(OFF)
V EN(LOW)

ON
OCD
OFF

ON

BRIDGE t DELAY t DISABLE

OFF

t OCD(ON) t EN(FALL) t OCD(OFF) t EN(RISE) t D(ON)EN

t D(OFF)EN

Figure 12. tDISABLE versus CEN and REN

R EN = 220 k R EN = 100 k
1 1 0
3
R EN = 47 k
R EN = 33 k

R EN = 10 k

100
tDISABLE [µs]

10

1
1 10 100
C EN [n F ]

DS6996 - Rev 4 page 12/26

 L6230
Circuit description

Figure 13. tDELAY versus CEN

10

tDELAY [s]

0.1
1 10 100
CEN [nF]

DS6996 - Rev 4 page 13/26

 L6230
Application information

6 Application information

A typical application using the L6230 device is shown in this section.

A high quality ceramic capacitor (C2) in the range of 100 nF to 200 nF should be placed between the power pins
VSA and VSB and ground near the L6230 device to improve the high frequency filtering on the power supply and
reduce high frequency transients generated by the switching.
The capacitor (CEN) connected from the DIAG-EN input to ground sets the shutdown time when an overcurrent is
detected (see Section 5.3).
The current sensing inputs (SENSEx) should be connected to the sensing resistor RSENSE with a trace length as
short as possible in the layout. The sense resistor should be non-inductive resistor to minimize the dI/dt transients
across the resistor. To increase noise immunity, unused logic pins are best connected to 5 V (high logic level) or
GND (low logic level), see Table 4. It is recommended to keep power ground and signal ground separated on
PCB.

Table 8. Component values for typical application

Component Value

C1 100 µF

C2 100 nF

CBOOT 220 nF

CEN 5.6 nF

CP 10 nF

D1 1N4148

D2 1N4148

REN 100 kΩ

The examples reported describe some typical application to drive a 3-phase BLDC motor using the L6230 device.
In the first example is shown a field oriented control (FOC) system, with this method it is possible to provide
smooth and precise motor control of BLDC motors.
A six-step driving method with current control is reported in the second example, the inputs sequence is
generated by an external controller and the L6230 comparator is used to obtain the information for the peak
current control.
Finally, the third example shows how to implement a sensorless motor control system, the information on the rotor
position is achieved by BEMF zero-crossing detection.

DS6996 - Rev 4 page 14/26

 L6230
Application information

6.1 Field oriented control driving method

In this configuration (see Figure 14) three sensing resistors are required, one for each channel. The sensing
signals coming from the output power stage are conditioned by external operational amplifiers which provide the
proper feedback signals to the AtoD converter and the system controller. According to the feedback signals the
six input lines are generated by the controller.
Note that some filtering and level shifting RC networks should be added between the sense resistor and the
correspondent op-amp input.
The uncommitted internal comparator with open-drain output is available.

Figure 14. F.O.C. typical application

REN
+ VSA DIAG/EN ENABLE
VS
C1 C2 CEN
8 - 52 VDC VSB
D1
POWER
CP
GROUND IN1 IN1
- VCP
EN1 EN1
D2
CBOOT
IN2 IN2
SIGNAL VBOOT
GROUND RSENSE EN2 EN2
SENSE1
RSENSE IN3 IN3
SENSE2
EN3 EN3
RSENSE
SENSE3

Signal conditioning

ADC +
CP+
-
CPOUT
CP-

OUT1
THREE-PHASE
M OUT2
MOTOR
OUT3
GND

DS6996 - Rev 4 page 15/26

 L6230
Application information

6.2 Six-step driving method with current control

In this configuration only one sense resistor is needed, the three OUT pins are connected together to the RSENSE
(see Figure 15).
The inverting input comparator CP- monitors the voltage drop across the external sense resistor connected
between the source of the three lower power MOSFET transistors and ground.
As the current in the motor increases the voltage across the RSENSE increases proportionally. When the voltage
drop across the sense resistor becomes greater than the reference voltage applied at non-inverting input CP+ the
internal open-drain is switched on pulling down the CPOUT pin.
This signal could be managed by the controller to generate the proper input sequence for the six-step driving
method with current control and select what current decay method to implement.
When the sense voltage decreases below the CP+ voltage, the internal open-drain is switched off and the voltage
at the CPOUT pin starts to increase charging the capacitor CCPOUT.
The reference voltage at the pin CP+ will be set according to the sense resistor value and the desired regulated
current (VCP+ ≈ RSENSE ∙ ITARGET). A very simple way to obtain variable voltage is the low-pass filtering of the
PWM signal coming from a controller.

Figure 15. Six-step with current control typical application

REN
+ VSA DIAG/EN ENABLE
VS
C1 C2 CEN
8 - 52 VDC VSB
D1
POWER
CP
GROUND IN1 IN1
- VCP
EN1 EN1
D2
CBOOT
IN2 IN2
SIGNAL VBOOT
GROUND RSENSE EN2 EN2
SENSE1
IN3 IN3
SENSE2
EN3 EN3

SENSE3

CP-
RCP+
PWM
CP+ RCPOUT
from controller
CCP+
Current control
CPOUT
signal
CCPOUT
OUT1
THREE-PHASE M OUT2
MOTOR
OUT3 GND

6.3 Thermal management

In most applications the power dissipation in the IC is the main factor that sets the maximum current that can be
delivered by the device in a safe operating condition. Therefore, it has to be taken into account very carefully.
Besides the available space on the PCB, the right package should be chosen considering the power dissipation.
Heat-sinking can be achieved using copper on the PCB with a proper area and thickness.
For instance, using a VFQFPN32L 5x5 mm package the typical Rth(JA) is about 42 °C/W when mounted on a
double-layer FR4 PCB with a dissipating copper area of 0.5 cm2 on the top side plus the 6 cm2 ground layer
connected through 18 via holes (9 below the IC).
Otherwise, using a PowerSO package with a copper slug soldered on a 1.5 mm copper thickness FR4 board with
a 6 cm2 dissipating footprint (copper thickness of 35 μm), the Rth(jA) is about 35 °C/W. Using a multi-layer board
with vias to a ground plane, thermal impedance can be reduced down to 15 °C/W.

DS6996 - Rev 4 page 16/26

 L6230
Package information

7 Package information

To meet environmental requirements, ST offers these devices in different grades of ECOPACK packages,
depending on their level of environmental compliance. ECOPACK specifications, grade definitions, and product
status are available at: www.st.com. ECOPACK is an ST trademark.

7.1 VFQFPN32 package information

Figure 16. VFQFPN 5x5x1.0 mm, 32 lead, pitch 0.50 package outline

DS6996 - Rev 4 page 17/26

 L6230
Package information

Table 9. VFQFPN 5x5x1.0 mm, 32 lead, pitch 0.50 mechanical data

Dimensions (mm)
Symbol
Min. Typ. Max.

A 0.80 0.85 0.90

A1 0 - 0.05
A3 - 0.20 -
b 0.20 0.25 0.30
D 4.90 5.00 5.10
D2 3.90 4.00 4.10
E 4.90 5.00 5.10
E2 3.00 3.10 3.20
e - 0.50 -
L 0.30 0.40 0.50
e1 - 0.175 -
e2 - 0.250 -
S1 - 0.31 Ref -
ddd - - 0.08

DS6996 - Rev 4 page 18/26

 L6230
Package information

7.2 PowerSO36 package information

Figure 17. PowerSO36 package outline
1 1

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DS6996 - Rev 4 page 19/26

 L6230
Package information

Table 10. PowerSO36 package mechanical data

Dimensions

Symbol mm

Min. Typ. Max.

A - - 3.60
a1 0.10 - 0.30
a2 - - 3.30
a3 0 - 0.10
b 0.22 - 0.38
c 0.23 - 0.32

D (1) 15.80 - 16.00

D1 9.40 - 9.80
E 13.90 - 14.50
e - 0.65 -
e3 - 11.05 -

E1 (1) 10.90 - 11.10

E2 - - 2.90
E3 5.80 - 6.20
E4 2.90 - 3.20
G 0 - 0.10
H 15.50 - 15.90
h - - 1.10
L 0.80 - 1.10
N 10° (max.)
S 8° (max.)

1. “D” and “E1” do not include mold flash or protrusions.

• - Mold flash or protrusions shall not exceed 0.15 mm (0.006 inch)
• - Critical dimensions are “a3”, “E” and “G”.

DS6996 - Rev 4 page 20/26

 L6230
Ordering information

8 Ordering information

Table 11. Order code

Order Code Package Package marking Packing

L6230PD PowerSO36 L6230PD Tube

L6230PDTR PowerSO36 L6230PD Tape and reel
L6230Q VFQFPN32 L6230Q Tube
L6230QTR VFQFPN32 L6230Q Tape and reel

DS6996 - Rev 4 page 21/26

 L6230

Revision history
Table 12. Document revision history

Date Revision Changes

14-Oct-2010 1 First release.

07-Jun-2011 2 Updated maturity status from preliminary data to final datasheet.
Updated Figure 1.
Updated Table 1 and Table 2 (corrected SENSE pin labels).
Updated Figure 2, Figure 3, Figure 10, Section 5.3, and Figure 14 to Figure 1 (replaced “DIAG/EN”
by “DIAG-EN”).

01-Aug-2016 3 Added cross-reference to Table 4in Section 6,

to Section 5.3 in Section 5.2 and in Section 6.
Updated Section 6.2 (several updates).
Replaced “DIAG/EN” by “DIAG-EN” in whole document.
Minor modifications throughout document.
Updated Table 2, Table 4, and Table 5.
Added Table 7.
15-Nov-2024 4
Updated Section 5.1, Section 5.3, and Section 7.1.
Removed 'Six-step driving method with BEMF zero-crossing detection' section.

DS6996 - Rev 4 page 22/26

 L6230
Contents

Contents
1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
2 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2.1 Absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.2 Recommended operating condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.3 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3 Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
4 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
5 Circuit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
5.1 Power stages and charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.2 Logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.3 Non-dissipative overcurrent detection and protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
6 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
6.1 Field oriented control driving method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.2 Six-step driving method with current control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.3 Thermal management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
7.1 VFQFPN32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7.2 PowerSO36 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
8 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
List of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
List of figures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

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List of tables

List of tables
Table 1. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Table 2. Recommended operating condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Table 3. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 4. Pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 5. Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 6. Charge pump external component values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 7. Truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 8. Component values for typical application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 9. VFQFPN 5x5x1.0 mm, 32 lead, pitch 0.50 mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 10. PowerSO36 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 11. Order code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 12. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

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List of figures

List of figures
Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Figure 2. Pin connection PowerSO36 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 3. Pin connection VFQFPN32 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 4. Switching characteristic definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 5. Overcurrent detection timing definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 6. Charge pump circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 7. Logic input internal structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 8. Pin DIAG-EN open collector driving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 9. Pin DIAG-EN push-pull driving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 10. Overcurrent protection simplified schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 11. Overcurrent protection waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 12. tDISABLE versus CEN and REN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 13. tDELAY versus CEN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 14. F.O.C. typical application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 15. Six-step with current control typical application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 16. VFQFPN 5x5x1.0 mm, 32 lead, pitch 0.50 package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 17. PowerSO36 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

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