Driver and Interface for Kyocera 320x240 QVGA LCD

Lajos Losonczi 1) and Iuliu Szekely 2)

1)
R&D Department, Lambda Communications Ltd., Targu Mures, Romania
2)
Electronics and Computers Department, Transylvania University of Brasov, Romania

Abstract: This paper is presenting the authors’ realization of an original, tested and applied driver and
interface - called D/I - made for QVGA LCD with Touch Screen, type Kyocera KCG057QV1. We proposed, to
achieve with a reduced number of components, a set of important functions: interface signal generation, display
data generation, touch screen interface, power supply command sequences generation, USB and RS232/485
interface, back light signal generation, screen memory, character generator. All of these functions are controlled
with a single LSI integrated circuit: the multiprocessor microcontroller Propeller-P8X32A, made by Parallax
Inc. This allows the development of a complex driver and interface for which, since not so long ago, there were
used industrial microcomputer modules or specialized FPGA circuits.
Even in these conditions, the generation of fast synchronization signals was possible only through rapid timing,
by calculating the effective duration of the performed machine code instructions, used in Propeller Driver
Objects written in assembly language. This paper is focused on presenting this issue.

1. INTRODUCTION the specialized driver used TPC-10, which solves a

part of analog signal processing [3]. To supply the
Block Diagram of the D/I and Kyocera QVGA- STN- high voltage backlight module (1.8kV) of the display,
LCD is shown in Figure 1. It can be seen, that all it uses a specialized modular DC to AC Inverter [4].
commands are given by P8X32A microcontroller that To store several screen picture information (bitmap),
contains 8 individual processors of 32-bit [1]. Signals has been provided a serial access (I2C) EEPROM
generated to drive the (320xRGB)x240 dot format memory block, with 256 kB capacity. Also, to store
must match stringent criteria in terms of succession the firmware of the applications, it has been provided
and fasting change in time [2]. Handling signals of the an individual 32kB capacity I2C EEPROM.
120x91mm size Touch Panel is an easier job, due to

I2C
4 x 64KB Touchscreen 4 bit

Driver Touch Panel 115x88 mm

EEPROM
6 bit
I2C

USB D0-D7 8 bit

Serial
RS232/485 CP

Parallax LOAD
SEG DRIVER IC
4 bit I/O P8X32A

+3.3V Propeller FRM

COM [320 x R.G.B] x 240
VBLEN
DRIVER
9 - 24 Vac
Power VDDEN DISP IC LCD
Supply VDD VDD
VDD

VEE VEE
VEE
+12V VBL
INVERTER CFL BACKLIGHT

Fig.1 Circuit Block Diagram: D/I and LCD

 To achieve communication with the outside there Data is sent to the LCD one row at a time,
are used dedicated circuits (USB, RS232/485). Power followed by a pulse on the LOAD signal, which
supply block has a complex relationship because it has causes the data to be latched into place and displayed
to be provided a wide range of stabilized voltages for on the next row. When the FRM signal is asserted
different functional blocks (CPU-12V, CPU-5V, high, LOAD causes the data to be displayed on the
CPU-3.3V, LCD-3.3V, LCD-3.3V/C, BL-12V), with first (top) row. The latch action takes place when
a sequence of connection / disconnection strictly LOAD falls from high to low. LCD has 8 data lines
determined. named D0, D1, … D7. Data is placed on these lines
The external supply voltage value is 16VAC/2A, and clocked in by falling pulse on the CP line. For 320
and is allowed a variation in a relatively wide voltage pixels, there will be 320x3=960 bits per row. With 8
range: 9-24VAC, due to use of switching regulators. data lines there will be 960/8=120 clock pulses on CP
per row. Bits are placed on the data lines as shown in
2. DRIVER SIGNALS FOR LCD Figure 3., where R,G,B are abbreviations for Red,
Green, Blue followed by the pixel number. The
Every Kyocera STN (passive matrix technology) described 320x240 format is called single scan
color LCDs has interface signals named LOAD, FRM, QVGA.
CP, and DISP, as well as 8 data lines D0-7. Using
these signals, it can make colored pixels appear on the
screen of the LCD. A pixel is a square dot of color, CP x (320xR.G.B) / 8 pulse
but it really consists of narrow red, blue and green
subpixels, side-by-side. Although in this application LOAD

the format of the screen is 320x240 pixels, meaning

CP
320 pixels across and 240 rows, but at the interface
level each row requires 960 bits, one for each D7 G318 R1 B3 G318 R1
subpixel.
Figure 2. presents the characteristics of the input D6 B318 G1 R4 B318 G1
timing, and the switching characteristics for the LCD
driver. D5 R319 B1 G4 R319 B1

D4 G319 R2 B4 G319 R2
60nS 40nS 100nS

D3 B319 G2 R5 B319 G2

CP
D2 R320 B2 G5 R320 B2
>25nS

D1 G320 R3 B5 G320 R3
D 0-7
D0 B320 G3 R6 B320 G3

60nS
FRM

CP last 1st
40nS 500nS
400nS

LOAD LOAD

>120nS >30nS X1 X2 X3-240 X1

D 0-7

FRM >170nS FRM

Fig. 2 LCD input timing chart Fig. 3 LCD interface timing chart
 The DISP signal must be held high during normal alphanumerical characters), then solving the control
operation. It should be held low to suppress display problem with a single integrated circuit seems
artifacts during power-up and power-down. impossible. But we found an interesting solution to
If the LCD driving voltage is left applied to a LCD resolve this requirement!
cell for any length of time, the liquid crystal
molecules become permanently polarized so that they 3. THE PROPELLER CHIP
can no longer assume their light transmitting
orientation. The solution is to reverse the polarity of The propeller chip is designed to provide
the LCD drive voltage hundreds of times per second. flexibility and high-speed processing for embedded
So, the controller must provide an AC signal to systems, through its eight processors, called Cogs, that
control the internal drive voltage polarization. After can perform simultaneous tasks independently or
the technical specifications, the used LCD accepts the cooperatively, sharing resources through a central
LOAD signal as input, to produce the polarization Hub, all while maintaining a relatively simple
signal. The only problem is, that for this reason, the architecture that is easy to learn and use [5].
cycle of LOAD signal should be stable and Common resources (I/O pins and the System
continuously applied without interruption. An LCD Counter) can be accessed at any time by any number
can easily be destroyed if the liquid crystal driver of Cogs. As shown in Figure. 4, mutually-exclusive
voltage is allowed to stay too long with the same resources (RAM, ROM, Configuration, Control), can
polarity! also be accessed by any number of Cogs, but only by
In consideration of display quality, it is one cog at a time, and the access to them is controlled
recommended that frame frequency to be set in the by the Hub.
range of 70 – 120Hz. Generally, as frame and clock
frequencies become higher, current consumption will
get bigger and display quality will be degraded.
On the other hand, if the frame frequency becomes
lower, the stability of the picture is broken, and the
vibration effect will occur.
This means that severe conditions are required for
design, if we want to generate through software
signals for the LCD driver. If we start from an
acceptable value for the frame frequency, of 80Hz,
this means that FRM signal period must be 1/80 =
12,5mS. As a result of this the LOAD signal period
must be 12,5mS / 240 = 52,1uS, and CP signal period
must be 52,1uS / (320x3)/8 = 434nS, what
corresponds to a data loading frequency of 1/434nS =
2,3MHz. Fig. 4 Hub and Cog interaction
These conditions (generating pulses of 150- 200nS,
with a frequency of 2.3 MHz and transferring with the Each Cog has its own RAM, called CogRAM
same speed the picture information from memory to (2kB configured as 512x32bits), and can be started
the LCD screen, respectively to generate other and stopped at run time and can be programmed to
interface signals synchronized with the CP signal perform tasks simultaneously, either independent or
fronts) are difficult to meet even using specialized with coordination from other Cogs through HubRAM
discrete controller IC or FPGA. ( 32kB ).
If we take into consideration that besides of the The Hub controls access to mutually-exclusive
generation of interface signals and transferring the resources by giving each Cog a turn in a "round robin"
image data to the LCD controller, should be solved fashion. The Hub and its bus run at half the System
many other important tasks (touchscreen signal Clock rate, giving a cog access to resources once
processing, serial communication with PC or other every 16 clock cycles. Hub instructions (assembly
embedded systems, control the own peripherals, instructions that access mutually-exclusive resources)
control I / O the signals, generating of graphical or require 7 cycles to execute but they first need to be
synchronized to the start of the Hub Access Window. In Figure 5. is presented the structure flowchart of the
It takes up to 15 cycles (16 minus 1, if we just missed LCD driver routine and in continue in Figure 6. is
it) to synchronize to the window, plus 7 cycles to presented the structure of assembly routine that
execute the Hub instruction, so Hub instructions take generates the LCD driver signals also that generates
from 7 to 22 cycles to complete. In the worst-case the loading procedure of image data (bitmaps) in the
scenario, the Cog waits until the next Hub Access LCD screen memory.
Window 15 cycles, then the Hub instruction executes
(7 cycles).
Again, there are 9 additional cycles after the Hub RUNLCD
instruction for other instructions to execute before the
next window arrives. Since most Cog assembly
DBUF  [DATPTR]
instructions take 4 clock cycles - except the
conditional branching instructions that take 8 cycles if
the condition isn't occurring (no jump) and 4 cycles if CP = 1
the condition occurring (jump), respectively except
the wait instructions - two such instructions can be PORTD  DBUF
executed in between otherwise contiguous Hub
instructions. So, to minimize clock waste, it can insert DATPTR = DATPTR+1
two 4-clock instructions between any two otherwise-
contiguous Hub instructions, without any increase in CP = 0
execution time.
The System Clock is the central clock source for DBUF  [DATPTR]
nearly every component of the Propeller chip. The
System Clock's signal comes from one of three CNTH = CNTH - 1
possible sources:
- the internal RC oscillator (20kHz or 12MHz)
N
- the XI input pin (crystal oscillator) CNTH = 0
- the clock PLL fed by the XI input (internally ?

multiplies the XIN pin frequency by 16) Y

The frequency range for the System Clock is 0- LOAD = 1
80MHz. A typical way to run the chip at the
maximum frequency of 80MHz is to use an external CNTH = 120
crystal oscillator of 5MHz and to enable the clock
PLL to multiply clock frequency by 16. This method CNTV = CNTV - 1
is also used in submitted applications.

4. LCD SIGNAL INTERFACE N

CNTV = 0
?

So, running the processor at 80MHz (12.5nS) Y

means, that the execution times of a regular Cog LOAD = 0 LOAD = 0
instructions will be 50 ns, and the duration of a Hub
instructions will be between 87.5-275nS. The use of DATPTR = ADRTAB FRM = 0
the execution time of an assembly instruction for
timing and for LCD driver signal generation, results in CNTV = 240
being able to fit in the time requirements imposed by
the technical specifications, if we choose the right FRM = 1
program instructions of the routine loop that generates
these signals. It should also be kept in mind any
further delays that will result from the use of Hub
instructions of variable duration. Fig. 5 LCD driver flowchart
 Contents of a full screen image, charge 320x3x240/8 synchronized with the System Clock. The clock cycles
= 28,800 bytes. These data are stored in advance in counting begins with the RDBYTE Hub instruction
HubRAM, by running in another Cog an independent because in this way it can calculate the number of
routine for external data transfer via serial cycles waiting for Hub Access Windows till the next
communication, or for transfer from the system call of the same instructions RDBYTE. From the
memory block. The start address of image data block diagram in Figure 7. results, that this number is 5, so
(screen bitmap) in HubRAM is called ADRTAB and the total duration of instruction is 5+7 = 12 cycles.
the pointer indicating the address of the current
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4
reading bytes from memory is called DATPTR.
Reading a byte from the current HubRAM address MOV PORTD,
RDBYTE DBUF, DATPTR DJNZ CNTH, SET CP
DATPTR is made by Hub instruction RDBYTE and RUNLCD DBUF
7 4 4 4
should be filed in the DBUF register in CogRAM,
from where will be transferred through MOV
3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7
instructions to PORTD output port, connected to the
LCD data inputs D0-7. WAIT for
ADD DATPTR, RESET CP RDBYTE DBUF, DATPTR
Previously it initializes two local counters, CNTH and #1 RDBYTE
4 4 5 7
CNTV, for counting the internal routine loops
(initialized data).
Fig. 7 Instructions time diagram

RUNLCD SET CP ; 4 It should be noted, that in this case, we interleave two

MOV PORTD, DBUF ; 4 non-Hub instructions wit Hub instruction to lower the
ADD DATPTR, #1 ; 4
RESET CP ; 4
number of cycles waiting for the next Hub Access
RDBYTE DBUF, DATPTR ; 5+7 Window.
DJNZ CNT1, RUNLCD ; 4 Similarly, by calculating the length of the
SET LOAD ; 4+4 instructions, we can calculate the time evolution of the
MOV CNTH, #120 ; 4 driver signals (CP, LOAD, FRM and PORTD) in the
DJNZ CNTV, RUN1 ; 4
RESET LOAD ; 4+4 presented routine. Finally, we can draw the timing
MOV DATPTR, #ADRTAB ; 4 chart diagram for the driver signals getting the timing
MOV CNTV, #240 ; 4 chart from Figure 8. Analyzing this diagram, we can
SET FRM ; 4 observe that the evolution in time of the driver signals
JMP RUN2 ; 4
RUN1 NOP ; 4
fits perfectly into the requirements of the technical
RESET LOAD ; 4 specifications and the period of the signals
NOP ; 4 respectively the frame frequency are:
NOP ; 4
RESET FRM ; 4 TCP = 150 + 250 = 400ns (duty cycle: 3/8)
NOP ; 4
RUN2 NOP ; 4
JMP RUNLCD ; 4 TLOAD = 119*(150+250) + 1*(150+850) = 48,6 uS

Fig. 6 LCD driver assembly routine TFRM = TLOAD * 240 = 11.664 mS

In the observation area of the program listing, was FFRM = 1/ TFRM = 85,7 Hz
highlighted the instruction cycle time in number of
system clock cycles (1 cycle =12.5nS). Supplementary Frame rate of approx. 86 Hz falls into the optimum
NOP instructions complete the program in order to zone of the technical characteristics features
obtain the necessary timing for compliance with the recommended by Kyocera.
switching characteristics of the LCD driver. If we Also, we can see that if a NOP instruction is inserted
analyze the duration of the instructions in the inner between ADD DATPTR,#1 and RESET CP
loop of the routine, we get the feature in Figure 7., instructions, the TCP duty cycle becomes ½, without
which is the time evolution of the instructions changing the frame frequency.
 t
[50nS]

200 48400 nS 200

LOAD 240 1

150 48600 nS

FRM

200 150 250 150 47050 nS 150 850 nS 150 250 150

CP 1 2 120 1 2
100 100 100 100 100

D 0-7

Fig. 8 Timing chart for generated driver signals

5.TOUCH SCREEN INTERFACE by implementing the firmware in P8X32A, and by

using the Serial and I/O ports of D/I to communicate
The I/D contains a touch controller, type TSC-10 with the process. Thus, using the D/I is simply the
that interfaces to a 4-wire resistive touchscreen. The quickest way to generate a user interface, making it a
touch sensitive transparent screen mounted in front of genuine Graphical User Interface for embedded
the LCD, provides a way for a person to interact with systems.
the system. The touch causes an analog signal which
is converted by the controller into 10bit screen
coordinates which are sent to the Propeller chip in
9600bps, RS232 serial format.
Interpretation of the data and answers to them are
handled by a routine implemented in a Cog in the
Propeller chip, which runs independently of the LCD
driver signals generation routine.

6. CONCLUSIONS

Using P8X32A microcontroller, allowed, besides

high-speed processing for the fast interface signals,
also a small physical footprint, minimizing the PCB,
as shown in Figure 9. The D/I PCB are fitted exactly
under the LCD body, in the conditions in which the
power supply voltage stabilizers and the inverter for Fig. 9 D/I Board PCB
generating high voltage for LCD backlight were
placed on the same PCB. USB port is provided, so REFERENCES
that a PC can download new bitmaps and firmware
[1] Propeller Manual, P8X32A Datasheet, Parallax Inc.
without having to be disconnected from the embedded
Rev. 1.1, Complete text 2008
system. [2] KCG057QV SNT 5.7" LCD Datasheet, Kyocera Co.
Although D/I acts as a smart terminal and is Hayato LCD Division, Rev 2.1/2006
generally connected to an embedded processor that [3] TCP-10 Datasheet, DMC Co. Ltd., 2005 Rev. 3088
implements the desired graphical user interface by [4] CXA-L0612A Datasheet, TDC Co., 2005
issuing commands to the D/I, it is possible to use [5] Chip Gracey, Why the Propeller works?", Parallax Inc.,
D/I as an embedded processor in a limited way, Propeller Articles, Feb.2007