Prof. R.K.

Chauhan (MMMUT-Gorakhpur)

LAYOUT
Layout-design describes how small feature device can be integrated and how closely they can
be packed in a particular manufacturing process. Popularly there are two methods to describe
any layout design
(a) Micron
(b) λ-Based design rule
In λ-based design rule λ is actually the resolution of process. It is generally half of the minimum
drawn transistor channel length. This is also the minimum width of a polysilicon wire.
Designers often describe a process by its feature size. Feature size refers to minimum channel
length, so λ is half the feature size.
Layout Rules:
 Metal and diffusion have minimum width and spacing of 4λ as shown in Fig.1
 Contacts are 2λ by 2λ and must be surrounded by 1λ on the layers above and below
(Fig.1)
 Polysilicon uses a width of 2λ (Fig.1)
 Polysilicon overlaps diffusion by 2λ where a transistor is desired and has a spacing of
1λ away where no transistor is desired (Fig.1).
 Polysilicon and contacts have spacing of 3λ from other polysilicon or contacts.
 n-well surrounds pOS transistor by 6λ and avoid nMOS transistor by 6λ.
Transistors dimensions are usually defined in terms of Width to length (W/L) ratio. In Fig. 2a
the transistor W/L ratios is defined as 4:2. For 0.18 micron technology the dimension of λ =
0.18 μm and therefore the channel length is 0.36 μm and width is 0.72 μm. It can be seen that
the spacing between two transistor i.e. nMOS and pMOS is 12λ. Fig.2b shows pMOS transistor
of W/L ratio as 8:2, where as the W/L ratio of nMOS transistor is 4:2.
Diffusion
Metal n p Polysilicon

Spacing
width

4λ 4λ
3λ

4λ 4λ 4λ 2λ 2λ
λ

2λ

2λ 3λ
Metal-Diffusion
Metal-Polysilicon contact
contact
Fig.1 λ-based design rule

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Prof. R.K. Chauhan (MMMUT-Gorakhpur)

2λ

pMOS

W/L = 8/2 8λ
4λ

4λ 12λ

W/L = 4/2 4λ

nMOS

Fig.2a Spacing between nMOS (4/2)

& pMOS transistor (4/2) Fig.2b. 8:2 pMOS
And 4:2 nMOS
Area Estimation:
Stick diagrams can easily be drawn compared to complete layout of any circuits because they
do not need to be drawn to scale. But, with the practice it is easy to estimate the area of a layout
from the corresponding stick diagram. Layout area is usually determined by the metal wires.
Transistors are small widths that fit under the wires. Wires having a width of 4λ and spacing
of 4λ to the next wire, the track pitch are in all 8λ. This pitch also leaves room for a transistor
to be placed between the wires. Therefore, as a thumb rule, it is reasonable to estimate the
height and width of a cell by counting the number of metal tracks and multiply by 8λ. The
spacing required between two transistors(nMOS and pMOS) is 12λ i.e. because of the well
used. This spacing could be utilized for additional track whether wire is needed or not. Fig.2b
shows layout of a three input CMOS NAND gate. The area required for a cell of three input
NAND gate is 40λ by 32λ.

VDD 6λ VDD

8λ

8λ 8λ
8λ 8λ
12λ

8λ

GND 6λ GND
Fig2. Standard layout of (a) CMOS Inverter (b) Three input CMOS NAND gate

Q1. Draw the layout of CMOS inverter in which the W/L ratio of pMOS is 8/2 and nMOS is
4/2.
Sol:

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Prof. R.K. Chauhan (MMMUT-Gorakhpur)

2λ

8λ
8/2
A Y
A Y 4/2

4λ

 
Q2. Implement the function F, F   A  B  C   D , by CMOS gates and estimate the area
required from its layout.
VDD

6 Tracks = 48λ

8λ 8λ
GND
5 tracks of 8λ each = 40
λ
Fig. 4. Implementation of function
Q3. Sketch stick diagram of a 4-input CMOS NOR gate and draw its layout. Calculate the
gate area.
Sol.

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Prof. R.K. Chauhan (MMMUT-Gorakhpur)

VDD

(a)

(c)

Fig. (a) Circuit of CMOS NOR gate

(b) (b) Its Stick diagram (c) Layout
The minimum area is 5 tracks by 5 tracks (40 λ x 40 λ = 1600 λ2).

Q4. Consider the design of a CMOS compound OR-AND-INVERT gate computing

F  A  B  C
(a) sketch transistor level schematic
(b) sketch stick diagram
(c) sketch layout and estimate the area
Sol.4
VDD

(c)
Fig.: (a) CMOS circuit implementation of
(b) Stick diagram (c) Its layout representation

Estimated Area is 4 by 6 tracks = 32 λ x 48 λ = 1536 λ2.