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Analog IC Design- Lab Manual

The document outlines a series of experiments focused on NMOS characteristics and designs using EDA tools, including tasks related to amplifier, inverter, and ring oscillator designs. Each task includes specific design parameters, simulation instructions, and expected outputs for analysis. The experiments utilize AMI Semiconductor's C5 process and involve plotting various characteristics based on different transistor dimensions and configurations.

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pandiammalkrp
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© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
13 views

Analog IC Design- Lab Manual

The document outlines a series of experiments focused on NMOS characteristics and designs using EDA tools, including tasks related to amplifier, inverter, and ring oscillator designs. Each task includes specific design parameters, simulation instructions, and expected outputs for analysis. The experiments utilize AMI Semiconductor's C5 process and involve plotting various characteristics based on different transistor dimensions and configurations.

Uploaded by

pandiammalkrp
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 27

Index

SI.No Exp.date Name of the Experiment Page No

1. TASK 1: CHARACTERISTICS OF NMOS

TASK 2: CHARACTERISTICS OF NMOS WITH


2.
EDA TOOL

3. TASK 3:AMPLIFIER DESIGN WITH EDA TOOL

4. TASK 4:INVERTER DESIGN WITH EDA TOOL

TASK 5: RING OSCILLATOR DESIGN WITH EDA


5.
TOOL

iii
EX.NO:1 CHARACTERISTICS OF NMOS

DATE :

The transistor dimension and the model parameters of a NMOS transistor is given as; width W = 20 μm, length
L = 2 μm, transconductance Kp = 60μA/V2, threshold voltage Vto = 0.6 V, channel length modulation parameter
 = 0.2 V−1, body effect coefficient  = 0.8√𝑉 and the surface potential parameter|2F| = 0.8 V. Analyze the
characteristics of the NMOS by performing the following simulations.

DESIGN:

1) Determine the bias current ID and the small-signal parameters gm, gmb and gds for the bias point of VGS = 1.5
V and VDS = 2.0 V.

4
2) Plot the input characteristics ID vs VGS for varying VDS
(In DC sweep have VGS as the first source and VDS as the second source )
5
.dc VGS 0 5 0.01 VDS 0 5 1

3) Plot the output characteristics ID vs VDS for varying VGS


In DC sweep have VDS as the first source and VGS as the second source )
.dc VDS 0 5 0.01 VGS 0 5 1

6
4) Plot the variation of drain current ID for channel width W = 10m, 20m and 30m with L = 2m

.model NMOS-TASK1 NMOS( Kp=60u


+ Vto=0.6 Lambda =0.2 Gamma =0.8 Phi= 0.8 )
.param L 2u
.step param W 10u 30u 10u
.dc VDS 0 5 0.01

.op

7
8
5) Plot the variation of drain current ID for channel length L = 1m, 3m and 5m, with W = 30m

.model NMOS-TASK1 NMOS( Kp=60u


+ Vto=0.6 Lambda =0.2 Gamma =0.8 Phi= 0.8 )
.step param L 1u 5u 2u
.param W 30u
.dc VDS 0 5 0.01

.op

9
EX.NO:2 CHARACTERISTICS OF NMOS USING EDA TOOL

DATE :

Design a NMOS Device with W/L ratio 10 and 300nm AMI Semiconductor's C5 Process and analyze its I/V
characteristics using EDA Tool.
A. Schematic design and simulation of NMOS Using EDA Tool.
DESIGN:

DC Operating Point

10
11
12
Input characteristics ID vs VGS for varying VDS
(In DC sweep have Vgs as the first source and Vds as the second source)
.dc Vgs 0 5 0.01 Vds 0 5 1

Output characteristics ID vs VDS for varying VGS


(In DC sweep have Vgs as the first source and Vds as the second source)
.dc Vds 0 5 0.01 Vgs 0 5 1

13
B. Layout design and simulation of NMOS Using Electric EDA Tool.
DESIGN:

DC Operating Point

14
15
Input characteristics ID vs VGS for varying VDS
(In DC sweep have Vgs as the first source and Vds as the second source)
.dc Vgs 0 5 0.01 Vds 0 5 1

Output characteristics ID vs VDS for varying VGS


(In DC sweep have Vgs as the first source and Vds as the second source)
.dc Vds 0 5 0.01 Vgs 0 5 1

16
EX.NO:3 AMPLIFIER DESIGN WITH EDA TOOL

DATE :

Design of Common Source Amplifier with W/L ratio 10 using 300nm AMI Semiconductor's C5 Process
using EDA Tool.
A. Schematic design and simulation.
DESIGN:

17
Transient Analysis

18
Frequency Response

B. Layout design and simulation.


DESIGN:

19
Transient Analysis

20
Frequency Response

21
EX.NO:4 INVERTER DESIGN WITH EDA TOOL

DATE :

Design of Inverter using 300nm AMI Semiconductor's C5 Process using EDA Tool.
A. Schematic design and simulation.
DESIGN:

22
Transient Analysis

Input

23
Output

B. Layout design and simulation.


DESIGN:

24
Transient Analysis

Input

25
Output

26
EX.NO:5 RING OSCILLATOR DESIGN WITH EDA TOOL

DATE :

Design of Ring Oscillator using 300nm AMI Semiconductor's C5 Process using EDA Tool.
A. Schematic design and simulation.

Inverter Icon Design

27
Ring Oscillator Schematic Design

Output

28
29

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