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VLSI arch

The document outlines two tests for the EE5016 and EE3516 courses at IIT Palakkad, focusing on VLSI architectures for signal processing and machine learning. Test 1 includes questions on designing VLSI architectures, implementing acknowledgment signals, fine-grain pipelining, and explaining circuit diagrams. Test 2 covers IIR filters, critical path calculations, retiming techniques, and performance analysis of signal processing structures.

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6 views

VLSI arch

The document outlines two tests for the EE5016 and EE3516 courses at IIT Palakkad, focusing on VLSI architectures for signal processing and machine learning. Test 1 includes questions on designing VLSI architectures, implementing acknowledgment signals, fine-grain pipelining, and explaining circuit diagrams. Test 2 covers IIR filters, critical path calculations, retiming techniques, and performance analysis of signal processing structures.

Uploaded by

threecounted03
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Departmnent of Electrical Engineering, IIT Palakkad

EE5016: VLSIArchitectures for Signal Processing and Machine Learning, Test 1


Time-: 12- 1PM Max Mau ks: 20 Date: 23-02-2023

Instructions:
i) Answer all questions. Each question carries nnarks stated against it.
[ij Students are suggested to maintain the sequence of answers.

1. Desigu a suitable VLSI architecture to produce a fron the given inputs a and z, both are are positive integers.
Take the data qualifiers to be operands_valid and outyut_valid at the input and output respectively. Output nas
to wait tillit gets the acknowledgement from the next module. Assume that a multiplier is given and ignore the
bit width growth. Clearly mark the data path, control path, status signals and control signals. (5 marks)

2. tionality?
Can you suggest minor modifications to the designed architeceture in Question 1to inplement the following func
(5 marks)
(a) acknowledgement
Add one more input signal to the design called ack mode. If the ack mode is 1the output has to wait for the
signal from the next module.
(b) If the ack_mode is 0 the output need not wait for the acknowledgement signal. output_valid will be asserted
only for one clock cycle and goes back to idle state.
3. Assuming that the propagation delay of a &-bit ripple carry adder is Trca, Carry out fine grain pipelining to reduce
it to approximately Trca/2. Clearly show the added pipelined registers (5 marks)
4. Briefy explain the following with the help of a circuit diagram (5 marks)
(a) 4-bit Incrementer
(b) Bar1ei Siifter to right shift the given 8-bit number by i positions. Assume i to be 2-bit.
CIence and n

Department of Elcctrical
EE3516: VLSI Architectures for Signal Engincering. and
IIT Palakkad
Time-: 12 - 1 PM
Processing Machine Learning, Test 2
Max Marks-: 30 Datc: 23-03-2023

Instructions:
i Answer all qucstions. Each
qucstion carrics narks stated against it.
iil Students are suggcsted to maintain the
sequcncc of answers.

1. Consider the IIR flter shown in the following fgure.


Assume that the multiplication operation takes 2 nsec and
the addition operation takes 1 nsec. Draw the DFG of the filter and
calculate the critical path. Pipeline the DFG
by placing registers at appropriate fccd forward cutscts to reducc the critical path to
3 nscc. (10 marks)

x(n)

M1

DD
M, ) M M,
y{n)

Figure J: Problem 1

2. Assuning that thecomputation timne of nodes A, B, C, D is l nsec cach and that of E, F is 2 nscc cach, Find out
the iteration bound and critical path of the following design. Apply retiming to make the critical path equal to the
iteration bound. Can you suggest a suitable technique to reduce the iteration bound to half of its current value?
Then apply retiming to reduce the critical path to iteration bound (10 marks)

D E

Figure 2: Problem 2

1
3. Constdr the sgnal
procssing stueture showu iu the followiug fheure. Find out thc
structur using retiming.
the strutures. (10 Cloarly show all thc cutscts and steps. cquivaleut data
Comment on the arca and performancebroadcast
marks) of both

-D -D -D

y(n)

b DA
-D -D -D -D
Figure 3: Problem 3

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