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The document details an experiment on designing a CMOS inverter using 180nm technology, focusing on achieving equal rise and fall times by adjusting PMOS and NMOS dimensions. It includes simulation results for transition times, propagation delays, and the construction of a 7-stage ring oscillator and a clock driver with a fanout of 64. The findings demonstrate successful implementation of the inverter and its applications in digital circuits with theoretical and practical observations on delays.

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Pranav Sai Theja Kota
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4 views

Report-1(Cadence)

The document details an experiment on designing a CMOS inverter using 180nm technology, focusing on achieving equal rise and fall times by adjusting PMOS and NMOS dimensions. It includes simulation results for transition times, propagation delays, and the construction of a 7-stage ring oscillator and a clock driver with a fanout of 64. The findings demonstrate successful implementation of the inverter and its applications in digital circuits with theoretical and practical observations on delays.

Uploaded by

Pranav Sai Theja Kota
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
You are on page 1/ 17

VLSI LABORATORY(EC39004)

EXPERIMENT-5

V.Ruchitha-22EC10085

K.Thiru Vardhan-22EC30031
​ ​ ​ ​
​ ​ ​ ​ ​ GROUP NO.:61

​ ​ ​ ​ DATE OF SUBMISSION:13-03-2025
a) Design a CMOS Inverter with equal rise and fall time in 180nm
CMOS technology.

CIRCUIT DIAGRAM:

SIMULATION PARAMETERS:

●​ W,L of PMOS W=2.45µm,L=0.18µm


●​ W,L of NMOS W=1µm,L=0.18µm
●​ Simulated CMOS inverter with square pulse of amplitude
1.8V,time period of 10µs,rise and fall time of 100ns and
Vdd=1.8V.

1
Design:

​ As we know the rise time is determined by how quickly the


PMOS transistor can pull the output voltage up to Vdd.A higher Kp
relative to Kn would generally result in faster rise times because it
indicates a more efficient PMOS transistor.Similarly,fall time is
determined by how quickly the NMOS transistor can pull the output
voltage down to GND.A higher Kn relative to Kp results in faster fall
time.Kp and Kn are related to the mobility of charge carriers in PMOS
and NMOS transistors.In NMOS majority charge carriers are electrons
which have higher mobility compared to holes which are majority
carriers of PMOS transistor which makes NMOS faster than PMOS for
equal dimensions of NMOS and PMOS.

​ However,Kp and Kn cannot be equal in common but it can be


achieved by adjusting the transistor widths which would result in
equal rise and fall time. In this circuit we have found the graphs for
both NMOS and PMOS Id vs Vgs and by keeping Id some constant we
took both the Vgs values and by equating the current values in Id
equation we found the relation between Kp and Kn .When we did this
we got that Kp is nearly 2-3 times that of the Kn value.So,in that way
we designed the CMOS inverter for equal rise time and fall time.

Results:

By adjusting the dimensions of PMOS and NMOS,finding the 10%


value of the Vdd and 90% value of Vdd we calculated the rise time to
be 15.3681ns and fall time to be 16.03ns which are nearly same as
shown in the below figure.Also propagation delay is also found as
shown in next pictures from which tpdL-H=6.936ns and
tpdH-L=9.23ns.So,tpd(average of tpdL-H and tpdH-L)=8.083ns.

2
Id vs Vgs for NMOS :

-Id vs Vgs for PMOS:

3
VTC of CMOS Inverter:

●​ Switching threshold is marked in above diagram(Vout=Vin).

Rise and Fall times of CMOS inverter:

4
TpdL-H:(50% input to 50%output time difference)

TpdH-L:

5
Complete Tpd diagram:

b) Simulate and observe transition time and delay(with fanout of 4)


of the designed inverter.

CIRCUIT DIAGRAM:

6
SIMULATION PARAMETERS:

●​ W,L of PMOS1 W=3.45µm,L=0.18µm


●​ W,L of NMOS1 W=1µm,L=0.18µm
●​ W,L of PMOS2 W=13.8µm(4*3.45),L=0.18µm
●​ W,L of NMOS2 W=4µm(4*1),L=0.18µm
●​ Simulated CMOS inverter with square pulse of amplitude
1.8V,time period of 10µs,rise and fall time of 100ns and
Vdd=1.8V.

Design:

​ In the question it is mentioned that we need to make a load of


fanout 4.For this,the NMOS and PMOS are made of width 4 times that
of the width of the original NMOS and PMOS so that the fanout 4
condition is met.This could also be done by connecting four CMOS
inverters of same length and width for the fanout of 4 in parallel at
the output side.By making such necessary changes,then we realized
the rise time,fall time and the propagational delay of the circuit.

Results:

By adjusting the dimensions of PMOS and NMOS,finding the 10%


value of the Vdd and 90% value of Vdd we calculated the rise time to
be 9.007ns and fall time to be 9.09ns which are nearly same as shown
in the below figure.Also propagation delay is also found as shown in
next pictures from which tpdL-H=0.317ns and
tpdH-L=2.369ns.So,tpd(average of tpdL-H and tpdH-L)=1.343ns.First
two TpdL-H and TpdH-L are for the circuit diagram shown.The next
diagrams are for the load of CMOS inverters in parallel (4 inverters).

7
TpdL-H:

8
TpdH-L:

9
c) Construct a 7-stage ring oscillation using the inverter and observe
the oscillations per period of the circuit.

CIRCUIT DIAGRAM:

10
Design:

​ In this part,we need to create a ring oscillator of 7-stages.So for


this 7 CMOS inverters are connected in series,and a feedback is given
from the last CMOS inverter to the first inverter and we observed
whether the feedback output is coming out to be a clock with 0 and 1
transitions and also observed the respective time delay for the entire
circuit which should be like if the single CMOS time delay is t0 then
the entire time delay should be nearly 2*N*t0 where N is the number
of stages(here N=7).

11
Here the propagational delay is nearly 100 and from theoretical
observation also,the value of the propagational delay is 14 times that
of the single CMOS which is like 14*8 nearly 112.In our circuit
design,the output is working as a clock with alternate 0s and 1s (high
and low) and also the delay is accurately 14 times by which our
requirement is met.

c) Design a clock driver of fanout of 64.

CIRCUIT DIAGRAM:

12
Design:

​ In this circuit diagram,for a fanout of 4 we have chosen 4 stages


excluding the source and the load.Considering the input capacitance
as C and the load capacitance as 64C then as we are considering it to
be 4 stages,F=64 and each fanout should be f=(F)^(1/N) where here
N=4 so f=(8)^0.5.As we go on increasing the widths by this factor the
software holds a limit of the width of 100µm so we have chosen the
value of source CMOS only in such a manner to meet our
requirement.As we are using even number of stages the input and
output should alike as shown in the below diagram.

13
Here the propagation delay should be N*t0(1+f) since we are
considering the minimum propagation delay circuit with the
inverters sized in a geometric progression.

14
DISCUSSION-1(V.RUCHITHA-22EC10085)

​ In this experiment we have basically implemented a CMOS


inverter normally and also created a symbol for the basic CMOS. By
creating this symbol,it makes it easier because usage of this basic
CMOS is quite simpler than creating many number of CMOS
inverters.In part a,we have just found the relation between Kp and
Kn by just creating a NMOS and PMOS separately by diode connected
circuits such that we could find the graph between Id and Vgs so that
by fixing a particular value of current we found both Vgs values for
NMOS and PMOS and then in the current equation of the saturation
region we found the relation between Kp and Kn which was found
out to nearly 2-3 times of Kn.And by increasing the load in part b,we
found out the transition and propagation delays.

​ For part c,we found that a clock can be created by just using
some feedback circuit with many number of inverters which has the
propagation delay of 2*N*t0 and also proved that the value of
propagational delay is nearly the same as that of what is
required.Fanout refers to the number of logic gates or loads that a
single logic gate can drive without significant degradation in its
output signal quality.It measures how many inputs a gate can supply
with its output before the signal becomes too weak or distorted.For
part d,we have constructed a CMOS inverter fanout of 64 using 4
inverters by some sizing factors.From this circuit,we got that the
output of the circuit is similar to that of the input due to the even
number of inputs and the propagational delay is also matched with
that of the theoretical delay to be achieved using formula N*t0(1+f).

15
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