ECT 304: VLSI Circuit Design

Module 4: Arithmetic circuits

Adders: Static adder, Carry-Bypass adder,
Linear Carry- Select adder, Square- root
carry- select adder. Multipliers: Array
multiplier.

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 Adders

❖ Addition is the most commonly used arithmetic operation.

❖ It often is the speed-limiting element as well.
❖ Optimisation of the adders is required.
❖ Optimisation can be done at logic or circuit levels.
❖ Logic-level optimisation try to rearrange the Boolean equations,
so that a faster or smaller circuit is obtained.
❖ Circuit optimisation manipulates transistor sizes and circuit
topology to optimize the speed.

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 Full Adder
A full adder can be represented as:
Truth Table:
Input Output
A B Ci S Co
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

S = A B C Co = AB + BCi + ACi
S = AB Ci + A BCi + A B Ci + ABCi 3
 Static Adder
❖ To implement a full-adder circuit, some logic manipulations are
done to reduce the transistor count.
❖ It is advantageous to share some logic between the sum and carry
generation sub-circuits, if this does not slow down the carry
generation.
❖ The sum and carry term of the full-adder can be reorganised as:
Co = AB + Ci ( A + B)
S = ABCi + Co ( A + B + Ci )
❖ Using above equations 28 transistors are only needed for the
implementation of a full-adder.
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Static Adder

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 Ripple Carry Adder (RCA)
• It is called as ripple-carry adder, as the carry bit ‘ripples’ from one
stage to the other.

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 Ripple Carry Adder (RCA)
❖ The propagation delay of ripple-carry adder (also called the
critical path delay) is defined as the worst case delay over all
possible input patterns.
❖ For RCA, the worst case delay happens when a carry generated at
the least significant bit (LSB) position propagates all the way to
the most significant bit (MSB) position.
❖ This carry is used in the last stage to produce the sum.
❖ The delay is then proportional to number bits in the input words
‘N ’ and is approximated by, t adder  ( N − 1)tcarry + t sum
❖ where, tcarry and t sum are the propagation delay of carry and sum.
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Full Adder

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 Full Adder
❖ Here we have some intermediate signals G (generate), D (delete),
and P (propagate).
❖ G =1 (D =1) ensures that a carry bit will be generated (deleted) at
Co independent of Ci, while P = 1, guarantees that an incoming
carry will propagate to Co.
G = AB
D = AB
P = A  B( sometimes, A + B)
❖ So Sum and Carry out can be represented in terms of above
equations:

Co (G, P) = G + PCi S (G, P) = P  Ci

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 Carry-Bypass (Skip) Adder
❖ Consider a four-bit adder block:

❖ Suppose that the values of Ak and Bk (k = 0,1,2,3) are such that all
propagate signals Pk (k = 0,1,2,3) are high.
❖ An incoming carry Ci,0 = 1, propagate under those conditions
through the complete adder chain and causes an outgoing carry,
Co,3 = 1.
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 Carry-Bypass (Skip) Adder
❖ If (P0P1P2P3 = 1), then Co,3 = Ci,0 . Else either DELETE or
GENERATE occurred.
❖ This can be used to speed up the operation of adders as below:

❖ When BP = P0P1P2P3 = 1, the incoming carry is forwarded

immediately to the next block through the bypass transistor, hence
the name carry-bypass adder or carry skip adder. 11
 Carry-Bypass (Skip) Adder
❖ Consider a N – bit carry-bypass adder (N = 16). Let the total
adder is divided in (N/M) equal-length bypass stages, each of
which contains M bits. (M =4)

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 Carry-Bypass (Skip) Adder
❖ Total propagation time tp, is given as:
N 
t p = t setup + M .tcarry + − 1tbypass + ( M − 1)tcarry + t sum
M 
❖ t setup is the fixed overhead time to create the generate and
propagate signals.
❖t carry is the propagation delay through a single bit.
❖ tbypass is the propagation delay through the bypass multiplexer of
a single stage.
❖ t sum is the time to generate the sum of the final stage.

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 Carry-Bypass (Skip) Adder
❖ In the worst-case, the carry is generated at the first bit position,
ripples through the first block, skips around (N/M -2) bypass
stages, and is consumed at the last bit position without generating
an output carry.
❖ The optimal number of bits per skip block is determined by
technological parameters such as the extra delay of the bypass-
selecting multiplexer, the buffering requirements in the carry
chain, and the ratio of the delay through the ripple and the bypass
paths.

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 Carry-Bypass (Skip) Adder
❖ In the worst-case, the carry is generated at the first bit position,
ripples through the first block, skips around (N/M -2) bypass
stages, and is consumed at the last bit position without generating
an output carry.
❖ The optimal number of bits per skip block is determined by
technological parameters such as the extra delay of the bypass-
selecting multiplexer, the buffering requirements in the carry
chain, and the ratio of the delay through the ripple and the bypass
paths.

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 Carry-Bypass (Skip) Adder
❖ Propagation delay of carry-skip adder Vs number of bits can be
plotted as:

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 Linear Carry-Select Adder

❖ In a ripple-carry adder, every full-adder cell has to wait for the

incoming carry before an outgoing carry can be generated.
❖ One way to get around this linear dependency is to anticipate both
possible value of the carry input and evaluate the result for both
possibilities in advance.
❖ Once the real value of the incoming carry is known, the correct
result is easily selected with a simple multiplexer stage.
❖ This implementation is called carry-select adder.

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 Linear Carry-Select Adder
Bit 0 - 3

Setup
P,G
0 0 - Carry Propagation

1 1 - Carry Propagation

C0,k-1 Multiplexer C0,k+3

Sum Generator

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 Linear Carry-Select Adder
❖ Consider the block of adders, which is adding bit k to k+3.
❖ Instead of waiting for on the arrival of the output carry of bit k-1,
both the 0 and 1 possibilities are analysed. i.e., two carry paths are
implemented.
❖ When C0,k-1 finally settles, either the result of the 0 or the 1 path is
selected by the multiplexer, which can be performed with a
minimal delay.
❖ Here the hardware overhead of the carry-select adder equals about
30% with respect to a ripple carry structure.

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 Linear Carry-Select Adder
• A full carry select-adder can be constructed by chaining a number
a number of equal-length adder stages.

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 Linear Carry-Select Adder
❖ Worst case propagation delay is:
N 
t add = t setup + M .tcarry + t mux + t sum
M 
❖ Where t setup, tsum , t mux are fixed delays and N and M represents
the total number of bits, and the number of bit per stage,
respectively. tcarry is the delay of the carry through a single full-
adder cell.
❖ The carry through a single block is proportional to the length of
that stage or equals M. tcarry.

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 Linear Carry-Select Adder
❖ The propagation delay of the adder is again, linearly proportional
to N.
❖ The reason for this linear behaviour is that the block-select signal
that selects between the 0 and 1 solutions still has to ripple
through all stages in the worst case.

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Linear Carry-Select Adder

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 Square-Root Carry-Select Adder
❖ Consider the multiplexer gate in the last adder stage (16 bit carry
select adder).
❖ The inputs to this multiplexer are the two carry chains of the
blocks and block-multiplexer signal from the previous stage.
❖ A major mismatch between the arrival times of the signals can be
observed.
❖ The results of the carry chains of the blocks are stable before the
multiplexer signal arrives.
❖ It makes sense to equalise the delay through both paths.

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 Square-Root Carry-Select Adder
❖ This can be achieved by adding more bits of the subsequent stages
in the adder, requiring more time for the generation of the carry
signals.
❖ For e.g., the first stage can add 2-bits, the second contains 3, the
third has 4, and so forth.
❖ This topology is faster than the linear organisation, even though an
extra stage is needed.

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Square-Root Carry-Select Adder

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 Square-Root Carry-Select Adder
❖ If an N-bit adder contains P stages, and the first stage adds M bits.
❖ An additional bit is added to each subsequent stage.
❖ Then, N = M + (M+1) + (M+2) + (M+3) + …….+ (M+P-1)
P ( P − 1) P2 1
❖ = MP + = + P( M − )
2 2 2
❖ If M << N (e.g., M = 2 and N = 64), the first sum term dominates
P2
and can be written as N  or P  2 N
2
❖ Thus the worst case delay is:
t add = t setup + M .tcarry + ( )
2 N .t mux + t sum

❖ The delay is proportional to N for large adders (N >> M).

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Delay Comparison of Carry-Select Adders

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 Multiplier
❖ Multiplications are expensive and slow operations.
❖ The performance of many computational problems often is
dominated by the speed at which a multiplication operation can be
executed.
❖ Multipliers are complex array adders.
❖ Consider two unsigned binary numbers X and Y, that are M and N
bit wide respectively.
❖ X and Y can be expressed in binary as:
M −1 N −1
X =  Xi 2 i
Y = Yj 2 j withX i , Y j  {0,1}
❖ i =0 i =0
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 Multiplier
• The multiplication operation is then defined as:
M + N −1
Z = X Y =  k
Z 2
k =0
k

 M −1 i 
N −1
j  
M −1 N −1
i+ j 
=   X i 2   Y j 2  =    X iY j 2 
 i =0  i =0  i =0  i =0 
• Simplest way to perform multiplication is by using shift and add
algorithm, for multiplication adds together M partial products.
• Each partial product is generated by multiplying the multiplicand
with a bit of multiplier.
• All partial products are generated at the same time and organised
in an array.
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 Multiplier
• A multiplicand addition is applied to compute the final product.

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 Multiplier
❖ The above operations can be mapped directly into hardware.
❖ The resulting structure is called an array multiplier and combines
partial-product generation, partial-product accumulation and
final addition.
❖ Partial Product Generation:
❖ Partial products results from logical AND of multiplicand X with
a multiplier bit Yi. Each row in the partial product array is either a
copy of the multiplicand or a row of zero’s.

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 Multiplier
• Partial Product Generation:

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 Multiplier
❖ Partial Product Accumulation:
❖ After the partial products are generated, they must be summed.
❖ This accumulation is essentially a multi-operand addition.
❖ One method to accumulate partial products is by using a number
of adders, that will form an array – hence the name array
multiplier.

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 Multiplier
❖ Final Addition:
❖ The final step for completing the multiplication is to combine the
result in the final adders.
❖ The choice of adder style depends on the structure of
accumulation array.
❖ A carry look ahead adder is the preferable option if all input bits to
the adder arrive at the same time, as it have the smallest possible
delay.

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 Array Multiplier
• 4x4 bit multiplication:
X3 X2 X1 X0

Y3 Y2 Y1 Y0

X3Y0 X2Y0 X1Y0 X0Y0

+ + +
X3Y1 X2Y1 X1Y1 X0Y1
+ + +
X3Y2 X2Y2 X1Y2 X0Y2
+ + +
X3Y3 X2Y3 X1Y3 X0Y3

P7 P6 P5 P4 P3 P2 P1 P0

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 Array Multiplier
• 4x4 bit multiplication:
X3Y0 X2Y0 X1Y0 X0Y0
X3Y1 X2Y1 X1Y1 X0Y1
S3 S2 S1

X3Y2 X2Y2 X1Y2 X0Y2

S6 S5 S4
X3Y3 X2Y3 X1Y3 X0Y3

P7 P6 P5 P4 P3 P2 P1 P0

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Array Multiplier

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 Array Multiplier
❖ For an MxN array multiplier, it needs :
❖ MxN - 2-bitAND gates
❖ N – Half adders
❖ (M-2)N – Full adders
❖ Total (M-1)N adders
❖ The adders are arranged in a carry saw chain, the carry-out are fed
to the next available adder in the column to the left.
❖ The array multiplier accepts all of the input simultaneously.
❖ The longest delay in the calculation of the product bits depends on
the speed of adders.
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 Array Multiplier
❖ Partial adders are implemented as ripple-carry structures.
❖ Two of the critical paths for the multiplier are shown as:

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 Array Multiplier
❖ Approximate expression for the propagation delay for critical path
2 is, t mult  [( M − 1) + ( N − 2)]tcarry + ( N − 1)t sum + t and
❖tcarry is the propagation delay between input and output carry.
❖ t sum is the delay between the input carry and sum bit of the full
adder
❖ t and is the delay of the AND gate

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