Lecture Notes: Buses and Bus Architecture

1. Introduction to Buses in Computer Architecture

A bus is a communication system that transfers data between components inside a computer
or between computers. It allows different parts of a computer to communicate with each other
and share data.

Key Functions of a Bus:

 Data Transfer: Moves data between components.

 Addressing: Specifies where data should be read from or written to.
 Control: Manages the flow of data and timing of operations.

2. Bus Architecture

Bus Architecture refers to the design and organization of the bus system within a computer.
It determines how different parts of the computer are connected and how they communicate.

Components of a Bus Architecture:

i) Data Bus :
Data bus is used for transmitting the data / instruction from CPU to memory/IO and
vice-versa.
 It is bi-directional.
Data Bus Width

 The width of a data bus refers to the number of bits (electrical wires) that the bus can carry
at a time.
 Each line carries 1 bit at a time. So, the number of lines in data bus determine how many
bits can be transferred parallely.
 The width of data bus is an important parameter because it determines how much data can
be transmitted at one time.
 The wider the bus width, faster would be the data flow on the data bus and thus better
would be the system performance.
 Examples-
 A 32-bit bus has thirty two (32) wires and thus can transmit 32 bits of data at a time.
 A 64-bit bus has sixty four (64) wires and thus can transmit 64 bits of data at a time.

ii) Address Bus: Carries the address to/from which data is being transferred.

Example-
When CPU wants to read or write data, it sends the memory read or memory write control signal
on the control bus to perform the memory read or write operation from the main memory and the
address of the memory location is sent on the address bus.
If CPU wants to read data stored at the memory location (address) 4, the CPU send the value 4 in
binary on the address bus.
Address Bus Width
The width of address bus determines the amount of physical memory addressable by the
processor.
 In other words, it determines the size of the memory that the computer can use.
 The wider is the address bus, the more memory a computer will be able to use.
 The addressing capacity of the system can be increased by adding more address lines.
Examples-
 An address bus that consists of 16 wires can convey 216 (= 64K) different addresses.
 An address bus that consists of 32 wires can convey 232 (= 4G) different addresses.

iii) Control Bus: Carries control signals that manage and coordinate the operations of
the system. It is used to transfer the control and timing signals from one component to the other
component. It is bi-directional in nature

 Control signals are generated in the control unit of CPU.

 Timing signals are used to synchronize the memory and I/O operations with a CPU clock.

Bus Lines:

 Data Lines: Used for transmitting actual data.

 Address Lines: Used for specifying the address of the memory location or I/O
device.
 Control Lines: Used for sending control signals such as read/write commands.

Bus Width: The number of lines in the data bus. A wider bus can transfer more data in a
single operation. For example, a 32-bit bus can transfer 4 bytes of data at a time.

Bus Speed: Refers to the rate at which data is transferred over the bus, usually measured in
Hertz (Hz).

3. Types of Buses

Buses can be classified based on their functionality, usage, and the type of data they handle.
3.1 System Bus

The System Bus connects the CPU, memory, and other major components. It is typically
divided into:

 Data Bus: Transfers data between CPU, RAM, and other components.
 Address Bus: Carries the address of the memory location to/from which data is being
transferred.
 Control Bus: Carries control signals such as Read/Write commands, interrupt signals,
and clock signals.

3.2 Expansion Bus

An Expansion Bus allows additional cards or devices to be added to a computer. It provides

a means for expansion beyond the main system bus. Examples include:

 PCI (Peripheral Component Interconnect): A common expansion bus used to

connect peripheral devices.
 PCIe (PCI Express): A high-speed expansion bus with lanes dedicated to each
device, offering faster data transfer rates compared to PCI.
 AGP (Accelerated Graphics Port): A specialized bus designed for graphics cards.

3.3 I/O Bus

The I/O Bus is used to connect external peripherals to the computer. Examples include:

 USB (Universal Serial Bus): A widely used I/O bus for connecting various external
devices.
 SATA (Serial ATA): Used primarily for connecting storage devices such as hard
drives and SSDs.

3.4 Memory Bus

The Memory Bus is dedicated to communication between the CPU and RAM. It includes the
memory controller and handles read/write operations to the system memory.

4. Bus Protocols and Standards

Bus Protocols define the rules and conventions for communication on the bus. Some
important protocols and standards include:

i) Direct Memory Access (DMA)

Direct Memory Access (DMA) is a protocol that allows peripherals to directly access the
system's memory without involving the CPU. This reduces CPU overhead and improves data
transfer efficiency.

Key Features:

 DMA Controller: Manages the transfer of data between memory and peripherals.
  Transfer Modes: Includes burst mode (transferring data in bursts), cycle stealing
(taking control of the bus temporarily), and transparent mode (non-intrusive).
 Advantages: Reduces CPU workload, speeds up data transfers, and allows
simultaneous data transfers.

Use Cases:

 Transferring large blocks of data, such as disk I/O operations.

 Real-time applications where minimizing latency is critical.

ii) I2C (Inter-Integrated Circuit)

I2C is a two-wire protocol used for communication between devices on the same circuit
board. It supports multiple master and slave devices on a single bus.

Key Features:

 Two-Wire Interface: Consists of a serial data line (SDA) and a serial clock line
(SCL).
 Addressing: Uses 7-bit or 10-bit addressing to identify devices on the bus.
 Multi-Master Capability: Multiple masters can control the bus, but only one can
transmit at a time.

Use Cases:

 Sensor interfaces in embedded systems.

 Communication between microcontrollers and peripheral devices.

iii) SPI (Serial Peripheral Interface)

SPI is a high-speed, synchronous serial communication protocol that allows for full-duplex
data transmission. It is widely used for connecting peripherals to microcontrollers.

Key Features:

 Four-Wire Interface: Consists of a clock line (SCK), master output/slave input

(MOSI), master input/slave output (MISO), and a slave select (SS) line.
 Full-Duplex: Allows simultaneous data transmission and reception.
 High-Speed Data Transfer: Faster than I2C due to its synchronous nature and
dedicated lines.

Use Cases:

 Flash memory and EEPROM interfacing.

 High-speed sensors and displays.

iv) PCI (Peripheral Component Interconnect)

PCI is a parallel bus standard for connecting peripheral devices to the CPU. It supports high-
speed data transfers and is used in many computer systems.

Key Features:

 32-Bit and 64-Bit Variants: Supports different data widths.

 Plug and Play: Automatically configures devices without user intervention.
 Bus Mastering: Allows devices to directly access memory, bypassing the CPU.

Use Cases:

 Expansion cards such as network cards, sound cards, and graphics cards.

v) PCI Express (PCIe)

PCI Express (PCIe) is a high-speed, serial expansion bus standard that has largely replaced
PCI. It offers faster data transfer rates and improved scalability.

Key Features:

 Serial Communication: Uses lanes for data transfer, with each lane consisting of two
pairs of wires (one for sending and one for receiving).
 Scalability: Supports different numbers of lanes (x1, x4, x8, x16) for varying levels
of performance.
 Point-to-Point Architecture: Direct connection between devices and the CPU or
chipset.

Use Cases:

 High-performance graphics cards, SSDs, and network cards.

vi) USB (Universal Serial Bus)

USB is a versatile and widely-used protocol for connecting external devices to computers. It
supports a variety of data transfer speeds and device types.

Key Features:

 Different Versions: USB 1.1, 2.0, 3.0, and 3.1/3.2 offer varying speeds (from 12
Mbps to 10 Gbps).
 Plug and Play: Automatically detects and configures devices.
 Hot Swappable: Allows devices to be connected or disconnected without rebooting
the system.

Use Cases:

 Keyboards, mice, printers, external storage, and more.

vii) Thunderbolt
Thunderbolt is a high-speed, serial communication protocol developed by Intel. It combines
data, video, and power into a single connection.

Key Features:

 High Data Transfer Rates: Up to 40 Gbps with Thunderbolt 3 and 4.

 Dual-Protocol: Supports PCIe and DisplayPort protocols.
 Daisy Chaining: Allows multiple devices to be connected in series.

Use Cases:

 High-performance external storage, monitors, and docking stations.

5. Bus Contention

Bus Contention occurs when two or more devices attempt to use the bus simultaneously,
leading to conflicts and reduced performance. Proper arbitration and bus management are
essential to minimize contention.

6. Bus Performance Considerations

Performance Factors:

 Bus Bandwidth: The amount of data that can be transferred per unit of time.
 Latency: The delay between initiating a request and receiving the data.
 Bus Utilization: The percentage of time the bus is actively used.

Optimization Techniques:

 Pipelining: Overlapping the stages of multiple transactions to improve throughput.

 Caching: Storing frequently accessed data to reduce bus traffic.

7. Summary

Understanding buses and their architecture is crucial for designing and optimizing computer
systems. Buses facilitate communication between various components, and their design and
performance can significantly impact the overall efficiency of a computer system.

Key Takeaways:

 Buses are essential for data transfer and communication within a computer.
 Different types of buses serve various purposes, including system, expansion, I/O, and
memory communication.
 Bus architecture and protocols are critical for ensuring efficient and reliable data
transfer.