DATAFLOW MODELLING

Basic Gates
AIM:-
Write verilog HDL codes in dataflow level for basic gates and implement.
OBJECTIVES:-
Upon completion of this experiment the students will be able to
1. To understand continuous assignment using the keyword “assign” in data flow
modeling
PROCEDURE
1. Open Xilinx ISE and create a new project with a project name (eg:-Gates)
2. Create a verilog source file with filename same as module name
3. Write the given program1 on the editor window
4. Select synthesis/Implementation in the drop down list of source window
5. Create source file of test bench waveform with timings as the following information for
the signal in1
♦ Clock High Time: 100 ns.
♦ Clock Low Time: 100 ns.
♦ Input Setup Time: 10 ns.
♦ Output Valid Delay: 10 ns.
♦ Offset: 0 ns.
6. Modify the test bench waveform by click on relevant part of the waves(May use the rescale
timing tab on the testbench menu to change edges and timings) and save it
7. Now select Behavioral simulation from source window after selecting the tbw file in the
process window
8. Double click on simulate behavioral model
9. Observe the output waveforms obtained by simulation and verify truth table
10. Repeat steps 3 to 9 for other programs
PROGRAM
Program 1
// Verilog HDL program in Data flow level for basic Gates

module gate_2(out1i1,i2);

//gate_2 is the module name (it should be same as verilog source file name)

// port declaration
input i1,i2;
output out1;
// Logical expression for out1
assign out1 = i1 & i2;
// assign is the keyword for continuous assignment)
// & is the logical AND operator
endmodule
Program 2
module gate_2(out2,i1,i2);
 Dataflow Modelling

input i1,i2;
output out2;
// Logical expression for out2
assign out2 = i1 | i2;
// assign is the keyword for continuous assignment)
// | is the Logical OR operator
endmodule
Program 3
module gate_2(out3,i1,i2);
input i1,i2;
output out3;
// Logical expression for out3
assign out3 = i1 ^ i2;
// ^ is the logical EXOR operator
endmodule
Program 4
module gate_1(out7,in);
input in;
output out
// Logical expression for out7
assign out7 = in;
Program 5
module gate_1(out8,in);
input in;
output out
// Logical expression for out8
assign out8 = ~in;
// ~ is the logical NOT operator
endmodule
Program 6
module gate_2(out4,out5,i1,i2);
input i1,i2;
output out4;
// Logical expression for out4
assign out4 = ~(i1 & i2);
endmodule
Program 7
module gate_2(out5,i1,i2);
input i1,i2;
output out5;
// Logical expression for out5
assign out5 = ~(i1 | i2);
endmodule
Program 8
module gate_2(out6,i1,i2);
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 Dataflow Modelling

input i1,i2,in;
output out6;
// Logical expression for out6
assign out6 = i1 ^~ i2;
// ^~ is the logical EX NOR operator
endmodule

4 x 1 MULTIPLEXER
AIM:-
Write verilog HDL codes in dataflow level for 4 X 1 Multiplexer
OBJECTIVES:-
Upon completion of this experiment the students will be able to
1. To understand various logical operators
2. To understand conditional operator
PROCEDURE
1. Open Xilinx ISE and create a new project with a project name (eg:-Mux)
2. Create a verilog source file with filename same as module name
3. Write the given program on the editor window
4. Select synthesis/Implementation in the drop down list of source window
5. Create verilog source file of test bench waveform with timings with the following
information for the signal i0
♦ Clock High Time: 20 ns.
♦ Clock Low Time: 20 ns.
♦ Input Setup Time: 0 ns.
♦ Output Valid Delay: 0 ns.
♦ Offset: 0 ns.
6. Modify the test bench waveform by click on relevant part of the waves and save it
7. Now select Behavioral simulation from source window after selecting the tbw file in the
process window
8. Double click on simulate behavioral model
9. Observe the output waveforms obtained by simulation and verify truth table
LOGIC DIAGRAM:-

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HDL and MATLAB at GPC Thrikaripur by SITTTR Kerala
 Dataflow Modelling

Program 1
// Module 4-to-1 multiplexer using data flow.
module mux4_to_1 (out, i0, i1, i2, i3, s1, s0);
// Port declarations from the I/O diagram
output out;
input i0, i1, i2, i3;
input s1, s0;
//Logic equation for out
assign out = (~s1 & ~s0 & i0) |
(~s1 & s0 & i1) |
(s1 & ~s0 & i2) |
(s1 & s0 & i3) ;
endmodule
Program 2
// 4-to-1 multiplexer in Dataflow model using conditional operator
module mux4_to_1 (out, i0, i1, i2, i3, s1, s0);
// Port declarations from the I/O diagram
output out;
input i0, i1, i2, i3;
input s1, s0;
// syntax of conditional operator is “condition_check ? true_statement:False_statement”
assign out = s1 ? ( s0 ? i3 : i2 ) : ( s0 ? i1 : i0 ) ;
endmodule
ADDERS
AIM:-
Write verilog HDL codes in dataflow level one bit adder and four bit adder
OBJECTIVES:-
Upon completion of this experiment the students will be able to

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HDL and MATLAB at GPC Thrikaripur by SITTTR Kerala
 Dataflow Modelling

1. To understand the usage of concatenation operator for assigning multiple outputs

with single assignment
PROCEDURE
1. Open Xilinx ISE and create a new project with a project name (eg:-Adder1)
2. Create a verilog source file with filename same as module name
3. Write the given program on the editor window
4. Select synthesis/Implementation in the drop down list of source window
5. Create source file of test bench waveform with timings as the following information for
the signal c_in
♦ Clock High Time: 100 ns.
♦ Clock Low Time: 100 ns.
♦ Input Setup Time: 10 ns.
♦ Output Valid Delay: 10 ns.
♦ Offset: 0 ns.
6. Modify the test bench waveform by click on relevant part of the waves and save it
7. Now select Behavioral simulation from source window after selecting the tbw file in the
process window
8. Double click on simulate behavioral model
9. Observe the output waveforms obtained by simulation and verify truth table
LOGIC DIAGRAM:-

TRUTH TABLE:-
INPUT OUT PUT
a B c_in Sum c_out
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
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 Dataflow Modelling

PROGRAMS:-
Program 1
// Define a 1-bit full adder by using dataflow statements.
module fulladd(sum, c_out, a, b, c_in);
// I/O port declarations
output sum;
output c_out;
input a, b;
input c_in;

// Specify the function of a full adder

assign sum = a ^ b ^ c_in;
assign c_out = (a & b) | (b & c_in ) | ( a & c_in);
endmodule
Program 2
// Define a 4-bit full adder by using dataflow statements.
module fulladd4(sum, c_out, a, b, c_in);

// I/O port declarations

output [3:0] sum;
output c_out;
input[3:0] a, b;
input c_in;

// Specify the function of a full adder

assign {c_out, sum} = a + b + c_in;

endmodule
DIY(2 X 4 Decoder)

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