WD16

MICROCOMPUTER

(Using MCP 3-Chip Microprocessor Set)

PROGRAMMER'S REFERENCE MANUAL

WESTERN!If DIGITAL
CORPORATION
WD1600 MICROCOMPUTER

(Using MCP 3-Chip Microprocessor Set)

PROGRAMMER'S REFERENCE MANUAL

4 OCTOBER 1976

©1977-WESTERN DIGITAL CORP.

NEWPORT BEACH, CA. 92663
I
~

c
 TABLE OF CONTENTS

PAGE
CHAPTER ONE - GENERAL 1.1
Abbreviations
Processor Status Word
Registers

CHAPTER TWO - INTRODUCTION 2.1

Addressing Modes
Stack Operations
Interrupt Lines
Priori ty Mask
External Status Register
Power Up Options
Halt Options
User Bootstrap Routine
System Error Traps
Reserved Core Locations

CHAPTER THREE - OP CODES 3.1

Format 1 Op Codes
Format 2 Op Codes
Format 3 Op Codes
Format 4 Op Codes
Format 5 Op Codes
Format 6 Op Codes
Format 7 Op Codes
Format 8 Op Codes
Format 9 Op Codes
Format lOOp Codes
Format 11 Op Codes

APPENDIX A - Numeric Op Code Table Al

APPENDIX B - Assembler Notes Bl
APPENDIX C - Programming Notes Cl
APPENDIX D - Microm State Code Functions Dl
APPENDIX E - Op Code Timings El
CHAPTER 1 - GENERAL

The WD16~~ microcomputer is a 16 bit machine with both word and byte
addressing, an automatic push down hardware sta.ck, vectored interrupt
handling, eight 16 bit registers, and PC relative addressing. A byte is
defined as 8 bits, and a word is defined as 2 bytes. A memory address
increment of one is an increment of 1 byte. An address increment of two
is an increment of 1 word. Word addresses always start on even bytes.
For any memory location the even byte is the least significant byte.
Bit ~ is defined as the LSB of a memory location.

(MSB) 15 8 7 ~ (LSB)

I High Byte
~-----.--' .....
Low Byte
""--.(
]
Byte Address Byte Address
~ (ODD) X (EVEN) )
--....r
Word Address X (EVEN)

Unless otherwise stated, word addressing is implied. All addresses

and op codes are done in hex unless otherwise stated. All hex numbers
are enclosed within double quotes.

LEGEND OF ABBREVIATIONS

REG Register

SRC Source Address

(SRC) = Contents of Source Address

DST Destination Address

(DST) Contents of Destination Address

(SRC) B = Contents of Source Byte Address

(DST) B = Contents of Destination Byte Address

1
 x = Ones Complement of X

-x = Twos Complement of X

A = Logical And

'V = Logical Or

SL = Exclusive or
@ = Indirect

{- = Push

t = Pop
+ = Destination Direction

+ = Addition
- = Subtraction
* = Multiplication
/ = Division
= Double Precision Chain Link

PROCESSOR STATUS WORD

A 16 bit Processor Status (PS) Word exists. The format is as follows:

15 8 7 4 3 2 1 f4
IExt. Status Reg. I ALU IN I z I V I ci
Where bits 8-15 are the contents of the external status register
(see chapter 2), bits 4-7 are the status of the microprocessor ALU flags,
and bits ~ -3 are the status of the condition indicators at the time the
PS is formed. The ALU flags are of no use or concern to the progranuner.
They are stored along with the condition indicators automatically as a func-
tion 'of the micro-op. The four condition flags are updated during the exe-
cution of most op codes, and are used by the branch instructions to test
for valid branch conditions. The exact status of each indicator is de-
fined along with the descriptions of individual op codes in chapter 3.
In general, however, ~e indicators are set by the following conditions:

N = set if the MSB of the result is set.

Z = set if the result is zero.
V= set if arithmetic overflow (underflow) occurs during addition (subtractic
Set to exclusive -or of Nand C indicators otherwise.
C= set if carry (borrow) occurs during addition (subtraction). Also set
to last bit shifted out during a shift operation.
(

2
 REGISTERS

There are 8 registers in the WD1600. All are 16 bits long. Six
can be hsed as either accumulators or index registers, one is the
stack pointer (SP), and one is the program counter (PC). The registers
are numbered ~ - R7 with R6 = SP and R7 = pc. The register set is
usually referred to in the following manner: ~ - RS, SP, PC.

3
 CHAPTER TWO - INTROQUCTION

ADDRESSING MODES

In general there are 8 addressing modes for both source and

destination addressing. Not all op codes accept all 8 modes (see
chapter 3). Those that do use the following format: 3 bits for
the index register (R~ - RS, SP, PC) and 3 bits for the mode. The
mode bits are the upper 3 bits of the 6 bit set. The modes are de-
fined below. The numbers in parenthesis refer to notes that follow
the definitions.

MODE NAME SYMBOLIC DESCRIPTION

~ Direct Register REG REG is or contains operand.

1 Indirect Register @REG REG contains address of operand.
2 Auto-increment (REG) + REG contains address of operand.
REG is post-incremented (1).
3 Auto-increment @(REG)+ REG contains address of add-
deferred ress of operand. REG is post-
incremen ted by 2.
4 Auto-decrement - (REG) REG is predecremented (1). REG
then contains address of operand.
5 Auto-decrement @- (REG) REG is predecremented by 2. REG
deferred then contains address of address
of operand.
6 Indexed register X(REG) Contents of REG plus X is address
of operand (2).
7 Indexed register @X(REG) Contents of REG plus X is address
deferred of address of operand (2).

NOTE 1: For word operations the increment/decrement is 2. For byte

operations the increment/decrement is 1 unless the index register
is SP or PC. In this case the increment/decrement is always 2.

NOTE 2: The contents of REG remain unchanged.

When using PC as the index register the assembler accepts the

following 4 formats in place of the formats mentioned above for
ease of programming.

MODE NAME SYMBOLIC DESCRIPTION

2 Immediate #N Operand N follows op code.

3 Absolute @#N Address of operand is N and it
follows the op code in memory.
6 Relative A PC relative offset to address A,
which contains operand, follows
op code.
7 Relative deferred @A PC relative offset to address A,
which contains address of operand,
follows the op code.

The 8 modes are referred to as Source Mode ~ to Source Mode 7

(S~ -SM7) and Destination Mode ~ to Destination Mode 7 (DMSI -DM7). In
Chapter 3 these modes are referred to in general terms during op code def-
initions as "SRC" and "DST".
1
 STACK OPERATIONS

Although automatic stack operations are provided for, no

specific area of memory is set aside for the stack. The user must
assign an area of memory by loading the stack pointer with the top
address of the designated stack area. Stack operations are push-
down pop-up operations with predecrements and post-increments of SP.
Stack operations may also be executed explicitly by using SP as an
index register with op codes that allow SM~ - SM7 and/or OM~ - OM7
addressing.
When pushing the PS the word is formed just prior to the push.
When popping the PS the condition indicators and interrupt enable flag
are set to the status of the appropiate bits in the popped PS. Other
than that the popped PS goes nowhere. Unless otherwise stated popping
the PS from the stack performs the above mentioned operations and only
the above mentioned operations.
When pushing the PC onto the stack PC will be set to the address
of the op code that follows the op code that caused the push. There
are cases where some op code formats can alter this rule. They gen-
erally involve advanced programming techniques. A few are mentioned
in appendix C. In particular, system errors that are caused by pro-
gramming errors and not real time error conditions will push a PC
that points to the op code that follows the op code that caused the
error. The stored PC must be decremented by two to get the address
of the offending op code.

INTERRUPT LINES

There are 4 interrupt lines available to the system. They are

labeled I~ - 13. These lines are assigned functions as follows:

I~ = Vectored interrupt line

II = Nonvectored interrupt line
12 = Enable/disable for I~ and II.
I3 = Halt switch

The priority among the lines is as follows:

13, Il~I2, I~~I2.

Note that 13 is always enabled. Note also that the nonvectored inter-
rupt has priority over the vectored interrupt. The system is currently
set up so that power fail and a real time clock can be assigned to II,
and up to 16 devices assigned to I~.* The two interrupts operate as follows:
A) Nonvectored Interrupt (II)
PS and PC are pushed onto the stack. 12 is disabled. The external
status register is tested for a power fail. If power fail is true
PC is fetched from location "14". If power fail is false PC is
fetched from location "2A", and a microm state code is transmitted
to clear the line clock (see appendix 0).
B) Vectored Interrupt (I~)
PS and PC are pushed onto the stack. 12 is disabled. An Interrupt
Acknowledge is executed, and the device code of the interrupting de-
vice is read in and stripped to bits 1- 4. PC is fetched from location
*NOTE: AI though onlX ~ 4 bj. t device code ia cUJ;'l;ently used, a minor microm
change can allow a device code of from 1-15 bits.
2
"28" and the device code is added to it. The ccntents of this inter-
mediate location are read in and added to PC to form the final address.
Each intermediate location is a table entry that contains the PC rela-
tive offset from the start of the device handler routine to itself. The
absolute address of the start of the table is in location "28".

PRIORITY MASK

Associated with the interrupts is a priority interrupt mask. This

is a 16 bit mask where each bit position represents a priority level.
Each priority level can be assigned to one or more devices. A one in any
bit position can represent an interrupt enable or disable for its associ-
ated devices as the hardware dictates. The SAVS, RSTS, and MSKO op codes
each alter the mask. When the mask is altered it is written into location
II 2E" for storage. While the mask is on the bus a microm state code is
transmitted (see appendix D) to signal the I/O devices that a new mask is
being transmitted. Each device can then look at its assigned mask bit
while the memory write to location 12E" is taking place. Whether or not
the mask feature is actually used by the I/O devices in no way alters
the operations of the op codes mentioned above.

EXTERNAL STATUS REGISTER

As a part of the hardware external to the CPU the External Status

Register supplies the CPU, upon demand, with information about the status
of certain hardware areas. This register is gated onto the bus when its
associated microm state code is present (see appendix D). The format
of the register is as follows:
Bit 7 = Power Fail Status
Bit 6 = Bus Error (Time Out) Status
Bit 5 Parity Error Status
Bit 4 I2 Interrupt Line Status
Bit 3 = Halt Option Jumper #2
Bit 2 = Halt Option Jumper #1
Bit 1 = Power Up Option Jumper #2
Bit ~ = Power Up Option Jumper #1

Bits 8-15 are don't care. Bits 5-7 are real time error conditions that
also generate a system reset (see next section). Bit 4 is the interrupt
enable status. The jumpers can be logic units, switches, or hard wired
jumpers as the user wishes. The various options associated with the 4
jumpers are discussed later.

POWER UP OPTIONS

A system reset indicate one of 4 conditions: power fail, bus error,

parity error, or power up. There are 2 levels of power fail possible in
this system (see appendix C): minor and major. Only a major power fail
generates a system reset. Both types set bit 7 in the External Status
Register. The following steps are performed after a system reset.

AI) Trace and wait flags are reset if on.

A2) The external Status Register is fetched.

3
A3) The Line-clock-clear state code is transmitted.
A4) 12 is reset.
A5) If power fail bit is set go to Dl.
A6) If bus error bit is set go to Cl.
A7) If parity error bit is set go to BI.
AS) Go to D2 otherwise.

BI) Push PS and PC onto stack.

B2) Fetch PC from location "12"and begin execution.

Cl) Push PS and PC onto stack.

C2) Fetch PC from location "IS" and begin execution.

Dl) Wait until power fail status = ~.

D2) Send a' system-reset microm state code.
D3) Wait 300 cycles.
D4) Execute power up option 1,2,3 or 4 per jumpers.

For a proper initial power up either bit 7 must be set or bits 5-7 must
be reset when the system reset line is released.
The 4 power up options are as follows:

JUMPERS OPERATION

Execute user bootstrap routine.

Pick up ~-R5, SP, PC, and PS from memory
locations ~-"l~".
l~ Execute selected halt option.
11 Fetch PC from location "16".

HMT OPTIONS

When the halt switch (I3) is set during program execution one of 4 halt
options is selected. 'the halt op code* and power up option #2 also select
the halt option specified. The options are as follows:

JUMPERS O:PERATION

Execute user bootstrap routine.

Save R~-R5,SP,PC and PS in memory locations
~-"l~". Wait until 13 = ~, then restore R~­
R5,SP,PC and PS from memory locations ~-"l~".
l~ Lock up processor (requires a system reset to clear)
11 Fetch new PC from location "16".

*NOTE: Conditional. See Chapter 3.

USER BOOTSTRAP ROUTINE

wnen the user bootstrap routine is selected as an option the system creates
the starting address by placing address "C~~~" in pC and then replacing
bits S-13 with the contents of the 6 bit External Address Register. This
register is gated in with a microm status code (see appendix D).

4
It allows the user 64 different starting addresses in the range "C~~~"
to "FF~~".

SYSTEM ERROR TRAPS

With the exception of the major power fail error that is a function
of a system reset, all error conditions perform a common routine as outlined
below. A non-vectored interrupt and some op codes also use this routine.
The numbers in parenthesis refer to notes that follow the table.

1) PS is pushed onto the stack

2) PC is pushed onto the stack
3) PC is fetched from location X where "X" is from the following table

(1)(2)(3) 12" for bus error PC

(1) (2) (3) 14" for nonvectored interrupt power fail PC
(I) (2) (3) 18" for parity error PC
(1) (2) (3) lA" for reserved op code error PC
(1) (2) (3) lC" for illegal op code format error PC
(1) (2) (3) lE" for XCT error PC
(1) (2) 2~" for XCT trace PC
(1) (2) (3) 2A" for nonvectored interrupt PC
(1) (2) 2C" for BPT PC

NOTE 1: wait flag reset if on

NOTE 2: trace flag reset if on
NOTE 3: interrupt enable (I2) reset if on

The meaning of the wait and trace flags is discussed in chapter 3. Note
that the nonvectored interrupt power fail PC is a minor power fail condition,
not a major one. See appendix C for full detail on how to include both
major and minor power fail conditions in the hardware.

RESERVED CORE LOCATIONS

The following is a complete list of memory locations that are re-

served for specific system functions or options. Byte addresses are given.

LOCATIONS RESERVED FUNCTION

~ - "II" R~ - RS, SP, PC and PS for power up/halt options

"12" - "13" bus error PC
"14 - "15" nonvectored interrupt power fail PC
"16" - "17" power up/halt option power restore PC
"18" - "19" pari ty error PC
"lA" -"lB" reserved op code PC
"lC" - "lD" illegal op code format PC
"IE" - ''IF'' XCT error PC
"213" - "21" XCT trace PC
"22" -
"23" SVCA ~able address
"24" - "25" SVCB PC
"26" - "27" SVCC PC
"28"- "29" vectored interrupt (I~) table address
"2A" -
"2B"
"2C" - "2D"
nonvectored interrupt (II) PC
BPT PC
"2E" - 2F" I/O priority interrupt mask
"3lJ" - "3F" reserved for floating point option
(
 CHAPTER 3 - OP CODES

This chapter is divided into a number of sections, each repre-

senting one class of op codes. At the beginning of each section there
is a detailed description of the format for that class. A list of op
codes and their base numeric values, less arguments, is also included.
A detailed description of each op code in the class then follows.

FORMAT 1 OP CODES

Single word - no arguments

15 12 11 8 7 4 3 o
L I OPC

There are 16 op codes in this class representing op codes "~fJfJfJ" to

"~~~F". Each is a one word op code with no arguments with the exception
of the SAVS op code which is a two word op code. Word two of the SAVS
op code is the I/O priority interrupt mask. The op codes and their mnemoni~s
are:

BASE OP CODE MNEMONIC

~~~~ NOP
~Illll RESET
1l1l1l2 lEN
~llfJ3 IDS
~~1l4 HALT
~~~5 XCT
ll~fJ6 BPT
1l~1l7 WFI
~~fJ8 RSVC
~~~9 RRTT
fJll~A SAVE
~~~B SAVS
~~~C REST
~~~D RRTN
~~~E RSTS
f6f6IlF RTT

NOP NO OPERATION

FORMAT: NOP
FUNCTION: No operations are performed
INDICATORS : Unchanged

RESET I/O RESET

FORMAT: RESET
FUNCTION: An I/O reset pulse is transmitted
INDICATORS : Unchanged

1
lEN INTERRUPT ENABLE

FORMAT: lEN
FUNCTION: The interrupt enable (I2) flag is set. Allows
one more instruction ~o execute before inter-
rupts are recognized.
INDICATORS: Unchanged

IDS INTERRUPT DISABLE

FORMAT: IDS
FUNCTION: The interrupt enable (12) flag is reset.
This instruction can honor interrupts, but
the 12 bit in the PS that is stored on the stack
is reset if an interrupt occurs.*
INDICATORS: Unchanged

*NOTE: On some machines 12 will be set or reset during the lEN or

IDS. If so the change will be valid immediately, not one op
code later.

HALT HALT

FORMAT: HALT
FUNCTION: Tests the status of the Power Fail bit in the
external status register. If the bit is set it
is assumed that the HALT occured in a power fail
routine, and the following operations occur:
1) The interrupt enable (12) flag is reset
2) The CPU waits until the Power Fail bit is rese"
3) PC is fetched from location "16", and program
execution begins at this new location
If the power fail bit is reset then the CPU waits
until the halt switch (13) is set. At that time
the selected halt option (see chapter 2) is execub
The interrupt enable flag is also reset.
INDICATORS : Unchanged

XCT EXECUTE SINGLE INSTRUCTION

FORMAT: XCT
OPERATION: PC + @SP, SP t
PS +- @SP, SP t
Trace flag set, execute op code
+SP, @SP + PS
+SP, @SP + PC
Trace flag reset
PC + (loc "2~") if no error
PC + (loc "lE") if error
FUNCTION: PC and PS are popped from the stack, but 12 is no t
altered. The trace flag, which disables all inter
rupts except 13, is set. The op code is executed:
PS and PC are pushed back onto the stack)and PC
is fetched from location 2~" • The trace flag is
II

reset. If the program tries to execute a HALT, XC

BPT, or WFI the attempt is aborted, PS and PC are

2
pushed onto the stack, and PC is fetched from location "lE" instead.
12 is also reset.
INDICATORS: Depends upon executed op code

BPT BREAKPOINT TRAP

FORMAT: BPT
OPERATION: ~ SP, @SP +PS
,.: SP, @SP +PC
PC +. (loc "2C")
FUNCTION: PS and PC are pushed onto the stack. PC is
fetched from location "2C"
INDICATORS : Unchanged

WFI WAIT FOR INTERRUPT

FORMAT: WFI
FUNCTION: The CPU loops internally without accessing
the data bus until an interrupt occur~. Program
execution continues with the op code that follows
the WFI after the interrupt has been serviced.
The interrupt enable flag is also set.
INDICATORS : Unchanged

SAVE SAVE REGISTERS

FORMAT: SAVE
OPERATION: -} SP, @SP+ R5
~ SP, @SPof- R4
~ SP, @SP+ R3
~ SP, @SP+ R2
~ SP, @SP+ RI
-} SP, @SP+ Rf6
FUNCTION: Registers R5 to ~ are pushed onto the stack.
INDICATORS : Unchanged.

SAVS SAVE STATUS

FORMAT: SAVS MASK

OPERATION: SAVE
'"+SP, @SP + (loc "2E")
(loc "2E") +0 (loc "2E ") V mask
MsKO
lEN
FORMAT: Registers R5 to Rf6 and the priority mask in location
"2E" are pushed onto the stack. The old and new masks
are ORED together and placed in location "2E".
A mask out state code (see appendix D) is transmitted
and the interrupt enable (I2) flag is set.
INDICATORS : Unchanged

REST RESTORE REGISTERS

FORMAT: REST
OPERATION: ~ -+- ·@SP, SP +
Rl @SP, SP 1-
+-
R2 +- @SP, SP t
3
 R3 +- @SP, SP of
R4 +- @SP, SP t
RS+ @SP, SP t

FUNCTION: Registers R? to ~ are popped from the stack,

INDICATORS: Unchanged

RTT RETURN FROM TRAP

FORMAT: RTT
OPERATION: PC +@SP, SP t
PS +-@SP, SP t
FUNCTION: PC and PS are popped from stack
INDICATORS : N = Set per PS bit 3
Z = Set per PS bit 2
V = Set per PS bit 1
C = Set per PS bit ~

RRTN RESTORE AND RETURN FROM SUBROUTINE

FORMAT: RRTN
OPERATION: REST
PC +- @SP, sPt
FUNCTION: Registers R~ to R5 and PC are popped
from the stack
INDICATORS : Unchanged

~TT RESTORE AND RETURN FROM TRAP

FORMAT: RRTT
OPERATION: REST
RTT
FUNCTION: Registers ~ to R5~ PC and PS are popped
from the stack.
INDICATORS : Set per PS bits ~ - 3

RSTS RESTORE STATUS

FORMAT: RSTS
OPERATION: (LOC 12E") +- @SP, SP t
MSKO
REST
RTT
FUNCTION: The priority mask is popped from the stack and
restored to locaton "2E". A MASK OUT state code
(See Appendix D) is transmitted. Registers ~
to !OJ PC and PS are popped from the stack.
INDICATORS : Set per PS bits ~ - 3

RSVC RETURN FROM SUPERVISOR CALL (B or C)

FORMAT: RSVC
OPERATION: REST
SPI-
RTT

4
FUNCTION: Registers ~ to RS, PC and PS are popped from
the stack with the saved SP bypassed.
INDICATORS : Set per PS bits ~ - 3

s
 FORMAT 2 OP CODES

SINGLE WORD - 3 BIT REGISTER ARGUMENT

15 12 11 8 7 3 2 o
OPC REG

There are 4 op codes in this class representing op codes "f6f6lfl"

to "f6f12F". Each is a one word op code with a single 3 - bit register
argument. The op codes and their mnemonics are:

BASE OP CODE MNEMONIC

f6!ilf6 IAK
f6f1l8 RTN
flf62f6 MSKO
f6f628 PRTN

IAK INTERRUPT ACKNOWLEDGE

FORMAT: IAK REG

FUNCTION: An interrupt acknowledge (READ and lACK) is
executed, and the 16 bit code that is returned
is placed in· REG unmodified. Used with the
nnnvectored interrupt when the user does
not wish to use the vectored format.
INDICATORS : Unchanged

RTN RETURN FROM SUBROUTINE

FORMAT: RTN REG

OPERATION: PC;: + REG
REG· + @SP,Sp. t
FUNCTION: The' . linkage register is placed in PC and the
saved linkage register is popped from the stack.
The register used must be the same one that was
used for the subroutine call.
INDICATORS : Unchanged

MSKO MASK OUT

FORMAT: MSKO REG

OPERATION: (LOC "2E" ) + REG
MSKO
FUNCTION: The contents of REG are written into location
"2E" and a MASK OUT state code (see appendix D)
is transmitted.
INDICATORS : Unchanged

PRTN POP STACK AND RETURN

FORMAT: PRTN REG

OPERATION: TMP+ @SP
SP + SP+(TMP*Q)
RTN REG
6
FUNCTION: Twice the value of the top word on
the stack is added to SP, and a standard
RTN call is then executed.
INDICATORS : Unchanged

7
 · ..
FORMAT 1 OP CODES

SINGLE WORD - 4 BIT NUMERIC ARGUMENT

15 12 11 8 7 4 3 ~
fI , fI I OPC I ~I
There is only one op code in this class representing op codes
"flfl3f1" to "flfl3F". It is a one word op code with a 4-bit numeric argument.

BASE OP CODE MNEMONIC

LCC

LCC LOAD CONDITION CODES

FORMAT: LCC ARG

FUNCTION: The 4 indicators are loaded from bits fI-3
of the op code as specified.
INDICATORS : N = Set per bit 3 of op code
Z = Set per bit 2 of op code
V = Set per bit 1 of op code
C = Set per bit fI of op code

8
 FORMAT 4 OP CODES

SINGLE WORD - 6 BIT NUMERIC ARGUMENT

15 12 11 8 7 6 5
I OPC I ARG

There are 3 op codes in this class representing op codes

"f6f64[1" to "f6f1FF".
All 3 are supervisor calls. All 3 are one word
op codes with a 6-bit numeric argument.

BASE OP CODE MNEMONIC

SVCA
SVCB
SVCC

SVCA SUPERVISOR CALL "A"

FORMAT: SVCA ARG

OPERATION: ~SP I@SP of- }\S:i -I- SP I@SP+ PC
PC -+ (LOC "22") + (ARG *2)
PC +PC + @PC
FUNCTION: PS and PC are pushed onto the stack. The
contents of location "22" plus twice the value
of the argument (which is always positive) is placed
in PC to get the table address. The contents
of the table address is added to PC to get the
final destination address. Each table entry is the
relative offset from the start of the desired
routine to itself.
INDICATORS : Unchanged

SVCB SUPERVISOR CALL "B"

SVCC SUPERVISOR CALL "c"

FORMAT: SVCB ARG

SVCC ARG
OPERATION: TMPA + SP
+SP I @SP+ PS
~SP, @SP+ PC
TMPB +SP
'+ SP, @SP + TMPA
SAVE
Rl + TMPB
R5 + ARG*2
PC... (LOC "24") if SVCB
PC +' (LOC "26") if SVCC

FUNCTION: PS and PC are pushed onto the stack. The value

of SP at the start of op code execution is the
pushed followed by registers R5 to~. 'The address
of the saved PC is placed in Rl, and twice the value
of the 6-bit positive argument is placed in R5.

9
 PC is loaded from location ,. 24"
for SVCB or "26" for SVCC.
INDICATORS : Unchanged.

«
10
 FORMAT 5 OP CODES

SINGLE WORD - 8 BIT SIGNED NUMERIC ARGUMENT

15 8 7 ~
OPC I DISPLACEMENT c= ,

There are 15 op codes in this class representing op codes

"~l~~" to "~7FF" and "8~~W' to "87FF". All are branches with a
signed 8 bit displacement that represents the word offset from PC
(which points to the op code that follows) to the desired branch
location. The op codes consist on one unconditional branch, 8
signed conditional branches, and 6 unsigned conditional branches.
No op code in this class modifies any of the indicator flags. Max-
imum branch range is +.128, -127 words from the branch op code.

BASE OP CODE MNEMONIC

)i11)i1)i1 BR
)i12)i1)i1 BNE
)i13~)i1 BEQ
)i14~~ BGE
)i15)i1)i1 BLT
)i16)i1)i1 BGT
)i17)i1~ BLE
8~~)i1 BPL
81~~ BMI
82~0 BHI
83~~ BLOS
84)i1~ BVC
850~ BVS
86~)i1 BCC, BHIS
87~~ BCS, BLO

BR BRANCH UNCONDITIONALLY

FORMAT: BR DEST
OPERATION: PC + PC+ (DISP *2)
FUNCTION: Twice the value of the signed displacement
is added to PC.

SIGNED BRANCHES

BNE BRANCH IF NOT EQUAL TO ZERO

FORMAT: BNE DEST

OPERATION: IF Z = ¢, PC + PC + (DISP *2)

~,____________________~B~RA~N~C~H~I~F~E~Q~U~A~L~TO~~Z~E~RO~_________________

FORMAT: BEQ DEST

OPERATION: IF Z = 1, PC + PC + (DISP *2)

BGE B~~CH IF GREATER THAN OR EQUAL TO ZERO

FORMAT: BGE DEST

OPERATION: IF N9v = ~, PC + PC + (DISP *2)

11
BLT BRANCH IF LESS THAN ZERO

FORMAT: BLT DEST

OPERATION: IF N~V = 1, PC + PC + (DISP *2)

BGT BRANCH IF GREATER THAN ZERO

FORMAT: BGT DEST

OPERATION: IF Z v(~) = ~, PC + PC + (DISP *2)

BLE BRANCH IF LESS THAN OR EQUAL TO ZERO

FORMAT: BLE DEST

OPERATION: IF ZV (WV) = 1, PC ... PC + (DISP *2)

BPL BRANCH IF PLUS

FORMAT: BPL DEST

OPERATION: IF N = ~, PC + PC + (DISP *2)

BMI BRANCH IF MINUS

FORMAT: BMI DEST

OPERATION: IF N = 1, PC + PC + (DISP *2)

UNSIGNED BRANCHES

BHI BRANCH IF HIGHER

FORMAT: BHI DEST

OPERATION: IF CVZ = ¢, PC + PC + (DISP *2)

BLOS BRANCH IF LOWER OR SAME

FORMAT: BLOS DEST

OPERATION: IF CVZ = 1, PC + PC + (DISP *2)

BVC BRANCH IF OVERFLOW CLEAR

FORMAT: BVC DEST

OPERATION: IF V = ¢, PC + PC + (DISP *2)

BVS BRANCH IF OVERFLOW SET

·FORMAT: BVS DEST

OPERATION: IF V = 1"PC + PC + (DISP *2)

BCC BRANCH IF CARRY CLEAR

BHIS BRANCH IF HIGijER OR SAME

FORMAT: BeC DEST

BHIS DEST
OPERATION: IF C = ¢, PC + PC + (DISP *2)

12
BCS BRANCH IF CARRY SET
BLO BRANCH IF LOWER

FORMAT: BCS DEST

BLO DEST

OPERATION: IF C = 1, PC~ PC + (DISP *2)

13
 FORMAT 6 OP CODES

S.iNGLE WORD - SINGLE OPS - SPLIT FIELD - DMf6 ONLY

15 9 8 6 5 4 3 o
I OPC BASE I REG I OPC I COUNT

There are 12 op codes in this class representing op codes "f68~~"

to "f69FF", "88~f6" to " 89FF" , and "8E~fIS" to "8FFF". There are 4 immedi-
ate mode op codes with a register as a destination, 4 multiple count
single register shifts, and 4 multiple count double register shifts.
In all op codes the actual count (or number in the case of the immedi-
ates) is the value of bits f6 - 3 plus one. Count is always a positive
number in the range 1 - "l~", but it is stored in the op code as ~ -
"F". All of these op codes are one word op codes with the op codes them-
selves split between bits 9-15 and 4-5.
In the case of the double shifts the 32 bit number (REQtl)
(REG) is the operand. If REG = PC then (REG+l) = R!2S.

BASE OP CODE MNEMONIC

~8f1S(IS ADDI
~81flS SUBI
flS82f1S BICI
flS83f1S MOVI
88f1SfIS SSRR
881flS SSLR
882f1S SSRA
883f1S SSLA
8Ef6f1S SDRR
8ElflS SDLR
8E2f1S SDRA
8E3f1S SDLA

ADD I ADD IMMEDIATE

FORMAT; ADDI NUMBER, REG

OPERATION: REG +- REG + COUNT + 1
FUNCTION: The stored number plus one is added to the
destination register.
INDICATORS : N = Set if bit 15 o~ the result is set
Z = Set if the result = (IS
V = Set if arithmetic overflow occurs; i.e. set
if both operands were positive and the sign of
the result is negative
C = Set if a carry was generated from bit 15
of the result

SUBI SUBTRACT IMMEDIATE

FORMAT: SUBI NUMBER, REG

OPERATION: REG +. REG - (COUNT +1)
FUNCTION: The stored number plus one is subtracted from
the destination register.

14
INDICATORS : N ~ Set if bit l5 Qf ~e ~eault is set
Z = Set if the result = ~
V = Set if arithmetic underflow occurs; i.e. set
if the operands were of opposite signs and
the sign of the result is positive
C = Set if a borrow was generate from bit 15
of the result

BICI BIT CLEAR IMMEDIATE

FORMAT: BICI NUMBER, REG

OPERATION: REG +. REG l!.(COUNT + 1)
FUNCTION: The stored number plus one is one's complemented
and ANDED to the d~stination register
INDICATORS : N = Set if bit 15 of the result is set
Z Set if the result = ¢
V = Reset
C = Unchanged

MOVI MOVE IMMEDIATE

FORMAT: MOVI NUMBER REG

I

OPERATION: REG +- COUNT + 1

FUNCTION: The stored number plus one is placed in
the destination register
INDICATORS : N Reset
Z = Reset
V Reset
C = Unchanged

SSRR SHIFT SINGLE RIGHT ROTATE

FORMAT: SSRR REG, COUNT

FUNCTION: A l7-bit right rotate is done stored count+l
times on REG:C-Flag. The C-Flag is shifted into
bit 15 of REG, and the C-Flag gets the last bit
shifted out of REG bit ¢.
INDICATORS : N = Set if bit 7 of REG is set
Z = Set if REG = ¢
V = Set to exclusive or of Nand C flags
C = Set to the value of the last bit shifted
out of REG bit ¢

SSLR SHIFT SINGLE LEFT ROUTINE

FORMAT: SSLR REG, COUNT

FUNCTION: A 17-bit left rotate is done stored count+l
times on C-Flag: REG. The C-Flag is shifted
into bit ¢ of REG and the C-Flag gets the
last bit shifted out of REG bit 15.
INDICATORS : N = Set if bit 15 of REG is set
Z = Set if REG = ~
V = Set to exclusive or of N and C flags
C = Set to the value of the last bit shifted
out of REG bit 15.

15
SSRA SHIFT SINGLE RlGliT ARITHMETIC

FORMAT: SSRA REG, COUNT

FUNCTION: A l7-bit right arithmetic shift is done
stored count+l times on REG: C-Flag. Bit
15 of REG is replicated. The C-Flag gets the
last bit shifted out of REG bit~. Bits shifted
out of the C-Flag are lost.

INDICATORS : N = Set if bit 7 of REG is set

Z = Set if REG = ~
V = Set to exclusive or of Nand C flags
C = Set to the value of the last bit shifted
out of REG bit ~

SSLA SHIFT SINGLE LEFT ARITHMETIC

FORMAT: SSLA REG, COUNT

FUNCTION: A l7-bit left arithmetic shift is done stored
count+l . times on C-Flag:R;EG. Zeros are shifted
into REG bit~, and the C-FLAG gets the last bit
shifted out of REG bit 15. Bits shifted out of the
C-Flag are lost-
INDICATORS: N = Set if REG bit 15 is set
Z = Set if REG = ~
V = Set to exclusive or of N and C flags
C = Set to the value of the last bit shifted
out of REG bit 15

SDRR SHIFT DOUBLE RIGHT ROTATE

FORMAT: SDRR REG, COUNT

FUNCTION: REG+l:REG:C-Flag is rotate right stored
count+l times. The C-Flag is shifted into
REG+l bit 15, REG+l bit ¢ is shifted into
REG bit 15, and REG bit ¢ is shifted into the C-Fla
INDICATORS: N = Set if bit 7 of REG is set
Z = Set if REG = ~
V = Set to exclusive or of N and C flags
C = Set to the value of the last bit shifted
out of REG bit ~

SDLR SHIFT DOUBLE LEFT ROTATE

FORMAT: SDLR REG, COUNT

FUNCTION: A 33 bit left rotate is done stored count+l
times on C-Flag:REG+l:REG. The C-Flag is
shifted into REG bit ~, REG bit 15 is shifted
into REG+l bit~, and REG+l bit 15 is shifted
into the C-Flag
INDICATORS : N = Set if REG+l bit 15 is set
Z = Set if REG+l = ~
V = Set to exclusive or of N and C flags
C = Set to the value of the last bit shifted
out of REG+l bit 15.

16
SDRA SHIFT OOUBLE RIGHT ARITHMETIC

FORMAT: SDRA REG, COUNT

FUNCTION: A right arithmetic shift is done stored
count+l times on REG+l:REG:C-Flag.
Bit 15 of REG+l is replicated. Bit ~ of
REG+l . is shifted to bit 15 of REG. Bit
~ of REG is shifted to the C-Flag. Bits
shifted out of the C-Flag are lost.
INDICATORS: N = Set if bit 7 of REG is set
Z = Set if REG = ~
V = Set to exclusive or of Nand C flags
C = Set to the value of the last bit
shifted out of REG bit ~

SDLA SHIFT DOUBLE LEFT ARITHMETIC

FORMAT: SDLA REG, COUNT

FUNCTION: A left arithmetic shift is done stored
count+l times on C-Flag:REG+l:REG.
Zeros are shifted into REG bit ~, REG bit
15 is shifted to REG+l bit~. REG+l
bit 15 is shifted to the C-Flag. Bits
shifted out of the C-Flag are lost.
INDICATORS: N = Set if REG+l bit 15 is set
Z = Set if REG+l = ~
V Set to exclusive or of N and C flags
C Set to the value of the las~ bit shifted
out of REG+l bit 15

17
 FORMAT 7 OP CODES

SINGLE OPS - ONE OR TWO WORDS - DM~ TO DM7

15 6 5 3 2 o
OPC I MODE REG I
There are 32 op codes in this class representing op codes
"~A~~" to "~DFF" and "SA~~" to nSDFF". All addressing modes from
~ to 7 are available with all registers available as index regis-
ters (see chapter two). A one word op code is generated fbr ad-
dressing modes ~ to 5. A two word op code is generated for addres-
sing modes 6 and 7 with the offset value in word two. For DM6 and
DM7 with PC as the index register PC is added to the offset from word
two af€er the offset is fetched from memory. The offset is there-
fore relative to a PC that points to the op code that follows (i.e.
current op code + 4). Codes "SA~~" to "SCC~" are BYTE ops.

BASE OP CODE MNEMONIC BASE OP CODE MNEMONIC

~A~~ ROR 8A~~ RORB

~A4~ ROL SA4~ ROLB
~AS~ TST SAS~ TSTB
~AC~ ASL SAC~ ASLB
~B~~ SET SB~~ SETB
~B4~ CLR SB4~ CLRB
~BS{t ASR SBS~ ASRB
~BC~ SWAB 8BC~ SWAD
~C~~ COM SC~~ COMB
~C4~ NEG 8C4~ NEGB
~CS~ INC SCS~ INCB
~CC~ DEC 8CC~ DECB
~D~~ IW2 8D~~ LSTS
~D4~ SXT SD4~ SSTS
~DS~ TCALL 8DS~ ADC
~DC~ TJMP SDC~ SBC

WORD OPS

ROR ROTATE RIGHT

FORMAT: ROR DST

FUNCTION: A I-bit right rotate is done on (DST):C-Flag
The C-Flag is shifted into (DST) bit 15, and (DST)
bit ~ is shifted into the C-flag.
INDICATORS: N = Set if bit 7 of (DST) is set
Z = Set if (DST) = ~
V = Set to exclusive or of N and C flags
C = Set to the value of the bit shifted out of (DST)

ROL ROTATE LEFT

FORMAT: ROL DST

FUNCTION: A I-bit left rotate is done on C-Flag: (DST). The

IS
 C-Flag i~ shifted into (OST) bit ~, and (OST)
bit 15 is shifted intQ the C-Flag.
INDICATORS : N = Set if bit 15 of (OST) is set
Z = Set if (OST) = ~
V = Set to exclusive or of N and C flags
C = Set to the value of the bit shifted out of (OST)

TST TEST WORD

FORMAT: TST OST

OPERATION: (OST) l!. (OST)
FUNCTION: The indicators ?re set to reflect the destination
operand status.
INOICATORS: N = Set if (OST) bit 15 is set
Z = Set if (OST) = ~
V = Reset
C = Unchang~d

ASL ARITHMETIC SHIFT LEFT

FORMAT: ASL OST

FUNCTION: A I-bit left arithmetic shift is done on (DST). A
zero is shifted into (OST) bit ~, and (OST) bit 15
is shifted into the C-Flag.
INDICATORS : N - Set if (DST) bit 15 is set
Z = Set if (OST) = ~
V = Set to exclusive or of N and C flags
C = Set to the value of the bit shifted out of (OST)

SET SET TO ONES

FOP.MAT: SET OST

OPERATION: (OST) +' "FFFF"
FUNCTION: The destination operand is set to all ones
INOIcATORS : N = Set
Z = Reset
V = Reset
C = Unchanged

CLR CLEAR TO ZEROS

FORMAT: CLR OST

OPERATION: (OST) +- ~
FUNCTION: The destination operand is cleared to all zeros
INDICATORS : N = Reset
Z = Set
V = Reset
C = Unchanged if OMgJ. Reset if OMI-0M7.

ASR ARITHMETIC SHIFT RIGHT

FORMAT: ASR OST

FUNCTION: A I-bit right arithmetic shift is done on (OST). Bit
15 of (OST) is replicated. Bi t ~ of (OST) is shifted.
into the C-Flag.

19
INDICATORS : N = Set if (OST) bit 7 is set
Z = Set if (OST) = ~
V = Set to exclusive or of N and C flags
C = Set to the value of the bit shifted out of (OST)

SWAB SWAP BYTES

FORMAT: SWAB OST

OPERATION: COST) 15-8 t (OST) 7-~
FUNCTION: The upper and lower bytes of (OST) are exbanged.
INOICATORS : N - Set if (OST) bit 7 is set
Z = Set if (OST) lower byte = ~
V = Reset
C = Unchanged

COM COMPLEMENT

FORMAT: COM OST

OPERATION COST) -+- COST)
FUNCTION: The destination operand is one's complemented.
INDICATORS.: N = Set if (OST) bit 15 is set
Z = Set if (OST) = ~
V = Reset
C = Set

NEG NEGATE

FORMAT: NEG OST

OPERATION: (OST) -+- - (OST)
FUNCT<ION: The destination operand is two's complemented.
INOiICATORS: N = Set if (OST) bit 15 is set
Z = Set if COST) = ~
V = Set if (OST) = "8~~~".
C = Reset if (OST) = ~

INC INCREMENT

FORMAT: INC OST

OPERATION: COST) -+- (OST) + 1
FUNCTION: The destination operand is incremented by one.
INOICATORS : N = Set if COST) bit 15 is set
Z = Set if (OST) = ~
V = Set if (OST) = "8~~~"
C = Set if a carry is generated from (OST) bit 15

OEC OECREMENT

FORMAT: OEC OST

OPERATION: (OST) -+- (OST) - 1
FUNCTION: The destination operand is decremented by one,
INDICATORS : N = Set if (OST) bit 15 is set
Z = Set if (OST) = ~
V = Set if (OST) = 17FFF"
C = Set if a borrow is generated from (OST) bit 15

20
IW2 INCREMENT WORD BY TWO

FORMAT: IW2 DST

OPERATION: (DST) -+- (DST) + 2
FUNCTION: The destination operand is incremented by two..
INDICATORS : N = Set if (OST) bit 15 is set
Z = Set if (DST) = [4
V= Set if (DST) = "8[4[4[4" or "8[4[41"
C = Set if a carry is generated from (DST) bit 15

SXT SIGN EXTEND

FORMAT: SXT DST

OPERATION: IF N = [4, (DST) -+- [4
IF N = 1, (DST; -+- "FFFF"
FUNCTION: The N-Flag status is replicated in the destination operand
INDICATORS : Utic;::hanged

TCALL TABLED SUBROUTINE CALL

FORMAT: TCALL DST

OPERATION: SP, @SP +. PC
4.-
PC +: PC + (DST)
PC -+- PC + @PC
FUNCTION: PC, which points to the op code that follows, is pushed
onto the stack. The destination operand is added to
PC. The contents of this intermediate table address is
also added to PC to get the final destination address.
Note that at least one op code must exist between the
TCALL and the table for a subroutine return.
INDICATORS : Unchanged

TJMP TABLED JUMP

FORMAT: TJMP DST

OPERATION: PC -+- PC + (OST)
PC-+- PC + @PC
FUNCTION: The destination operand is added to PC, and the contents
of this intermediate location is also added to PC to get
the final destination address-
INDICATORS : unchanged

LSTS LOAD PROCESSOR STATUS

FORMAT: LSTS DST

FUNCTION: The four indicators and the interrupt enable (I2)
are loaded from the destination operand.
INDICATORS : Set to the status of (DST) bits [4 - 3

SSTS STORE PROCESSOR STATUS

FORMAT: SSTS DST

FUNCTION: The processor status word is formed and stored in (DST).
INDICATORS : Unchanged

21
ADC ADO CARRY

FORMAT: ADC OST

OPERATIQN; (PST) *" lOST) + C-flag
FUNCTION: The carry flag is added to the destination operand
INDICATORS : N= Set if (OST) bit 15 is set
Z = Set if (OST) = ~
V = Set to exclusive or of N and C flags
C == Set if a carry is generated from COST) bit 15

SBC SUBTRACT CARRY

FORMAT: SBC OST

OPERATION: COST) 0(- (OST) - C-Flag
FUNCTION: The Carry flag is subtracted from the destination operand
INotICATORS : N = Set if (OST) bit 15 is set
Z = Set if (OST) = ~
V = Set to exclusive or of N and C flags
C == Set if a borrow is generated from COST) bit 15

BYTE OPS

For OM~ addressing only the lower byte of the destination register
is affected by a byte op code. For DM1-DM7 addressing only the speci~
fied meIOOry byte is affected by a byte op. For even memory addresses
the lower byte is altered, and for ddd meIOOry addresses the upper byte
is altered.

RORB ROTATE RIGHT BYTE

FORMAT: RORB DST

FUNCTION: A l-bit right rotate is done on (OST)B:C-Flag. Bit
~ of (OST)B is shifted into the C-Flag, and the C-Flag
is shifted into (OST)B bit 7.
INDICATORS : N = Set if (DST)B bit 7 is set
Z = Set if (DST)B = ~
V = Set to exclusive or of N and C flags
C = Set to the value of the bit shifted out of (OST) Bbit ~

ROLB ROTATE LEFT BYTE

FORMAT: ROLB DST

FUNCTION: A l-bit left rotate is done on C-flag : (DST)B· Bit 7
of (DST)B is shifted into the C-flag, and the C-flag
is shifted into (DST)B bit ~

INDICATORS: N = Set if (DST)B bit 7 is set

Z = Set if (OST)B = ~
V == Set to exclusive or of N and C flags
C = Set to the value of the bit shifted out of (OST)B bit 7

TSTB TEST BYTE

JroRMAT: TSTB OST

OPERATION: (OST) B f1 (DST) B

22
FUNCTION: The destination operand status sets the indicators.
INDICATORS : N = Set if (DST)B bit 7 is set
Z = Set if (DST)B = ~
V = Reset
C Unchanged

ASLB ARITHMETIC SHIFT LEFT BYTE

FORMAT: ASLB DST

FUNCTION: A I-bit left arithmetic shift is done on C-Flag:(DST)B
A zero is shifted into (DST)B bit ~, and (DST)B bit 7 is
shifted into the C-flag.
INDICATORS: N = set if (DST)B bit 7 is set
Z = Set if (DST) B = ~
V = Set to exclusive or of Nand C flags
C = Set to the value of the bit shifted out of (DST)B bit 7

SETB SET BYTE TO ONES

---------------------
FORMAT: SETB DST
OPERATION: (DST) B + "FF"
FUNCTION: The destination byte operand is set to all ones
INDICATORS : N = Set
Z = Reset
V Reset
C = Unchanged

CLRB CLEAR BYTE TO ZEROS

FORMAT: CLRB DST

OPERATION: (DST) B +' $3
FUNCTION: The destination byte operand is cleared to all zeros.
INDICATORS : N = Reset
Z = Set
V = Reset
C = Reset

ASRB ARITHMETIC SHIFT RIGHT BYTE

FORMAT: ASRB DST

FUNCTION: A I-bit right arithmetic shift is done on (DST)B:
C-flag. Bit 7 of (DST)B is replicated. Bit $3 of
(DST)B is shifted into the C-flag.
INDICATORS : N = Set if (DST)B bit 7 is set
Z = Set if (DST)B = ~
V = Set to exclusive or of Nand C flags
C = Set to the value of the bit shifted out of (DST)B bit ~

SWAD SWAP DIGITS

FORMAT: SWAD DST

FUNCTION: The two hex digits in the destination byte operand
are exchanged with each otherl
INDICATORS : N = Set if (DST)B bit 7 is set
Z : Set if (DST)S = ~
V = Set if (DST)B bit 7 is set
C = Reset

23
COMB COMPLEMENT BYTE

FORMAT: COMB DST

OPERATION: (DST) B +- (OST) B
FUNCTION: The destination byte operand is one's complemented
INDICATORS : N = Set if (DST)B bit 7 is set
Z = Set if (DST)B = ~
V = Reset
C = Set

NEGB NEGATE BYTE

FORMAT: NEGB DST

OPERATION: (DST) B + - (DST) B
FUNCTION: The destination byte operand is two's complemented
INDICATORS: N = Set if (DST)B bit 7 is set
Z = Set if (DST)B = ~
V = Set if (DST) B = "81'5151"
C = Reset if (DST)B = 51

INCB INCREMENT BYTE

FORMAT: INCB DST

OPERATION: (DST) B + (DST) B + 1
FUNCTION: The destination byte operand is incremented by one
INDICATORS : N = Set if (DST)B is set
Z = Set if (DST)B = 51
V = Set if (DST)B = "8161616"
C = Set if a carry is geperated from (DST)B bit 7

DECB DECREMENT BYTE

FORMAT: DECB DST

OPERATION: (DST) B+ (DST) B - 1
FUNCTION: The destination byte operand is decremented by one
INDICATORS: N = Set if (DST)B bit 7 is set
Z = Set if (DST)B = 51
V - Set if (DST)B = "7FFF"
C = Set if a borrow is generated from (DST)B bit 7

24
 FORMAT 8 OP CODES*

DOUBLE OPS - SINGLE WORD - S~ AND D~ ONLY

15 6 5 3 2 ~
OPC IS REG I D REG I
There are 8 op codes in this class representing op codes
"~E~~" to "~FFF". Only addressing mode ~ is allowed for both the
source and destination. All are one word op codes, and all are block
move instructions. The last 4 can be used as pseudo DMA ops in some
hardware configurations. In all cases the source register contains
the address of the first word or byte of memory to be moved, and the
destination register contains the address of the first word or byte
of memo17Y to receive the data being moved. The number of words or
bytes being moved is contained in R~. The count ranges from 1-65536
(~ = 65536) words or bytes. The count in ~ is an unsigned positive
integer. None of the indicators are altered by these op codes.
Each of these o~ codes is interruptable at the end of each word
or byte transfer. If no interrupt requests are active the trans-
fers continue. PC is not incremented to the next op code until the
opcode is completed. This allows for complete interruptability
as long as register integrity is maintained during the interrupt.

BASE OP CODE MNEMONIC

fJE~~ MBWU
fOE4fO MBWD
~E8~ MBBU
~EC~ MBBD
~F~~ MBWA
fOF4fO MBBA
roF8~ MABW
~FC~ MABB

* NOTE: These op codes are all in the third microm.

MBWU MOVE BLOCK OF WORDS UP

FORMAT: MBWU SRC, DST

FUNCTION: The word string beginning with the word addressed
by the source register is moved to successively
increasing word addresses as specified by the des-
tination register. The source and destination reg-
isters are each incremented by two after each word
is transferred. R~ is decremented by one after each
transfer, and transfers continue until ~ = ~.

MBWD MOVE BLOCK OF WORDS DOWN

FORMAT: MBWD SRC, DST

FUNCTION: The word string beginning with the word addressed
by the source register is moved to successively

25
 decreasing word addresses as specified by the des-
tination register. The source and destination reg-
isters are each decremented by two after each word is
transferred. ~ is decremented by one after each
transfer, and transfers continue until ~ = ~.
INDICATORS : Unchanged

MBBU MOVE BLOCK OF BYTES UP

FORMAT: MBBU SRC, DST

FUNCTION: The byte string beginning with the byte addressed by
the source register is moved to successively increas-
ing byte addresses as specified by the destination.
register. The source and destination registers are
each incremented by one after each byte is transfer-
red. ~ is decremented by one after each transfer,
and transfers continue until ~ = ~.
INDICATORS: Unchanged.

MBBD MOVE BLOCK OF BYTES DOWN

FORMAT: MBBD SRC, DST

FUNCTION: The byte string beginning with the byte addressed by
the source register is moved to successively decreas-
ing byte addresses as specified by the destination
register. The source register, destination register,
and R$, are each decremented by one after each byte is
transferred. Transfers continue until R~ = ~.
INDICATORS: Unchanged ('

MBWA MOVE BLOCK OF WORDS TO ADDRESS

FORMAT: MBWA SRC, DST

FUNCTION: Same as MBWU except that the destination register is
never incremented.
INDICATORS : Unchanged

MBBA MOVE BLOCK OF BYTES TO ADDRESS

FORMAT: MBBA SRC, DST

FUNCTION: Same as MBBU except that the destination register is
never incremented.
INDICATORS : Unchanged

MABW MOVE ADDRESS TO BLOCK OF WORDS

FORMAT: MABW SRC, DST

FUNCTION: Same as MBWU except that the source register is never
incremented.
INDICATORS : Unchanged

MABB MOVE ADDRESS TO BLOCK OF BYTES

FORMAT: MABB SRC, DST

FUNCTION: Same as MBBU except that the source register is never (
incremented.
INDICATORS : Unchanged
26
 FORMAT 9 OP CODES

DOUBLE OPS - ONE OR TWO WORDS - SM9$, DMf6 to DM7

15 9 8 6 5 3 2 @
OPC I S REG I D MODE D REG I
There are 8 op codes in this class representing op codes
"7[4[4[4" to "7FFF". Source mode f6 addressing only is allowed, but des-
tination modes [4 - 7 are allowed for all op codes except 3: JSR and
LEA with DM9$ will cause an illegal instruction format trap (see chap-
ter 2), and SOB is a special format unique to itself. It is includ-
ed here only because its destination field is 6 bits long. SOB is
a branch instruction. Its 6 bit destination field is a positive
word offset from PC, which points to the op code that follows,
backwards to the desired address. Forward branching is not allowed.
SOB is always a one word op code, and it is used for fast loop con-
trol. All other op 00des are one wo~d long for DM9$ to DM5 addressing
and two words long for DM6 or DM7 addressing. The rules for PC rel-
ative addressing with DM6 or DM7 are the same as they are for the
format 7 op codes. Preliminary decoding of all these op codes ex-
cept SOB presets the indicator flags as follows: N = 1, Z = [4,
V = f6, C = 1.

BASE OP CODE MNEMONIC

7f4f4[4 JSR
72f4f4 LEA
74[4[4 ASH
76f6f4 SOB
78[4[4 XCH
7A[4f4 ASHC
7Cf4[4 MUL
7E[4f4 DIV

JSR JUMP TO SUBROUTINE

FORMAT: JSR REG, DST

OPERATION: +SP @SP + REG
I

REG +PC
PC +DST
FUNCTION: The linkage register is pushed onto the stack; PC,
which points to the op code that follows, is placed
in the linkage re~ister; and the destination add-
ress is placed in PC. DMf4 is illegal. The assem-
bler recognizes the format "CALL DST" as, being
equivalent to "JSR PC, DST".
INDICATORS : Preset

LEA LOAD EFFECTIVE ADDRESS

FORMAT: LEA REG, DST

OPERATION: REG + DST

27
FUNCTION: The destination address is placed into the source
register. DM(6 is illegal. The assembler recognizes
the format "JMP DST" as being equivalent to "LEA PC,DST" •

INDICATORS : Preset

XCH EXCHANGE

FORMAT: XCH REG, DST

OPERATION: REG ~(DST)
FUNCTION: The source register and destination contents are
exchanged with each other.
INDICATORS : Preset

SOB SUBTRACT ONE AND BRANCH (IF" iJ)

FORMAT: SOB REG, DST

OPERATION: REG+ REG - 1
IF REG F ~, PC +. PC - (OFFSET *2)
FUNCTION: The source register is decremented by one. If the
result is not zero then twice the value of the des-
tination offset is subtracted from PC.
INDICATORS : Unchanged

ASH ARITHMETIC SHIFT

FORMAT: ASH REG, DST

FUNCTION: The source register is shifted arithmetically with
the number of bits and direction specified by the
destination operand. If (DST) = iJ no shifting occurs.
If (DST) = -X then REG is shifted right arithmetically
X bits as in an SSRA. If (DST) = +X then REG is shifted
left arithmetically X bits as in an SSLA. Only an 8
bit destination operand is used. Thus, DST is a byte
address. For DM~ only the lower byte of the destin-
ation register is used.
INDICATORS: Preset if (DST) = iJ. Otherwise:
N = Set if REG bit 15 is set
Z = Set if REG = iJ
V = Set to exclusive or of N and C flags
C = Set to the value of the last bit shifted out of REG

ASHC ARITHMETIC SHIFT COMBINED

FORMAT: ASHC REG, DST

FUNCTION: Exactly the same as ASH except that the shift is done
on REG+l:IU3G. All other comments apply.
INDICATORS : Preset if (DST) =~. Otherwise.
N = Set if REG+l bit 15 is set
Z = Set if REG+l: REG = iJ
V - Beset
C = Set to the value of the last bit shifted out

28
MOL MULTIPLY

FORMAT: MOL REG, DST

OPERATION: REG+l :REG + REG * (DST)
FUNCTION: An unsigned multiply is performed on the source
register and the destination operand. The unsigned
32 bit result is placed in REG+l:REG.
INDICATORS : N = Set if REG+l bit 15 is set
Z = Set if REG+l:REG = ~
V = Reset
C = Indeterminate

DIV DIVIDE

FORMAT: DIV REG, DST

OPERATION: REG + [REG+1: REG/ (DST) ]
REG+ 1 + REMAINDER
FUNCTION: An unsigned divide is performed on the 32 bit source
op'~rand REG+l:REG and the destination operand. The
unsigned result is placed in REG, and the unsigned
remainder is placed in REG+l.No divide occurs and the
V-flag is set if REG+l is greater than or equal to (DST)
since the result will not fit into 16 bits. If the
divisor is zero both the V and C flags are set.

INDICATORS : If no division error:

N = Set if REG bit 15 is set
Z = Set if REG =~
V = Reset
C = Indeterminate
If division error:
N = Reset
Z = Reset
V = Set
C = set if (DST) ~

29
 FORMAT lOOP CODES

OOUBLE OPS - ONE TO THREE WORDS - S~ TO SM?, DM~ TO DM7.

15 12 11 9 8 6 5 3 2
I OPC I S MODE I S REG I D MODE I D REG i
There are 12 op codes in this class representing op codes "l~~~"
to "6FFF" and "9~~~" to "EFFF". Nine of the op codes are word ops.
Three are byte ops'. Full source and destination mode addressing with
any register is allowed. A one word op code is generated for S~-
SMS and D~-DM5 addressing. A two word op code is generated for either
SM6-SM7 or DM6-DM7 addressing, but not both. For both SM6-SM7 and
DMc-DM7 addressing a three word op code is generated. For a two word
op code with word #1 at location X: X + 2 contains the source or
destination offset and PC = X + 4 if PC is the register that applies
to the offset in location X + 2. For a three word op code with word
#1 at location X: X + 2 contains the source offset and X + 4 contains
the destination offset. If the source register is PC then PC = X + 4
when added to the offset to compute the source address. If the destin-
ation register is PC then PC = X + 6 when added to the offset to compute
the destination address.

BASE OP CODE MNEMONIC

l~~~ ADD
2~~f6 SUB
3f6f6f6 AND
4f6f6f6 BIC
5f6f6~ BIS
6f6~~ XOR
9f6f6~ CMP
A~~~ BIT
Bf6f6f6 MOV
cf6f6~ CMPB
Df6~~ MOVB
E~~~ BISB

WORD OPS

ADD ADD

FORMAT: ADD SRC, DST

OPERATION: (DST) + (SRC) + (DST)
FUNCTION: The source and destination operands are added to-
gether, and the sum is placed in the destination.
INDICATORS : N = Set if (DST) bit 15 is set
Z = Set if (DST) = f6
V = Set if both operands were of the same sign and
the result was of the opposite sign
C = Set if a carry is generated from bit 15 of the
result

30
SUB SUBTRACT

FORMAT: SUB SRC, DST

OPERATION: (DST) +" (DST) - (SRC)
FUNCTION: The two's complement of the source operand is added
to the destination operand, and the sum is placed
in the destination.
INDICATORS : N = Set if (DST) bit 15 is set
Z = Set if (OST) = ~
V = Set if operands were of different signs and
the sign of the result is the same as the sign
of tht:: source operand
C = Set if a borrow is generated from bit 15 of the
result

AND AND

FORMAT: AND SRC, DST

OPERATION: (D;::;T) ~+- (SRC) fl (DST)
FUNCTION: The source and destination operan da ~re logically
ANDED tOgether, and the .r:esul t is :.placed ih the
destination.
INDICATORS: N = Set if '(loST) bit 15 is set
Z = Set if (DST) = ~
V = Reset
C = Unchanged

BIC BIT CLEAR

FORMAT: BIC SRC, DST

OPERATION: (DST) + (SRC) fl (DST)
FUNCTION: The one's complement of the source operand is log-
ically ANDEO with the destination operand, and the
result is placed in the destination.
INDICATORS : N = Set if (DST) bit 15 is set
Z = Set if (DST) = ~
V = Reset
C = Unchanged

BIS BIT SET

FORMAT: BIS SRC, DST

OPERATION: (DST) + (SRC) V (DST)
FUNCTION: The source and destination operands are logically
ORED, and the result is placed in the destination.
INDICATORS: N = Set if (DST) bit 15 is set
Z = Set if (DST) = ~
V = Reset
C = Unchanged

XOR EXCLUSIVE OR

FORMAT: XOR SRC, DST

OPERATION: (DST) + -(SRC) !1- (OST)
FUNCTION: The source and destination operands are logically EX-
CLUSIVE ORED, and the result is placed in the destin~tion.

31
INDICATORS : N = Set if (DST) bit 15 is set
Z = Set if (DST) = ~
V = Reset
C = Unchanged

CMP COMPARE

~RMAT: CMP SRC, DST

OPERATION: . (SRC) - (DST)
FUNCTION: The destination operand is subtracted from the
source operand, and the result sets the indicators.
Neither operand is altered.
INDICATORS : N = Set if result bit 15 is set
Z = Set if result = ~
V = Set if operands were of opposite sign and the
sign of the result is the same as the sign of (DST)
C = Set if a borrow is generated from bit 15 of the
result

BIT BIT TEST

FORMAT: BIT SRC, DST

OPERATION: (SRC) A (DST)
FUNCTION: The source and destination operands are logically
ANDED, and the result sets the indicators. Neither
operand is altered.
INDICATORS : N = Set if result bit 15 is set
Z = Set if result = ~
V = Reset
C = unchanged

MOV MOVE

FORMAT: MOV SRC, DST

OPERATION: (DST) + (SRC)
FUNCTION: The destination operand is replaced with the source
operand.
INDICATORS : N = Set if (DST) bit 15 is set
Z = Set if (DST)" = ~
V = Reset
C = Unchanged

BYTE OPS

For S~ addressing only the lower byte of the source register is

used as an operand. For SM1-SM7 addressing only the addressed memory
byte is used as an operand. For D~ addressing only the lower byte
of the destination register is used as an operand with one exception:
MOVB will e~tenQ the sign through bit 15. For DMI-DM7 addressing only
the addressed memory byte is used as an operand.

CMPB COMPARE BYTE

FORMAT: CMPB SRC, DST

OPERATION: (SRC)B - (DST)B

32
FUNCTION: The destination operand is subtracted from the
source operand, and the result sets the indicat-
ors • Neither operand is altered.
INDICATORS : N = Set if result bit 7 is set
Z = Set if result = ~
V = Set if operands were of different signs and
the sign of the result is the same as the sign
of (DST)B.
C = Set if a borrow is generated from result bit 7

MOVB MOVE BYTE

FORMAT: MOVB SRC, DST

OPERATION: (DST) B -+- (SRC) B
FUNCTION: The destination operand is replaced with the source
operand. If DM~ the sign bit (bit 7) is replicat-
ed through bit 15.
INDICATORS : N = Set if (DST)B bit 7 is set
Z Set if (DST)B = ~
V = Reset
C = Unchanged

BISB BIT SET BYTE

FORMAT: BISB SRC, DST

OPERATION: (DST) B '*" . (SRC) B V (DST) B
FUNCTION: The source and destination operands are logically
ORED, and the result is placed in the destination.
INDICATORS : N = Set if (DST)B bit 7 is set
Z = Set if (DST)B = ~
V = Reset
C = Unchanged

When using auto increments or decrements in either the source

or destination (or both) fields the user must remember the following
rule: All increments or decrements in the source are fully completed
before any destination decoding begins even if the same index regis-
ter is used in both the source and destination. The two fields are
totally independent.

33
 FORMAT 11 OP CODES

DOUBLE OPS - ONE WORD - FLOATING POINT.

12 11 8 7 6 432
1111 OPC I I
I SRC II I DST

There are 16 OP Codes in this class representing OP Codes "Ff6f6f6" to

"FFFF". Only five are currently defined. They reside in the third
microm along with the Format 8 OP Codes. The remaining 11 OP Codes
are mapped to the fourth microm for future expansion or customized
user OP Codes. All are one word long. Two source and destination
addressing modes are available. These two modes, FP~ and FPl, are
unique to these OP Qodes. Each consists of a 3-bit Register Desig-
nation and a 1 bit indirect flag preceeding the register designator.
For FP,0 the indirect bit is ~, and FPl it is one. Both the source and
destination fields have both addressing modes. The modes are defined
as follows:

FPf6 The designated register contains the address of the operand.

FPl The designated register contains the address of the address

of the operand.

FP,0 is the same as standard addressing mode l, and FPl is the same
as standard addressing mode 7 with an offset of zero.

The computed address is the address of the first word of a 3 word f

I
floating point operand. The first word contains the sign, exponent, .~

and high byte of the mantissa. The next higher address contains the
middle two bytes of the mantissa, and the next higher address after
that contains the lowest two bytes of the mantissa. This format is
half way between single and double precision floating point formats,
and it represents the most efficient use of microprocessor ROM and
register space. The complete format is as follows:

1. A 1 bit sign for the entire number which is zero for positive.

2. An 8~it base-two exponent in excess-128 notation with a range of

+127, -128. The only legal number with an exponent of -128 is
true zero (all zeros).
3. A 40 bit mantissa with the MSB inpl1ed.

Since every operand is assumed to be normalized.upon entry and every

result is normalized before storage in the destination addresses,
and since a normalized mantissa has a MSB equal to one, then only 39
bits need to be stored. The MSB is implied to be a one, and the
bit position it normally occupies is taken over by the exponent to
increase its range by a factor of two. The full format of a floating
point operand is a follows:
15 14 7 6 g
LOCATION X: [S I EXPONENT J
I MANTISSA (HIGH)
15 8 7 @I
LOCATION X+2: _-=MANT==I=S=SA~...J:,--~(.:.:MI=DD::LE=-')_ _ _ _--:-l
a...1

(
15 8 7 g

34
True zero is represented by a field of 48 zeroes. In effect, the CPU
considers any number with an exponent of all zeroes (-128) to be a zero
during multiplication and division. For add and subtract the only legal
number with an exponent of -128 is true zero. All others cause erroneous results.
No registers are modified by any Format 11 OP Code. However, to make room
internally for computations 4 registers are saved in memory locations
"30" - "38" during the exelution of FADD, FSUB, FMUL and FDIV. These
registers are retrieved at the completion of the OP Codes. The
registers saved are: the destination address, SP, PC and~. No
Format 11 OP Code is interruptable ,(for obvious reasons). FMUL uses
location "38" for temporary storage of partial results.

FLOATING POINT ERROR TRAPS

Location "3E" is defined as the floating point error trap PC. When-
ever an overflow, underflow, or divide by zero occurs a standard trap
call is executed with PS and PC pushed onto the stack, and PC fetched
from location "3E". r:. is not altered. The remaining memory locations
that are reserved for the floating point option (" 3A and "3C") are
not currently used. The status of the indicator flags and destina-
tion addresses during the 3 trap conditions are defined as follows:

FOR UNDERFLOW (FADD, FSUB, FMUL, FDIV)

N I Destination contains all zeroes

Z = f1 (true zero).
V I
C f1
FOR OVERFLOW (FADD, FSUB, FMUL)

N= ~ Destination not altered in any way.

Z =~
V= 1
C = ~

FOR OVER FLOW (FDIV)

N = f1 Destination not altered if overflow detected

Z = ~ during exponent computation. Undefined
V 1 otherwise. (Used to save unnormalized
C = ~ partial results during a divide) •

FOR DIVIDE BY ZERO (FDIV)

N= 1 Destination not altered in any way.

Z = ~
V=1
C =1

RESERVED TRAPS

If the third microm is in the system and the fourth is not then the
last 11 ~oa~ing point OP codes are the only ones that will cause a
reserved OP code trap if executed. If the third microm is not in the
system then all Format 8 and '11 OP Codes will cause a reserved OP code
trap if executed. However, since the Format 8 OP Codes are: interrupt-
able the PC is not advance until the completion of the moves. In
all other cases PC is advanced when the OP Code is fetched. For
these reasons the PC that is saved onto the stack will point to the
offending OP Code during a reserved OP Code trap if and only if
the offending OP Code is a Format 8 OP COde. For the Format 11 .
OP Codes the saved PC will' point to the OP Code that follows the
offending OP Code. If the User wishes to identify which OP Code
caused the reserved OP Code trap he must not preceed a FOrmat 8
OP Code with a Format 11 OP Code or a literal that looks like a
Format 11 OP Code.

BASE OP CODE MNEMONIC

FflC1f1 FADD
Fll1f1 FSUB
F2f1f1 FMUL
F3f1f1 FDIV
F41116 FCMP
FSfl16
F61116
F7f1f1
F8f1f1
F9C1f1
FAfIfI
FB16f1
FC16f1
FD1616
FE1616
FFfl16
FADD FLOATING POINT ADD

FORMAT: FADD SRC,OST

OPERATION: (OST) + (OST) + (SRC>
FUNCTION: The source and destination operands are added
together, normalized, and the result is stored
in place of the destination operand.
INDICATORS : (if no errors)
N = Set if the result sign is negative (set).
Z = Set if the result is zero
V = Reset
C = Reset

FSUB FLOATING POINT SUBTRACT

FORMAT: FSUB SRC, OST

OPERATION: (OST)· + (DST) - (SRC)
FUNCTION: The source operand is subtracted from the
destination operand. The result is normalized
and stored in place of the destination operand.

WARNING: THIS OP CODE COMPLEMENTS THE SIGN OF THE SOURCE OPERAND !!!.
MEMORY AND DOES AN FADD.

INDICATORS : (if no errors)

N = Set if the result sign is negative (set)
Z = Set if the result is zero.

36
 v = Reset
C = Reset
FMUL FLO~ING POINT MULTIPLY

FORMAT: FMUL SRC, OST

OPERATION: (OST) +(OST) * (SRC)
FUNCTION: The source and destination operands are multi-
plied together, normalized, and the result is
stored in place of the destination operand.
INDICATORS: (if no errors)
N = Set if the sign of the result is negative (set).
Z = Set if the result is zero
V = Reset
C = Reset

FDIV FLOATING POINT DIVIDE

FORMAT: FDIV SRC, DST

OPERATION: (OST) +(DST) / (SRC)
FUNCTION: The destination operand is divided by the source
operand. The result is normalized and stored in
place of ,the destination operand.
INDICATORS ; (if no errors)
N = Set if the sign of the result is negative (set).
Z = Set if the result is zero
V Reset
C = Reset

FCMP FLOATING POINT COMPARE

FORMAT: FCMP SRC, OST

OPERATION: (SRC) - (OST)
FUNCTION: The destination operand is compared to the source
operand, and the indicators are set to allow
a SIGNED conditional branch.
INDICATORS : N = Set if result is negative
Z = Set if result is zero
V = Set if arithmetic underflow occurs.*
C = Set if a borrow is generated. *

*NOTE: True if first words of beth operands are !!2.:!:. equal.

CAUTION: The same physical operand may be used as both the source and
destination operand for any of the above floating point OP
Codes with no abnormal results except two. They are:
,1) If an error trap occurs the operand will probably be altered.
2) An FSUB gives an ans~er of -lx, if x # ¢, instead of ¢.

37
 APPENDIX A

NUMERIC OP CODE TABLE

OP CODE MNEMONIC

~~~~ ~~~~ ~~~~ ~~~~ NOP

~~~~ {4~{4~ ~~~{4 {4{4{41 RESET
{4~{4~ {4~~~ ~~~{4 ~~1~ IEN
~~{4~ f6~~f6 f6f6~{4 f6~11 IDS
f6~~~ ~~f6f6 f6{4{4f6 f61~f6 HALT
f6{4~{4 ~~f6~ ~{4~{4 {41{41 XCT
~~~~ {4~~~ ~f6f6f6 ,nf6 BPT
~~~f6 ~~{4~ ~{4f6~ f6111 WFI
{4~~f6 ~~~f6 f6{4~f6 If6~{4 RSVC
~f6{4{4 f6~~~ ~{4~~ 1~1 RRTT
~~~~ ~~~~ ~~~{4 l{4l{4 SAVE
{4{4~{4 {4~~{4 {4{4~~ 1{411 SAVS
~{4{4~ {4{4~{4 ~{4{4~ IH~ REST
~{4{4{4 ~{4{4{4 ~{4~{4 ll{4l RRTN
{4{4~~ ~~{4~ {4{4{4{4 l1l{4 RSTS
{4{4{4~ ~~~~ ~{4{4{4 1111 RTT
{4~{4~ {4{4{4{4 {4{4~1 {4REG IAK
{4{4{4~ {4~{4~ {4~{4l lREG RTN
{4~{4{4 {4~{4{4 ~{41{4 {4REG MSKO
~{4~{4 ~{4~~ ~~l{4 lREG PRTN
{4{4{4~ ~~~{4 ~{411 ARGU LCC
{4~{4{4 {4{4~~ {4lAR GUME SVCA
{4~~~ {4~{4{4 l{4AR GUME SVCB
~~{4{4 {4~~~ llAR GUME SVCC
~~{4~ ~~~1 DISP LACE BR
~~~~ ~~U; DISP LACE BNE
{4{4{4~ {4~11 DISP LACE BEQ
~{4~~ {41~{4 DISP LACE BGE
~~~{4 {41{41 DISP LACE BLT
~{4{4{4 ~11~ DISP LACE BGT
~~{4~ ~111 DISP LACE BLE
~f1f1{4 l{4{4R EG{4{4 VALU ADDI
~~f1f1 If1~R EG{41 VALU SUBI
~f1f1~ l~~R EGl{4 VALU BrCI
{4{4{4~ If1~R EG11 VALU Movr
~{4f1{4 l~lf6 {4f6MO DREG ROR
f6f1f1f6 l{4l{4 f6lMO DREG ROL
{4f1~~ l~lf6 l{4MO DREG TST
{4{4{4{4 1{41f1 llMO DREG ASL
f6{4{4{4 l~l1 {4{4MO DREG SET
{4f6~~ 1~11 {4lMO DREG CLR
f1{4f1f1 lf611 l{4MO DREG ASR
~f6f6f1 lf611 llMO DREG SWAB
taflflfl 1l~{4 ~f1MO DREG COM
~f1f1{4 llflf6 {41MO DREG NEG
flf1{4{4 11f6f1 lf1MO DREG INC
{4f1{4f1 ll${4 llMO DREG DEC

1
OP CODE MNEMONIC

~f6f6f6 11~1 f6f6MO DREG IW2

f6f6~~ 11~1 {HMO DREG SXT
f6r1r1f1 11r11 If6MO DREG TeALL
~f6f6~ 11f61 llMO DREG TJMP
~f6f6f6 111f6 f6f6SR COST MBWU
~~~f6 111~ fllSR CDST MBWD
f6f1f1f1 111~ 1f1SR COST MBBU
~f6~f6 111f6 l1SR CDST MBBD
~f6f6f6 1111 flflSR CDST MBWA
~~f6~ 1111 f61SR CDST MBBA
~f6f1f1 1111 1f6SR CDST MABW
flfIf6f1 1111 l1SR COST MABB
flf6~l SRCR EGDS TREG ADD
~f61fl SRCR EGOS TREG SUB
~f611 SRCR EGOS TREG AND
~1~~ SRCR EGDT TREG BIC
f61~1 SRCR EGDT TREG BIS
~11f6 SRCR EGDS TREG XOR
16111 rlf6f6R RRDS TREG JSR
~111 f6f61R RRDS TREG LEA
f6111 f61f6R RRDS TREG ASH
f6111 f611R RROF FSET SOB
f6111 Iflf6R RRDS TREG XCH
filII 1f11R RRDS TREG ASHC
f6111 Ilf6R RRDS TREG MUL
fll11 11lR RRDS TREG DIV
If6f1~ f6f1f1f6 DISP LACE BPL
Iflfl~ f6f6f11 DISP LACE BM!
Iflf6f1 f6f61f6 DISP LACE BHI
If6f6f1 f6f111 DISP LACE BLOS
If6f6f1 f61f6f6 DISP rACE BVC
Iflf6f1 ~lfll DISP !,.ACE BVS
l~flf6 f611f6 DISP LACE BCC, BRIS
Iflflf6 f6111 DISP LACE BCS, BLO
If1f1f6 1f6f6R EGflfI VALU SSRR
If6f6f6 If6f6R EGflI VALU SSLR
1f6f6f1 1f1f1R EGlf6 VALU SSRA
If6f6f1 1f6f1R EGll VALU SSLA
Iflflf6 Ifllfl flfIMO DREG RORB
Iflflf6 1~1f6 f6lMO DREG ROLB
If6f6f6 1~1f6 1f1MO DREG TSTB
If6~f6 1f61f6 11MO DREG ASLB
Iflflf6 1~11 flflMO DREG SETB
If6f6f1 1~11 ~lMO DREG CLRB
If6~f6 1~11 If6MO DREG ASRB
If6f1f1 1~11 llMO DREG SWAD
1f6f6f6 11f6f6 flflMO DREG COMB
If6f6f6 11f6f1 f6lMO DREG NEGB
If6f1f6 11f6f6 1f61«> DREG INCB
1f6f6f6 11f6f1 llMO DREG DECB

2
OP COOE MNEMONIC

l¢¢¢ l1¢l ¢¢MO OREG LSTS

l¢¢¢ 11f61 ¢lMO OREG SSTS
l¢¢¢ l1¢l l¢MO OREG ADC
l¢¢¢ ll¢l llMO OREG SBC
1¢¢¢ l1lR EG¢¢ VALU SORR
1¢¢¢ 111R E~l VALU SOLR
1¢¢¢ ll1R EG1¢ VALU SORA
1¢¢¢ 111R EGl1 VALU SOLA
l¢¢l SRCR EGOS TREG CMP
1¢1¢ SRCR EGOS TREG BIT
Ifill SRCR EGOS TREG MOV
l1~fI SRCR EGOS TREG CMPB
11f11 SRCR EGOS TREG MOVB
111¢ SRCR EGOS TREG BISB
1111 flfI~~ ISRC lOST FADO
1111 ~~fl1 ISRC ID.(3T FSUB
1111 fI~l~ lSRC lOST FMUL
1111 ~fl11 lSRC lOST FOIV
1111 fl1¢~ lSRC lOST FCMP
1111 ~1f11 lSRC lOST
1111 ~11¢ lSRC lOST
1111 ~111 lSRC lOST
1111 l~fI~ lSRC lOST
1111 1~~1 ISRC lOST
1111 1¢1~ lSRC lOST
1111 Ifill ISRC lOST
1111 l1¢fI lSRC lOST
1111 11~1 lSRC lOST
1111 111f1 lSRC lOST
1111 1111 lSRC lOST

3
 APPENDIX B

ASSEMBLER NOTES

FORMAT 1 OP CODES

All are one word op codes except SAVS which is a two word op
code. The second word of the SAVS op code is an absolute value.

FORMAT 2 OP CODES

All are one word with a 3 bit register argument

FORMAT 3 OP CODE

A one word op code with a 4 bit numeric argument

FORMAT 4 OP CODES

All are one word with a 6 bit numeric argument

FORMAT 5 OP CODES

All are one word with an 8 bit signed PC relative word o;~­
placement. The displacement is relative to op code+2. Maximum
displacement from the op code is +128, -127 words.

FORMAT 6 OP CODES

All are one word with a 3 bit register and a 4 bit numeric argu-
ment. The stored numeric argument is a positive number from ~ -"F"
that equals the actual numeric argument (l-"l~") minus one.

FORMAT 7 OP CODES

All are one word op codes for DM~ - DMS addressing and two word
op codes for DM6 - DM7 addressing. For DM6- DM7 addressing the off-
set is in the second word. If the index register is PC with DM6 -
DM7 the offset is relative to op code+4.

FORMAT 8 OP CODES

All are one word with a 3 bit source and a 3 bit destination reg-
ister argument. The count register is implied to be ~.

FORMAT 9 OP CODES

All have a 3 bit register argument with a 6 bit destination argu-

ment that allows D~ - DM7 addressing. For D~ - DMS a one word op code
is generated. For DM6 - DM7 a two word op code is generated with the
offset in word two. If the index register is PC with DM6-DM7 then the
offset is relative to op code+4.

1
FORMAT 10 OP CODES

All have a 6 bit source and a 6 bit destination argumentl that

allow S~ - SM7 and D~ - DM7 addressing. For S~ - SM5 and DM~ -
DMS combined addressing a one word op code is generated. For SM6-
SM7 or DM6 - DM7 but not both a two word op code is generated with
the offset in word two. If the field with mode 6 or 7 addressing
uses PC as the index register then the offset is relative to the op
code + 4. For SM6 - SM7 and DM6 - DM7 combined addressing a 3 word
op code is generated. Word two contains the source offset, and
word 3 contains the destination offset. For SM6 - SM7 with PC the
offset is relative to the op code + 4. For DM6 - DM7 with PC the
offset is relative to the op code + 6.
Any autoincrements/decrements in the source are fully comple-
ted before any destination decoding begins.
FORMAT 11 OP CODES

All are one word op codes with a 4 bit source and a 4 bit des-
tination argument. Each argument consists of a 3 bit register ar-
gument preceeded by a I bit indirect argument.

2
 APPENDIX C

PROGRAMMING NOTES

Several of the op codes and addressing modes have person-

ality peculiarities that the user should be aware of. Most of
these can be put to good use in particular situations. This
appendix attempts to list most of them.

lEN: This instruction allows one more instruction to begin ex-

ecution before enabling 12.

IDS: This instruction allows one more instruction to begin ex-

ecution before disabling 12. IDS is therefore interruptable.
If such a situation occurs the status of 12 that is included
in the pushed PC will equal ~.

HALT: There is no halt in the microcode. A selection of op-

tions is therefore (,iven that allows the user to define HALT for
himself •

ADDRESSING MODES

In order to clarify the function of the various address-

ing modes several programming examples are given. In each case
assume that the first word of the op code is at location X.

SET ~

~gister R~ is set to all ones.

CLR @R2

The memory location pointed to by R2 is cleared to zeros. If R2

contained a "~I[6~" the memory word address "[6I[6~" would be cleared.

INC (R3)+

The memory location pointed to by R3 is incremented by one. R3 is

then incremented by 2.

DEC (PC)+

Location X + 2 is decremented by one, and program control is ad-

vanced to location X + 4. This allows for in-line literals in a
program, a method that saves a word of memory in most cases.

SWAB @(R4)+

If R4 contains a "[61[6~" and location "[6I~~" contains a "[62[6[6" then

the two bytes in location "[62[6[6" are swapped and R4 is incremented
to "[61[62".

1
COM -(RS)

RS is decremented by two. The address specified by the altered R5

is one's complemented.

NEG - (PC)

A BOZO no-no since location X is the location negated and program

control is again transferred to locati~~ X after the negation is
completed.

TST @-(RI)

If R = "f.Jlf.J4" and location "f.Jlf.J2" contains a "1f.Jf.Jj3" then the following

sequence occurs: (1) RI is decremented by 2 to "131132". (2) The contents
of location "{6l{62" (i.e. "1{6f.Jf.J") becomes the address of the operand
to be tested.

ROR 4 (R4)

The contents of memory location R4 + 4 is rotated right. R4 is not

altered. Word two of this op code contains a 4. Program control is
advanced to location X + 4 at the completion of the rotate.

ROL @6(SP)

The contents ofmemoDY location SP + 6 contains the address of the

operand to be rotated. Word two of this op code contains a 6. Pro-
gram control is advanced to location X + 4 at the completion of the
rotate.

JSR PC, TAG

Location X + 2 contains the byte offset from location "TAG" to location

X + 4. The address of location X + 4 is pushed onto the stack, and the
address of location "TAG" is placed in PC.

JSR RS,TAG .

Location X + 2 contains the byte offset from location "TAG" to location

X + 4. The content of register RS is pushed onto the stack, the ad-
dress of location X + 4 is placed in RS, and the address of location
"TAG" is placed in PC.

JSR PC, (R4) +

Location X + 2 is pushed onto the stack, R4 is moved to PC, and R4 is

incremented by two.

JSR PC, @(~P)+

This is a co-routine call. Pay attention:

1) The contents of the location pointed to by SP is saved in CPU
register "TMPA".

2
2) SP is incremented by two.
3) The address of location X + 2 is pushed onto the stack
4) CPU register "TMPA" is moved to PC

The effect of all this is to swap the top word on the stack
with the address of location X + 2 without altering SP or stack size.
Consider the following routine.
SUBR: JSR PC,2(PC)
TAGA: JSR PC,@(PC)
TAGB:

RTN PC

The first JSR places the address of TAGA on the stack and exe-
cutes the routine starting at TAGB. The RTN PC transfers control
to location TAGA when it is executed. The second JSR places address
TAGB onto the stack-'nd into PC, effectively leaving PC unaltered.
The second time the RTN PC is executed program control passes to lo-
cation TAGB. The third time the R1~ PC is executed program control
passes back to the routine that call subroutine SUBR. Since TAGA
and TAGB are never addressed explicitly both of the labels could be
eliminated from the program. If left in then the "2(PC)" could be
replaced with "TAGB".

CMP (R¢) +, (R)2l) +

If R~ = "~l~~" then the contents of location "~l~W' is compared to

the contents of location "~102" , and F$ is incremented to "0l~4".
All source auto increments or decrements are completed before destin-
ation decoding begins.

MOV @R2,-(R2)

If R2 = "~l~6" then the contents of location "~l~6" is moved to lo-

cation "01~4", am3: R2 H; decremented to "01~4".
,.., ~. ,.. (' t<J'.':- .~,

BIT #2,@#4

The contents of absolute memory location 4 is tested against the lit-

eral value 2. This is a three word op code with word two containing
a 2 and word three containing a 4. This op code works on location 4
from anywhere in memory.

CMP (PC)+,TAG

This won't work. The assembler generates a two word op code for this
with the destination offset in word two. The execution of the op
code, however, uses word two as a literal and word three (which does
not exist) as the destination offset. By swapping the source and
destinations around then an in-line literal could be used for word
three, and word two would contain a valid source offset.

3
JSR PC, (PC) +

The address of location X + 4 is pushed onto the stack, and PC gets

the address of location X + 2.

JSR R5, (PC) +

The contents of R5 are pushed onto the stack, R5 gets the address of
location X + 4, and PC gets the address of location X + 2.

MOVB (RI1) +, (R¢} +.

If R¢ = "¢1¢2" then the contents of memory byte location n¢I¢2" is moved

to memory byte location "¢1¢3", and R¢ is incremented to "¢1¢4".

MOVB (SP)+,Rl

The contents of the memory byte addressed by SP is moved to the lower

byte of RI, the sign bit (bit 7) is replicated through bit 15 of Rl,
and SP is incremented by 2. SP is always autoincremented or autode-
cremented by two.

CLRB (Pc)+

The contents of the lower byte memory location X + 2 is cleared to

zeros. The upper byte (X + 3) is not affected. PC is incremented
by two. PC is always autoincremented or autodecremented by two.

BISB R¢, Rl

The lower bytes of register R¢ is logically ORED with the lower byte
of register RI. The upper byte of Rl is not altered.

MOVB @(~)+,@-(R3)

If R2 contains a "¢l¢¢" and R3 contains a "¢2¢W' then location n¢l¢¢n

contains the byte address of the source operand and location "¢IFE"
contains the address of the destination byte that is to receive the
source byte. R2 is incremented by two, and R3 is decremented by two
since they point to addresses of (16 bit) addresses.

JSR SP, TAG

Not recommended since the value of the stack is lost. Perfectly le-
gal however.

SAVS and RSTS

Although designed to be used for automatic register and I/O priority

level saving and restoring, the lack of hardware priority masking
does not alter the operation or the op codes. The SAVS op code is
usually the first instruction executed in a device interrupt routine,
and the RSTS is the last. The priority mask can use a one bit as an
enable or disable with bit ¢ the highest or lowest priority level.
Such decisions are made by the hardware.

4
 POWER FAIL

Two levels of power fail are provided for in the firmware. The
hardware may use two, one, or no levels of power fail.The three
modes are discussed in increasing order of complexity.

NO LEVELS: External address register bit 7 is hardwired to ~,

and a prayer is offered.

ONE LEVEL: The detection of a power fail sets bit 7 of the exter-
nal status register and the CPU RESET line. When the
power fail disappears the CPU RESET line is reset, but
bit 7 of the external status register remains set. The
Line Clock Clear State Code (see appendix D) clears
bit 7 of the external status register (and bits 5, 6
if used). A system power up is then executed.

TWO LEVELS: This req1 ires two hardware functions, AC LOW and DC
LOW, plus two levels of power fail; AC and DC. It
all works like this: If AC power begins to deterior-
ate AC LOW is set first. This sets bit 7 of the ex-
ternal status register and generates an interrupt via
I~ or II. If AC power does not deteriorate too far then
nothing else happens except that bit 7 of the external
status register is reset when power is restored. If
AC power continues to deteriorate then eventually DC
power will begin to deteriorate. When this happens
DC LOW is set and DC LOW sets CPU RESET. AC LOW is
still set and it maintains bit 7 of the external status
register. When power is restored DC LOW is reset. This
resets CPU RESET. A power up sequence is initiated, and
the Line Clock Clear State (see appendix D) clears The
External Status Register bi~ 7 (plus 5 and 6 if they are
used). If the user wishes to be able to execute a pro-
grammed power fail routine even during a sudden and com-
plete power failure then the DC power supply must be
strong enough to run the CPU and MEMORY for at l~ast 2
milliseconds. The power fail interrupt must also be
programmed, and the interrupts enabled.

The use of the Line Clock Clear State Code to clear bits 5-7 on
a CPU RESET function (plus the line clock of course) should have no
effect on normal system operation. Should an error occur during a
non-vectored interrupt the error would be cleared momentarily and then
set again as CPU RESET obviously could not have been generated. If it
had been then the system could not be in the non-vectored interrupt
routine.

PARITY AND BUS ERRORS

These functions are also part of the CPU RESET function along with
power fail/up. In order to get only one or the other then bit 7 of
the external status register must be reset when the CPU RESET function

5
is activated. In order to generate a valid CPU RESET the CPU
RESET line must be held active for three clock cycles. Longer is
fine, but the CPU goes into a wait state until the CPU RESET is
reset. If more than one error exists at one time then the highest
priority error is the one honored The priority, from highest to
lowest, is:
Power Fail
Bus Error
Parity Error

If all 3 functions are reset a power up is assumed. All 3 functlons

have a bit associated with them in the external status register. Once
set these bits stay set until cleared by the Line Clock Clear State
Code (see appendix D) that is generated during the first phases of
the reset routine. See chapter two "Power Up Options".

6
 APPENDIX D

MICROM STATE CODE FUNCTIONS

Below is a list of MICROM STATE CODE FUNCTIONS for the WD1600 with a
brief de.cription of what each does. More elaborate descriptions,
where necessary, follow the table.

CODE MNEMONIC FUNCTION

~~~l PMSK Priority mask out

~~l~ RUN Macro instruction fetch
~~ll IORST I/O reset
~l~ra INTEN 12 set
~l~l INTDS 12 reset
~ll~ ESRR External status register request
~lll SRS System reset
l~~~ BYT!. Read byte operation
lra~l RMWW Read-modify-write word
l~l~ RMWB Read-modify-write byte
l~ll RLCI Reset line clock interrupt
ll~~ EARR External address register request
11~1 Duplicate of "BYTE"
ll1~ Duplicate of "RMWW"
1111 Duplicate of "RMWB"

PMSK: The state code is generated on an OUTPUT WORD instruction when

a new mask is written into location "2E". It signals the I/O
devices that a new interrupt mask is on the DAL.

RUN: Generated during macro instruction fetch for a run light.

IORST: Generated during a RESET macro op code to reset I/O devices to

some preset state.

INTEN: Enables the interrupt enable line -12.

INTDS: Disables the interrupt enable line -12.

ESRR: Generated during an INPUT STATUS BYTE micro op code to indicate

that the external status register is being requested. See note 1.

SRS: Generated during a power up for a master system reset. This code
is followed by a 300 cycle wait to allow time for any reset func-
tions the hardware generates to be completed before any DAL re-
quests are generated.

BYTE: Generated during an INPUT BYTE micro op code to indicate a read

byte operation without a read-modify-write.

RMWW: Generated d~ing an INPUT WORD micro op code with RMW active to
indicate a read-modify-write word sequence.

RMWB: Generated during an INPUT BYTE micro op code with BMW active to
indicate a read-modify-write byte sequence.

1
RLCI: Generated during a CPU RESET or a non-vectored interrupt with-
out a power fail to clear both the line clock interrupt and ex-
ternal status register bits 5-7.

EARR: Generated during an INPUT STATUS BYTE micro op code to. indicate
a request for the external address register during the user boot-
strap routine.

CODES "D" - "F": Duplicates of codes "8" - "A" respectively except that
these codes appear as a part of the READ micro op codes
instead of as a part of the INPUT micro op codes. Either
or both may be used by the hardware as is convenient.
These codes preceed the others. They are generated only
once, however, instead of repeating in the event of a
wait state as the others do.

NOTE 1: INPUT STATUS BYTE is not a function of reply and does not gen-
erate a SYNC. For these reasons the DAL must be tri-stated if
a DMA device also exists. The data is always gated onto the low-
er byte. The upper byte is ignored.

NOTE 2: Lack of state codes "8" - "A" or "D" - "F" during a READ - INPUT
sequence implies a read word operation without read-modify-write.

2
 APPENDIX E

OP CODE TIMINGS

All times are in cycles. Timings include all OP Code fetches,

memory reads, and memory writes applicable to each. Timings
assume that the memory is running with full speed with respect to
the CPU. This requires a 16 Bit access time = 1 CPU cycle, and a
16 Bit memory read/write cycle time = 2 CPU cycles. One CPU cycle =
300 NS @ 3.3 MHZ, U~~ NS @ 2.5 MHZ, and 500 NS @ 2 MHZ clock rates.
Timings are included for SM~ and D~ as basic with additions as
necessary in tables that follow the OP Codes for SMl-7 and DMl-7
timings.

FORMAT ONE OP CODES

OP CODE # CYCLES

NOP l~
RESET l~
lEN l~
IDS l~
HALT 16+
XCT 44 + OP CODE EXECUTED
BPT 24
WFI 16+
RSVC 62
RRTl' 60
S.AVE 46
SAVS 65
REST 48
RRTN 52
RSTS 64
RTT 13

FORMAT TWO-FOUR OP CODES

OP CODE # CYCLES

IAK l~
RTN 12
MSKO lSl
PRTN 22
LeC 7
SVCA 37
SVCB 73
SVCC 71

FORMAT FIVE OP CODES

All branches = 9 cycles if brancn occurs or not.

1
 FORMAT SIX OP CODES

OP CODE # CYCLES

ADD I 9
SUBI 9
BICI 9
MOVI 9
SSRR 8 + (5 X # bits shifted)
SSLR 8 + (5 X # bits shifted)
SSRA 8 + (7 X # bits shifted)
SSLA 8 + (5 X # bits shifted)
SDRR 20 + (7 X # bits shifted)
SDLR 20 + (7 X # bits shifted)
SDRA 20 + (9 X # bits shifted)
SDLA 20 + (7 X 3 bits shifted)

FORMAT 7 OP CODES - DM~

OP CODES # CYCLES OP CODES # CYCLES

ROR 1~ RORB 9
ROL 1~ ROLB 9
TST 1~ TSTB 9
ASL 1~ ASLB 9
SET 1~ SETB 1$6
CLR 1~ CLRB 9
ASR 12 ASRB 11
SWAB 1$6 SW:1J;) 21
COM 1~ COMB 9
NEG 1$6 NEGB 9
INC 1~ INCB 9
DEC 1~ DECB 9
IW2 1~ LSTS 15
SXT 12 SSTS 1$6
TCALL 21 ADC 11
TJMP 16 SBC 11

FOR WORD OPS AND: FOR BYTE OPS AND:

DMI ADD 4 DMI ADD 3

DM2 ADD 4 DM2 ADD 3 *
DM3 ADD 8 DM3 ADD 7
DM4 ADD 6 DM4 ADD 5 *
DMS ADD 1~ DMS ADD 9
DM6 ADD 1~ DM6 ADD 9
DM7 ADD 14 DM7 ADD 13

For DM1 - DM7 and:

CLR subtract 1 cycle

SWAB subtract 1 cycle *NOTE: Add 2 more if SP or PC.

2
 FORMAT 8 OP CODES

OP CODE #: CYCLES (ASSUMES NO INTERRUPTS)

MBWU 17 + (16 X #: words moved)

MBWD 15 + (16 X # words moved)
MBBU 17+ (15 X #: bytes moved)
MBBD 15 + (15 X #: bytes moved)
MBWA 19 + (16 X #: words moved)
MBBA 19 + (15 X # bytes moved)
MABW 19 + (16 X #: words moved)
MABB 19 + (15 X #: bytes moved)

FORMAT 9 OP CODES - D~

OP CODE #: CYCLES

JSR* 22
LEA * 15
ASH 19 if DST = fi1; 22 + (5 X count) if DST>¢; 25+ (7 X count) if DST < ¢.
SOB lfi1 if no branch, 13 if branCh
XCH 23
ASHC 19 if DST = fi1; 38 + (7 X count) if DST>¢; 38+ (9 X count) if DST < ¢
MUL 183
DIV 29 if divisor error, 2fi12 if no divisor error

*NOTE: DM~ illegal. Used as base figure only.

FOR ALL OP CODES EXCEPT SOB AND:

DM1 add fi1

DM2 add 2
DM3 add 2
DM4 add 2
DM5 add 4
DM6 add 4
DM7 add 8

FORMAT lfi1 OP CODES - SM{i1 AMD D¥fi1

OP CODE #: CYCLES

ADD 11
SUB 11
AND 11
BIC 11
BIS 11
XOR 11
CMP 11
BIT 11
MOV 11
CMPB 11
MOVB 12
BISB 11

3
For SM1: add 3 for word ops, 1 for byte ops.
For SM2: add 4 for word ops, 2 for byte ops. *
For SM3; add 7 for word ops, 5 for byte ops.
For SM4; add 5 for word ops, 3 for byte ops. *
For SM5; add 9 for word ops, 7 for byte ops.
For SM6'; add 9 for word ops, 7 for byte ops.
For SM7; add 13 for word ops, 11 for byte ops.

For DM1;add 4 for word ops, 3 for byte ops.

For DM2;add 4 for word ops, 3 for byte ops. *
For DM3;add 8 for word ops, 7 for byte ops.
For DM4;add 6 for word ops, 5 for byte ops. *
For DM5;add l.0for word ops, 9 for byte ops.
For DM6;add l.0for word ops', 9 for byte ops.
For DM7iadd 14for word ops, 13 for byte ops.

For MOVB and DM1-DM7 subtract 1 cycle.

*NOTE: Add 2 if SP or PC

FORMAT 11 OP CODES - ALL ADDRESSING MODES

FADD: If exponent difference> 39 138-145

Worst Case 638
Typical 180-420

FSUB: If exponent difference > 39 141-148

Worst Case 641
Typical 190-430

FMUL: If either operand = f1 108-111

Worst Case 805
Typical 590-780

FDIV: If divide by .0 96
If divide into fl 118
Worst Case 1596
Typical 280-1210

FCMP: 49-86

4
- NOTES -
- NOTES -