Course – Computer Organization and

Architecture

Course Instructor
Dr. Umadevi V
Department of CSE, BMSCE

1
16 October 2024 CSE, BMSCE
 Unit-2

Stacks, Subroutines, Additional Instructions

Basic Input/Output: Accessing I/O Devices, Interrupts, Bus
Structure, Bus Operation, Arbitration

16 October 2024 CSE, BMSCE 2

 Stacks

16 October 2024 CSE, BMSCE 3

Stack
 A stack is a special type of data structure where elements are inserted from one end and elements are deleted
from the same end. This end is called the top of the stack
 The various operations performed on stack:
◼ Insert: An element is inserted from top end. Insertion operation is called push operation.
◼ Delete: An element is deleted from top end. Deletion operation is called pop operation.
 A processor-register is used to keep track of the address of the element of the stack that is at the top at any given
time. This register is called the Stack Pointer.
 If we assume a byte-addressable memory with 32-bit word length
◼ The Push operation can be implemented as
Subtract SP, SP, #4
Store Rj, (SP)
◼ The Pop operation can be implemented as
Load Rj, (SP)
Add SP, SP, #4

16 October 2024 CSE, BMSCE 4

Stack: Push Operation Implementation
Subtract SP, SP, #4
Store R1, (SP)
Before Executing the Instruction After Executing the Instruction
Memory Memory
4 Bytes 4 Bytes

Memory Memory
Address Contents Address Contents
3016 3016
3020 SP 3020 6
SP 3024 28 3024 28

R1 6 R1 6

SP(StackPointer) 3024 SP 3020

16 October 2024 CSE, BMSCE 5
Stack: Pop Operation Implementation
Load R1, (SP)
Add SP, SP, #4
Before Executing the Instruction After Executing the Instruction
Memory Memory
4 Bytes 4 Bytes

Memory Memory
Address Contents Address Contents
3016 3016
SP 3020 6 3020 6
3024 28 SP 3024 28

R1 19 R1 6

SP(StackPointer) 3020 SP 3024

16 October 2024 CSE, BMSCE 6
Question
Register R5 is used in a program to point to top of a stack. Consider each word length in stack is of 32-bits.Write a sequence of
instructions to perform each of the following
a. Pop the top two items off the stack, add them and then push the result onto the stack.
b. Copy the fifth item from the top of the stack into register R3
c. Remove the top ten items from stack 4 Bytes
Address Memory Contents
3000 10
R5
3004 20

3008 00
3012 40
3016 50
3020 60
Note: 3024 70
Push operation can be implemented as
Subtract SP, SP, #4
3028 80
Store Rj, (SP) 3032 90
Pop operation can be implemented as
Load Rj, (SP) 3036 100
Add SP, SP, #4
3040
16 October 2024 CSE, BMSCE 7
Answer
Register R5 is used in a program to point to top of a stack. Consider each word length in stack is of 32-bits.Write a sequence of
instructions to perform each of the following
a. Pop the top two items off the stack, add them and then push the result onto the stack.
b. Copy the fifth item from the top of the stack into register R3 Contents of Memory after executing set of instruction

c. Remove the top ten items from stack 4 Bytes

a. Address Memory Contents
Load R1, (R5) ; Pop 3000 10
Add R5, R5, #4
R5 3004 30
Load R2, (R5) ; Pop
Add R5, R5, #4 3008 00
Add R3, R1, R2 ; Add 3012 40
Subtract R5, R5, #4 ; Push 3016 50
Store R3, (R5)
3020 60
Note: 3024 70
Push operation can be implemented as
Subtract SP, SP, #4
3028 80
Store Rj, (SP) 3032 90
Pop operation can be implemented as
Load Rj, (SP) 3036 100
Add SP, SP, #4
3040
16 October 2024 CSE, BMSCE 8
Answer
Register R5 is used in a program to point to top of a stack. Consider each word length in stack is of 32-bits.Write a sequence of
instructions to perform each of the following
a. Pop the top two items off the stack, add them and then push the result onto the stack.
b. Copy the fifth item from the top of the stack into register R3 Contents of Memory after executing set of instructions

c. Remove the top ten items from stack 4 Bytes

b. Address Memory Contents
Load R3, 16(R5) 3000 10
R5
3004 20

3008 00

R3 3012 40
3016 50
50
3020 60
Note: 3024 70
Push operation can be implemented as
Subtract SP, SP, #4
3028 80
Store Rj, (SP) 3032 90
Pop operation can be implemented as
Load Rj, (SP) 3036 100
Add SP, SP, #4
3040
16 October 2024 CSE, BMSCE 9
Answer
Register R5 is used in a program to point to top of a stack. Consider each word length in stack is of 32-bits.Write a sequence of
instructions to perform each of the following
a. Pop the top two items off the stack, add them and then push the result onto the stack.
b. Copy the fifth item from the top of the stack into register R3 Contents of Memory after executing set of instruction

c. Remove the top ten items from stack 4 Bytes

C. Address Memory Contents
Add R5, R5, #40 3000 10

3004 20

3008 00
3012 40
3016 50
3020 60
Note: 3024 70
Push operation can be implemented as
Subtract SP, SP, #4
3028 80
Store Rj, (SP) 3032 90
Pop operation can be implemented as
Load Rj, (SP) 3036 100
Add SP, SP, #4
R5 3040
16 October 2024 CSE, BMSCE 10
Subroutines

16 October 2024 CSE, BMSCE 11

Subroutine Linkage using a Link register

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 Subroutine: Program to add n numbers
Subroutine
LISTADD Address
Main
Address Program Clear R3 2000
3000 Load R2, N Loop: Load R5, (R4) 2004
3004 Move R4, #Num1
Add R3, R3, R5 2008
3008 Call LISTADD
3012 Store R3, Sum Add R4, R4, #4 2012

Subtract R2, R2, #1 2016

Memory
4 Bytes Address Branch_if_[R2] > 0 LOOP 2020
N 4 1000 Return 2024
Sum 1004
Num1 2 1008
Num2 1 1012
Num3 3 1016
Num4 10 1020
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Subroutine Nesting

16 October 2024 CSE, BMSCE 14

Subroutines: Parameter Passing
 The exchange of information between a calling program and a
subroutine is referred to as Parameter passing.
 The parameters may be passed using
◼ Registers
◼ Memory Location
◼ Stack

16 October 2024 CSE, BMSCE 15

 Subroutine: Passing of Parameters through Register and Memory Location
Subroutine
LISTADD Address
Main Subtract SP, SP, #4 2000
Address Program
Store R5, (SP) 2004
3000 Load R2, N Clear R3 2008
3004 Move R4, #Num1 Loop: Load R5, (R4) 2012
3008 Call LISTADD Add R3, R3, R5 2016
Add R4, R4, #4 2020
3012 Store R3, Sum
Subtract R2, R2, #1 2024
Memory Branch_if_[R2] > 0 LOOP 2028
4 Bytes Address
Load R5, (SP) 2032
N 4 1000 Add SP, SP, #4 2036
Sum 1004 Return 2040
In calling program,
Num1 2 1008 Register R2 and R4 is used to pass the parameters N and
address of Num1 location
Num2 1 1012
- N is passed using: Pass by Value
Num3 3 1016 - Address of Num1 is passed using: Pass by Reference.

Num4 10 1020 The called Subroutine: LISTADD, returns the parameter

total value through the register R3
16 October 2024 CSE, BMSCE 16
 Subroutine LISTADD

Subroutine: Passing of Parameters through Stack

Main Program

16 October 2024 CSE, BMSCE 17

 Subroutine LISTADD

3012

3016

3020

3024

3028
R2
3032
R3 100
3036
R4 200
SP
3040 3040
R5 300
18
Stack Frame
 Stack Frame refers to locations that constitute a private work-space for the subroutine.
 The work-space is
◼ Created at the time the subroutine is entered and
◼ Freed up when the subroutine returns the control to the calling program
Figure shows an example of a commonly used layout for information in a stack
frame. In addition to the Stack Pointer(SP), it is useful to have another pointer register, called
the Frame Pointer (FP), for convenient access to the parameters passed to the subroutine and
to the local memory variables used by the subroutine. In the figure, we assume that four
parameters are passed to the subroutine, three local variables are used within the subroutine,
and registers R2, R3, and R4 need to be saved because they will also be used within the
Subroutine.

16 October 2024 CSE, BMSCE 19

 Additional Instructions

So far, we have learned the following instructions:

Load, Store, Move, Clear, Add, Subtract, Branch, Call, and Return.

Next we will learn few more instructions that are found in most instruction sets.

16 October 2024 CSE, BMSCE 20

Logic Instructions
 Logic operations such as AND, OR, and NOT are applied to individual bits.
 For example, the instruction
And R4, R2, R3
computes the bit-wise AND of operands in registers R2 and R3, and leaves the result in R4.

 An immediate form of this instruction may be

And R4, R2, #Value
where Value is a 16-bit logic value that is extended to 32 bits by placing zeros into the 16
most-significant bit positions.

16 October 2024 CSE, BMSCE 21

Logic Instruction: Example

And R4, R2, R3

Before Executing the Instruction After Executing the Instruction

R3 R3
1 0 0 1 0 1 0 1 1 0 0 1 0 1 0 1

R2 R2
1 0 1 0 0 1 1 0 1 0 1 0 0 1 1 0

R4 R4

0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0

16 October 2024 CSE, BMSCE 22

Question
Suppose that four ASCII characters are contained in the 32-bit register R2. In some task, we
wish to determine if the rightmost character is Z. If it is, then a conditional branch to FOUNDZ is
to be made. Write sequence of instructions for this task

ASCII Hex Character ASCII Hex Character

value value
0x41 A 0x4A J
0x42 B ….. …..

0x43 C 0x59 X

… … 0x5A Z

16 October 2024 CSE, BMSCE 23

Hexadecimal numbers
 A group of 4 bits can take any value between 0 (0000 binary) and 15 (1111 binary).
 In hexadecimal, we replace each group of 4 bits with a single digit to represent the value 0 to 15. Since we only have digits 0 to 9, we use
letters A to E to represent values 10 to 15. Here is a table of binary, denary and hex values:

Note: To specify
Hexadecimal numbers
Prefix 0x will be used
i.e.,
0x123
or
123h

16 October 2024 CSE, BMSCE 24

Question
Suppose that four ASCII characters are contained in the 32-bit register R2. In some task, we
wish to determine if the rightmost character is Z. If it is, then a conditional branch to FOUNDZ is
to be made. Write sequence of instructions for this task

ASCII Hex Character ASCII Hex Character

value value
0x41 A 0x4A J
0x42 B ….. …..

0x43 C 0x59 X

… … 0x5A Z

16 October 2024 CSE, BMSCE 25

Answer
Suppose that four ASCII characters are contained in the 32-bit register R2. In some task, we wish to determine if the
rightmost character is Z. If it is, then a conditional branch to FOUNDZ is to be made. Write sequence of instructions for
this task.

And R2, R2, #0xFF

ASCII Hex Character ASCII Hex Character
Move R3, #0x5A value value
Branch_if_[R2]=[R3] FOUNDZ
0x41 A 0x4A J
0x42 B ….. …..

0x43 C 0x59 X

… … 0x5A Z

16 October 2024 CSE, BMSCE 26

Shift Instructions
Shift Instructions

Logical Arithmetic

Left Right Left Right

16 October 2024 CSE, BMSCE 27

Logical Left Shift Instruction
C 0
MSB LSB
LShiftL, shifts the contents of register Rj left by a number of bit positions given by
Logical Left Shift the count operand, and places the result in register Ri, without changing the contents of Rj.
General Syntax: LShiftL Ri, Rj, Count During shift, bits are passed through the Carry flag, C, and then dropped.

LShiftL R1, R2 , #2
Before Executing the Instruction After Executing the Instruction

R2 R2
1 0 1 0 1 1 0 1 1 0 1 0 1 1 0 1

C R1 C R1
0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 1 0 0

16 October 2024 CSE, BMSCE 28

Logical Left Shift Instruction

C 0
MSB LSB
Logical Left Shift
General Syntax: LShiftL Ri, Rj, Count
LShiftL R1, R1 , #2
Before Executing the Instruction After Executing the Instruction
C R1 C R1
0 1 0 1 0 1 1 0 1 1 0 1 0 1 1 0 1 0
After 1st Shift

C R1
0 1 0 1 1 0 1 0 0
After 2nd Shift

16 October 2024 CSE, BMSCE 29

 Logical Right Shift Instruction
0 C
MSB LSB
Logical Right Shift
General Syntax: LShiftR Ri, Rj, Count

LShiftR R1, R1, #2

Before Executing the Instruction After Executing the Instruction
R1 C R1 C
1 0 1 0 1 1 0 1 0 0 1 0 1 0 1 1 0 1
After 1st Shift

R1 C
0 0 1 0 1 0 1 1 0
After 2nd Shift

16 October 2024 CSE, BMSCE 30

Question

The content of a 4-bit register is initially 1101. The register

is logically shifted 2 times to the right. What is the content
of the register after each shift?
a. 1110, 0111
b. 0001, 1000
c. 1101, 1011
d. 0110, 0011

16 October 2024 CSE, BMSCE 31

Question

The content of a 4-bit register is initially 1101. The register

is logically shifted 2 times to the right. What is the content
of the register after each shift?
a. 1110, 0111
b. 0001, 1000
c. 1101, 1011
d. 0110, 0011

16 October 2024 CSE, BMSCE 32

Question

If a register containing data 11001100 is subjected to

logical shift left operation of 1 bit, then the content of the
register after 'LshiftL' shall be
a. 01100110
b. 10011001
c. 11011001
d. 10011000

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Answer

If a register containing data 11001100 is subjected to

logical shift left operation of 1 bit, then the content of the
register after 'LshiftL' shall be
a. 01100110
b. 10011001
c. 11011001
d. 10011000

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Question
Suppose that two decimal digits represented in ASCII code are located in the memory at byte locations LOC and LOC +
1. We wish to represent each of these digits in the 4-bit BCD code and store both of them in a single byte location
PACKED. The result is said to be in packed-BCD format. Write sequence of instructions for this task.
Hint: Use shift and logic instructions. Consider in memory, each memory location capacity is one of byte.
ASCII Hex Number
value
0x31 1
0x32 2

0x33 3

… …

0x39 9

LOC 0x39

LOC+1 0x32

Note: Binary Coded Decimal system(BCD): Each decimal digit is represented by a group of 4 bits. PACKED 92

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Answer
Suppose that two decimal digits represented in ASCII code are located in the memory at byte locations LOC and LOC +
1. We wish to represent each of these digits in the 4-bit BCD code and store both of them in a single byte location
PACKED. The result is said to be in packed-BCD format. Write sequence of instructions for this task.
Hint: Use shift and logic instructions. Consider in memory, each memory location capacity is one of byte.
Move R2, #LOC ASCII Hex Number
Load R3, (R2) value
LShiftL R3, R3, #4 ;Shift left by 4-bit position 0x31 1
Add R2, R2, #1 0x32 2
Load R4, (R2) 0x33 3
And R4, R4, #0xF ;Clear high-order bits to zero.
… …
Or R3, R3, R4 ;Concatenate the BCD digits.
Store R3, PACKED 0x39 9

LOC 0x39

LOC+1 0x32

PACKED 92

16 October 2024 CSE, BMSCE 36

 Arithmetic Right Shift Instruction

C
MSB LSB

RShiftR R1, R1, #2

Before Executing the Instruction After Executing the Instruction
R1 C R1 C
1 0 1 0 1 1 0 1 0 1 1 0 1 0 1 1 0 1
After 1st Shift

R1 C
1 1 1 0 1 0 1 1 0
After 2nd Shift

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Rotate Instructions
Rotate Instructions

With Carry Without Carry

Left Right Left Right

16 October 2024 CSE, BMSCE 38

Rotate Left with Carry

C
MSB LSB

RotateLC R1, R1, #1

Before Executing the Instruction After Executing the Instruction

C R1 C R1
0 1 0 1 1 0 1 0 0 1 0 1 1 0 1 0 0 0

16 October 2024 CSE, BMSCE 39

Rotate Left without Carry

C
MSB LSB

RotateL R1, R1, #1

Before Executing the Instruction After Executing the Instruction

C R1 C R1
0 1 0 1 1 0 1 0 0 1 0 1 1 0 1 0 0 1

16 October 2024 CSE, BMSCE 40

Rotate Right with Carry

C
MSB LSB

RotateRC R1, R1, #1

Before Executing the Instruction After Executing the Instruction

R1 C R1 C
1 0 1 1 0 1 0 0 0 0 1 0 1 1 0 1 0 0

16 October 2024 CSE, BMSCE 41

Rotate Right without Carry

C
MSB LSB

RotateL R1, R1, #1

Before Executing the Instruction After Executing the Instruction

R1 C R1 C
1 0 1 1 0 1 0 0 0 0 1 0 1 1 0 1 0 0

16 October 2024 CSE, BMSCE 42

Multiplication and Division Instructions

 Signed integer multiplication of n-bit numbers produces a

product with up to 2n bits
 Processor truncates product to fit in a register:
Multiply Rk, Ri, Rj (Rk  [Ri]  [Rj])
 For general case, 2 registers may hold result
 Integer division produces quotient as result:
Divide Rk, Ri, Rj (Rk  [Ri] / [Rj])
 Remainder is discarded or placed in a register

16 October 2024 CSE, BMSCE 43

Example for Multiplication instruction

Multiply R2 , R3, R4 ; R2 ← [R3] x [R4]

Before Executing the Instruction After Executing the Instruction

R2 76 R2 20
R3 10 R3 10
R4 2 R4 2

16 October 2024 CSE, BMSCE 44

Example for Divide instruction

Divide R2 , R3, R4 ; R2 ← [R3] / [R4] , Quotient in register R2 and Remainder in R1

Before Executing the Instruction After Executing the Instruction

R1 38 R1 0
R2 76 R2 5
R3 10 R3 10
R4 2 R4 2

16 October 2024 CSE, BMSCE 45

 Basic Input/Output

Accessing I/O Devices

Interrupts
Bus Structure
Bus Operation
Arbitration

16 October 2024 CSE, BMSCE 46

Accessing Input/Output (I/O) Devices
The components of a computer system communicate with each other through an interconnection network,
as shown in Figure.
The interconnection network consists of circuits needed to transfer information between the processor, the
memory unit, and a number of I/O devices.
Each I/O device is assigned a unique set of addresses

16 October 2024 CSE, BMSCE 47

Addressing Techniques of I/O Devices

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Addressing Techniques of I/O Devices
1. Memory mapped I/O

2. I/O (or Isolated) mapped I/O

16 October 2024 CSE, BMSCE 49

I/O Device Interface
 An I/O device interface is a circuit between a device and the interconnection network
 Provides the means for data transfer and exchange of status and control information
 Includes data, status, and control registers accessible with Load and Store instructions
 Memory-mapped I/O enables software to view these registers as locations in memory

16 October 2024 CSE, BMSCE 50

Registers in the Keyboard and Display interface

16 October 2024 CSE, BMSCE 51

Basic Input/Output Operations
We have seen instructions to:
Transfer information between the processor and the memory.
Perform arithmetic and logic operations
Program sequencing and flow control.
Input/Output operations which transfer data from the processor or memory to and from the real world are essential.
In general, the rate of transfer from any input device to the processor, or from the processor to any output device is likely to the slower
than the speed of a processor.
The difference in speed makes it necessary to create mechanisms to synchronize the data transfer between them

Speed:
Processor Many Million Instructions
Per Second

Speed: Several
Memory I/O Device Speed:
Thousand I/O Device Speed: Several
Few Hundred
Characters
Characters Characters
Per Second
Per Second Per Second

16 October 2024 CSE, BMSCE 52

Modes of I/O Data Transfer

Data transfer between the central unit and I/O devices can
be handled in generally three types of modes which are
given below:
1. Program Controlled I/O
2. Interrupt Initiated I/O
3. Direct Memory Access

16 October 2024 CSE, BMSCE 53

Three modes of I/O data transfer
Programmed I/O
 Programmed I/O instructions are the result of I/O instructions written in computer program. Each data item transfer is initia ted by the instruction in the
program.
 Usually the program controls data transfer to and from CPU and peripheral (I/O devices). Transferring data under programmed I/O requires constant
monitoring of the peripherals by the CPU.
Interrupt Initiated I/O
 In the programmed I/O method the CPU stays in the program loop until the I/O unit indicates that it is ready for data transfe r. This is time consuming
process because it keeps the processor busy needlessly.
 This problem can be overcome by using interrupt initiated I/O. In this when the interface determines that the peripheral is ready for data transfer, it
generates an interrupt. After receiving the interrupt signal, the CPU stops the task which it is processing and service the I/O transfer and then returns
back to its previous processing task.
Direct Memory Access
 Removing the CPU from the path and letting the peripheral device manage the memory buses directly would improve the speed of transfer. This
technique is known as DMA.
 In this, the interface transfer data to and from the memory through memory bus. A DMA controller manages to transfer data between peripherals and
memory unit.
 Many hardware systems use DMA such as disk drive controllers, graphic cards, network cards and sound cards etc. It is also used for intra chip data
transfer in multicore processors. In DMA, CPU would initiate the transfer, do other operations while the transfer is in progr ess and receive an interrupt
from the DMA controller when the transfer has been completed.

16 October 2024 CSE, BMSCE 54

Program Controlled I/O

 Let us consider a simple task of reading a character from a keyboard and displaying that
character on a display screen.
 A simple way of performing the task is called program-controlled I/O.
 There are two separate blocks of instructions in the I/O program that perform this task:
◼ One block of instructions transfers the character into the processor.
◼ Another block of instructions causes the character to be displayed.

16 October 2024 CSE, BMSCE 55

Program Controlled I/O:
Data Transfer from Input device to Processor
Monitor
Keyboard

Processor

R5

Keyboard interface Display interface

16 October 2024 CSE, BMSCE 56

Program Controlled I/O:
Data Transfer from Input device to Processor
Monitor
Keyboard

Processor

R5

Keyboard interface Display interface

READWAIT Read the KIN flag

Branch to READWAIT if KIN = 0
Transfer data from KBD_DATA to R5

16 October 2024 CSE, BMSCE 57

Program Controlled I/O:
Data Transfer from Input device to Processor
Monitor
Keyboard

Processor

R5

Keyboard interface Display interface

READWAIT: LoadByte R4, KBD_STATUS

And R4, R4, #2
Branch_if_[R4]=0 READWAIT
LoadByte R5, KBD_DATA

16 October 2024 CSE, BMSCE 58

Program Controlled I/O:
Data Transfer from Input device to Processor
Monitor
Keyboard

Processor

R5

Keyboard interface Display interface

WRITEWAIT Read the DOUT flag

Branch to WRITEWAIT if DOUT = 0
Transfer data from R5 to DISP_DATA

16 October 2024 CSE, BMSCE 59

Program Controlled I/O:
Data Transfer from Input device to Processor
Monitor
Keyboard

Processor

R5

Keyboard interface Display interface

WRITEWAIT: LoadByte R4, DISP_STATUS

And R4, R4, #4
Branch_if_[R4]=0 WRITEWAIT
StoreByte R5, DISP_DATA

16 October 2024 CSE, BMSCE 60

RISC-style program that reads a line of characters and displays it

16 October 2024 CSE, BMSCE 61

Rough slide to explain:
RISC-style program that reads a
line of characters and displays it

Monitor
Character ASCII Hexacode Keyboard
A 0x41
B 0x42
C 0x43
Memory
D 0x44
E 0x45
F 0x46
…. ….
Enter Key 0x0D
or Carriage
Return

16 October 2024 CSE, BMSCE 62

 Rough slide to explain: Monitor
Keyboard
RISC-style program that reads a
line of characters and displays it

Memory
Move R2, #LOC

MoveByte R3, #0x0D

READ: LoadByte R4, KBD_STATUS
And R4, R4, #2
Branch_if_[R4]=0 READ
LoadByte R5, KBD_DATA

StoreByte R5, (R2)

Add R2, R2, #1
ECHO: LoadByte R4, DISP_STATUS
And R4, R4, #4
Branch_if_[R4]=0 ECHO
StoreByte R5, DISP_DATA
Branch_if_[R5]≠[R3] READ

16 October 2024 CSE, BMSCE 63

Modes of I/O Data Transfer

Data transfer between the central unit and I/O devices can
be handled in generally three types of modes which are
given below:
1. Program Controlled I/O
2. Interrupt Initiated I/O
3. Direct Memory Access

16 October 2024 CSE, BMSCE 64

Disadvantage of Program Controlled I/O

 Under Program Controlled I/O, the program enters a wait loop in which it repeatedly
tests the device status. During this period, the processor is not performing any useful
computation. There are many situations where other tasks can be performed while waiting
for an I/O device to become ready.

READWAIT: LoadByte R4, KBD_STATUS

And R4, R4, #2
Branch_if_[R4]=0 READWAIT
LoadByte R5, KBD_DATA
Keyboard interface

16 October 2024 CSE, BMSCE 65

Interrupt based Data transfer between I/O device and Processor

16 October 2024 CSE, BMSCE 66

What is Interrupt ?
 Drawback of a Program controlled I/O: Wait-loop
 Instead of using wait-loop, let I/O device alert the processor when it is ready.
 Hardware sends an interrupt-request signal to the processor at the appropriate time, much like a
phone call.
 Interrupt is a mechanism used by most processors to handle asynchronous type of events.
 Essentially, the interrupts allow devices to request that the processor stops what it is currently doing
and executes software (called Interrupt Service Routine) to process the device’s request, much like a
Subroutine call that is initiated by the external device rather than by the program running on the
processor.
 Interrupts are also used when the processor needs to perform a long-running operation on some I/O
device and wants to be able to do other work while waiting for the operation to complete.

16 October 2024 CSE, BMSCE 67

 Interrupt mechanism for data transfer between I/O device and processor
3. Processor finishes the execution the
Processor current instruction i.e. Add R3,R4, R1
Saves the return address i.e.,1002
on the stack and changes Interrupt Service Subroutine (ISR) of KBD
Main program PC contents to 2000.
1000 And also sends interrupt acknowledgement to
2000 /*Saving the register
KBD contents on to the stack
1001 Add R3,R4, R1
that Will be altered by ISR*/
1002 Multiply R6,R7, R8

4. Execution of ISR ……. …..

2. Interrupt Signal given to Processor
2010 LoadByte R5, KBD_DATA
5. Returning to
KBD Interface Circuit Main program i.e.,
2011 StoreByte R5, LOC
KBD_DATA Changing PC contents to 1002
0x38 2012 /*Restore the registers
saved on the stack*/
1. User Pressing the key 8
2013 Return

16 October 2024 CSE, BMSCE 68

Interrupt Latency
 The information that needs to be saved and restored typically includes the condition code
flags and the contents of any registers used by both the interrupted program and the
interrupt-service routine.
 Saving registers also increases the delay between the time an interrupt request is received
and the start of execution of the interrupt-service routine. The delay is called interrupt
latency.
 Typically, the processor saves only the contents of the program counter and the processor
status register. Any additional information that needs to be saved must be saved by
program instruction at the beginning of the interrupt-service routine and restored at the end
of the routine

16 October 2024 CSE, BMSCE 69

Difference between Subroutine and Interrupt Service Routine (ISR)

16 October 2024 CSE, BMSCE 70

Question
Consider the case of a single interrupt request from one device. The device keeps interrupt request signal
activated until it is informed that the processor has accepted its request. This activated signal, if not
deactivated, may lead to successive interruptions causing the system to enter infinite loop.
Think, what measures the processor can take to avoid “successive interruptions causing the system to
enter infinite loop”

16 October 2024 CSE, BMSCE 71

Rough Slide to Explain the Question
Consider the case of a single interrupt request from one device. The device keeps interrupt request signal
activated until it is informed that the processor has accepted its request. This activated signal, if not
deactivated, may lead to successive interruptions causing the system to enter infinite loop.
Think, what measures the processor can take to avoid “successive interruptions causing the system to
enter infinite loop”
Device
Processor

16 October 2024 CSE, BMSCE 72

Rough slide to explain Answer:
Enabling and Disabling Interrupts

One mechanisms to avoid “successive interruptions causing the system to enter infinite loop” problem is as follows:
Processor automatically disabling the interrupts before staring the execution of ISR
The second option, which is suitable for a simple processor with only one interrupt-request line, is to have the processor automatically disable interrupts before
starting the execution of the interrupt-service routine. After saving the contents of the PC and the processor status register (PS) on the stack, the processor
performs the equivalent of executing an Interrupt-disable instruction. It is often the case that one bit in the PS register, called Interrupt-enable, indicates
whether interrupts are enabled. An interrupt request is received while this bit is equal to 1 will be accepted. After saving the contents of the PS on the stack,
with the Interrupt-enabled bit equal to 1, the processor clears the interrupt-enable bit in its PS register, thus disabling further interrupts. When a return from
interrupt instruction is executed, the contents of the PS are restored from the stack, setting the interrupt enable bit to 1. Hence interrupts are again enabled.
Device
Processor

16 October 2024 CSE, BMSCE 73

Enabling and Disabling Interrupts
The processor has a status register (PS), which contains information about its current state of operation. Let one bit, IE,
of this register be assigned for enabling/disabling interrupts. Then, the programmer can set or clear IE to cause the
desired action. When IE = 1, interrupt requests from I/O devices are accepted and serviced by the processor. When IE
= 0, the processor simply ignores all interrupt requests from I/O devices.

Let us now consider the specific case of a single interrupt request from one device. When a device activates the
interrupt-request signal, it keeps this signal activated until it learns that the processor has accepted its request. This
means that the interrupt-request signal will be active during execution of the interrupt-service routine, perhaps until an
instruction is reached that accesses the device in question. It is essential to ensure that this active request signal does
not lead to successive interruptions, causing the system to enter an infinite loop from which it cannot recover.

A good choice is to have the processor automatically disable interrupts before starting the execution of the interrupt-
service routine. The processor saves the contents of the program counter and the processor status register. After saving
the contents of the PS register, with the IE bit equal to 1, the processor clears the IE bit in the PS register, thus
disabling further interrupts. Then, it begins execution of the interrupt-service routine. When a Return-from-interrupt
instruction is executed, the saved contents of the PS register are restored, setting the IE bit back to 1. Hence, interrupts
are again enabled.

16 October 2024 CSE, BMSCE 74

Sequence of events involved in handling an interrupt request from a single device.

Assuming that interrupts are enabled, the following is a typical scenario.

1. The device raises an interrupt request.
2. The processor interrupts the program currently being executed and saves the contents of the
PC and PS registers.
3. Interrupts are disabled by clearing the IE bit in the PS to 0.
4. The action requested by the interrupt is performed by the interrupt-service routine, during
which time the device is informed that its request has been recognized, and in response, it
deactivates the interrupt-request signal.
5. Upon completion of the interrupt-service routine, the saved contents of the PC and PS
registers are restored (enabling interrupts by setting the IE bit to 1), and execution of the
interrupted program is resumed.

16 October 2024 CSE, BMSCE 75

Question
The signal sent to the device from the processor to the device after receiving an interrupt is
a) Interrupt-acknowledge
b) Return signal
c) Service signal
d) Permission signal

16 October 2024 CSE, BMSCE 76

Answer
The signal sent to the device from the processor to the device after receiving an interrupt is
a) Interrupt-acknowledge
b) Return signal
c) Service signal
d) Permission signal

Answer: a
Explanation: The Processor upon receiving the interrupt should let the device know that its
request is received.

16 October 2024 CSE, BMSCE 77

Question
The time between the recieving of an interrupt and its service is ______
a) Interrupt delay
b) Interrupt latency
c) Cycle time
d) Switching time

16 October 2024 CSE, BMSCE 78

Answer
The time between the recieving of an interrupt and its service is ______
a) Interrupt delay
b) Interrupt latency
c) Cycle time
d) Switching time

Answer: b
Explanation: The delay in servicing of an interrupt happens due to the time taken for transfer to
take place from Main Program to ISR

16 October 2024 CSE, BMSCE 79

Modes of I/O Data Transfer

Data transfer between the central unit and I/O devices can
be handled in generally three types of modes which are
given below:
1. Program Controlled I/O
2. Interrupt Initiated I/O
3. Direct Memory Access

16 October 2024 CSE, BMSCE 80

 Rough Slide to explain Interrupt request from single device
Single Interrupt Request Line
INTR

Processor
I/O
Device
1

16 October 2024 CSE, BMSCE 81

Handling Multiple Devices
Handling multiple devices gives rise to a number of questions:
▪ How can the processor recognize the device requesting an interrupt ?
▪ Given that different devices are likely to require different interrupt-service routines, how can the processor obtain the starting
address of the appropriate routine in each case ?
▪ Should a device be allowed to interrupt the processor while another interrupt is being serviced ?
▪ How should two or more simultaneous interrupt request be handled ?

Single Interrupt Request Line

INTR

Processor
I/O I/O I/O
Device Device …………… Device
1 2 n

16 October 2024 CSE, BMSCE 82

Under Interrupt Driven I/O data transfer: Handling Multiple Devices

I. Methods to identify the device over a single interrupt request line

a. Polling
b. Vectored Interrupt
II. Interrupt Nesting: A mechanism has to be developed such that even though a processor is executing
an ISR, another interrupt request should be accepted and serviced
a. Priority Structure
III. Simultaneous Requests: Multiple Requests are received over a single interrupt request line at the
same time

16 October 2024 CSE, BMSCE 83

I. Methods to identify the device over a single interrupt request line:
a. Polling

 Consider a simple arrangement where all devices send their interrupt-requests over a single
control line in the bus.
 When the processor receives an interrupt request over this control line, how does it know
which device is requesting an interrupt?
 This information is available in the status register of the device requesting an interrupt:
◼ The status register of each device has an IRQ bit which it sets to 1 when it requests an interrupt.
 Interrupt service routine can poll the I/O devices connected to the bus. The first device with
IRQ equal to 1 is the one that is serviced.
 Polling mechanism is easy, but time consuming to query the status bits of all the I/O devices
connected to the bus.

16 October 2024 CSE, BMSCE 84

I. Methods to identify the device over a single interrupt request line: a. Polling

Illustration: Considering eight devices

Single Interrupt Request Line

INTR

Processor
I/O I/O I/O
Device Device …………… Device
Interrupt Request 1 2 8
Status Register
0 0 0 0 0 0 0 0

Device8 Device1
Interrupt Status Bit Interrupt Status Bit

16 October 2024 CSE, BMSCE 85

Question

 A single Interrupt line can be used to service n different

devices?
a) True
b) False

16 October 2024 CSE, BMSCE 86

Question

 A single Interrupt line can be used to service n different

devices?
a) True
b) False

16 October 2024 CSE, BMSCE 87

Question
The process that periodically checks the status of an I/O devices, is known as
a. Cold swapping
b. I/O instructions
c. Polling
d. Dealing

16 October 2024 CSE, BMSCE 88

Question
The process that periodically checks the status of an I/O devices, is known as
a. Cold swapping
b. I/O instructions
c. Polling
d. Dealing

16 October 2024 CSE, BMSCE 89

I. Methods to identify the device over a single interrupt request line:
b. Vectored Interrupt

 Vectored interrupts reduce service latency; no instructions executed to

poll many devices.
 Let requesting device identify itself directly with a special signal or a unique
binary code (like different ringing tones for different callers). Processor
uses info to find address of correct routine in an interrupt-vector table
 Table lookup is performed. Vector table is located at fixed address, but
routines can be located anywhere in memory

16 October 2024 CSE, BMSCE 90

I. Methods to identify the device over a single interrupt request line:
b. Vectored Interrupt

 A device requesting an interrupt can identify itself if it has its own interrupt-request signal, or if it can
send a special code to the processor through the interconnection network.
 The processor’s circuits determine the memory address of the required interrupt-service routine.
 A commonly used scheme is to allocate permanently an area in the memory to hold the addresses of
interrupt-service routines. These addresses are usually referred to as interrupt vectors, and they are
said to constitute the interrupt-vector table. For example, 128 bytes may be allocated to hold a
table of 32 interrupt vectors.
 The interrupt-service routines may be located anywhere in the memory.
 When an interrupt request arrives, the information provided by the requesting device is used as a
pointer into the interrupt-vector table, and the address in the corresponding interrupt vector is
automatically loaded into the program counter.

16 October 2024 CSE, BMSCE 91

I. Methods to identify the device over a single interrupt request line:
b. Vectored Interrupt
Illustration
Single Interrupt Request Line
INTR
Interrupt Code
Processor 0001 1000
or
Interrupt I/O I/O I/O
Vector Device Device …………… Device
Interrupt-vector 1 2 8
Lookup Table
Addr Memory
0001 1000 Address of ISR
for Device 1 ISR
0010 2000 Addr for Device1
---- 1000 ----
---- 1001 ----
---- ----
---- ----
---- ----
1000 8000
16 October 2024 CSE, BMSCE 92
Question
The starting address sent by the device in vectored interrupt is
called as
a. Location ID
b. Interrupt vector
c. Service location
d. Service ID

16 October 2024 CSE, BMSCE 93

Question
The starting address sent by the device in vectored interrupt is
called as
a. Location ID
b. Interrupt vector
c. Service location
d. Service ID

16 October 2024 CSE, BMSCE 94

Under Interrupt Driven I/O data transfer: Handling Multiple Devices

I. Methods to identify the device over a single interrupt request line

a. Polling
b. Vectored Interrupt
II. Interrupt Nesting: A mechanism has to be developed such that even though a processor is executing
an ISR, another interrupt request should be accepted and serviced
a. Priority Structure

III. Simultaneous Requests: Multiple Requests are received over a single interrupt request line at the
same time

16 October 2024 CSE, BMSCE 95

Under Interrupt Driven I/O data transfer: Handling Multiple Devices
II. Interrupt Nesting: Priority structure

 Interrupt Nesting: A mechanism has to be developed such that even though a processor is executing an ISR, another interrupt
request should be accepted and serviced
 I/O devices are organized in a priority structure: An interrupt request from a high-priority device is accepted while the processor is
executing the interrupt service routine of a low priority device.
 A multiple-level priority organization means that during execution of an interrupt service routine, interrupt requests will be accepted
from some devices but not from others, depending upon the device’s priority.
 To implement this scheme, we can assign a priority level to the processor that can be changed under program control. The priority
level of the processor is the priority of the program that is currently being executed. The processor accepts interrupts only from
devices that have priorities higher than its own.
 At the time that execution of an interrupt-service routine for some device is started, the priority of the processor is raised to that of
the device either automatically or with special instructions. This action disables interrupts from devices that have the same or lower
level of priority.
 However, interrupt requests from higher-priority devices will continue to be accepted. The processor’s priority can be encoded in a
few bits of the processor status register.
 Finally, we should point out that if nested interrupts are allowed, then each interrupt service routine must save on the stack the
saved contents of the program counter and the status register. This has to be done before the interrupt-service routine enables
nesting by setting the IE bit in the status register to 1

16 October 2024 CSE, BMSCE 96

Under Interrupt Driven I/O data transfer: Handling Multiple Devices
II. Interrupt Nesting: Priority structure

Rough Slide for explanation

Illustration: Device1 Device2

Greater Than
Interrupt Priority > Interrupt Priority

ISR of ISR of
ISR of Device2 ISR of Device1
Device1 Device2

Interrupt from Interrupt

Device1 from
Device2

16 October 2024 CSE, BMSCE 97

Under Interrupt Driven I/O data transfer: Handling Multiple Devices

I. Methods to identify the device over a single interrupt request line

a. Polling
b. Vectored Interrupt
II. Interrupt Nesting: A mechanism has to be developed such that even though a processor is executing
an ISR, another interrupt request should be accepted and serviced
a. Priority Structure

III. Simultaneous Requests: Multiple Requests are received over a single interrupt request line at the
same time
 We also need to consider the problem of simultaneous arrivals of interrupt requests from two or more devices.
 The processor must have some means of deciding which request to service first.
 Polling the status registers of the I/O devices is the simplest such mechanism. In this case, priority is determined by the order in
which the devices are polled. When vectored interrupts are used, we must ensure that only one device is selected to send its
interrupt vector code. This is done in hardware, by using arbitration circuits.

16 October 2024 CSE, BMSCE 98

Under Interrupt Driven I/O data transfer:
Controlling I/O Device Behavior

 It is important to ensure that interrupt requests are generated only by those I/O devices that the processor is currently willing to
recognize. Hence, we need a mechanism in the interface circuits of individual devices to control whether a device is allowed to
interrupt the processor. The control needed is usually provided in the form of an interrupt-enable bit in the device’s interface circuit.

 The keyboard status register includes bits KIN and KIRQ. The KIRQ bit is set to 1 if an interrupt request has been raised, but not
yet serviced. The keyboard may raise interrupt requests only when the interrupt-enable bit, KIE, in its control register is set to 1.
Thus, when both KIE and KIN bits are equal to 1, an interrupt request is raised and the KIRQ bit is set to 1. Similarly, the DIRQ bit
in the status register of the display interface indicates whether an interrupt request has been raised. Bit DIE in the control register
of this interface is used to enable interrupts.
16 October 2024 CSE, BMSCE 99
Under Interrupt Driven I/O data transfer:
Processor Control Registers

 The status register, PS, includes the interrupt-enable bit, IE, in addition to other status information. Recall that the processor will
accept interrupts only when this bit is set to 1. The IPS register is used to automatically save the contents of PS when an interrupt
request is received and accepted. At the end of the interrupt-service routine, the previous state of the processor is automatically
restored by transferring the contents of IPS into PS. Since there is only one register available for storing the previous status
information, it becomes necessary to save the contents of IPS on the stack if nested interrupts are allowed.
 The IENABLE register allows the processor to selectively respond to individual I/O devices. A bit may be assigned for each device,
as shown in the figure for the keyboard, display, and a timer circuit that we will use in a later example. When a bit is set to 1, the
processor will accept interrupt requests from the corresponding device.
 The IPENDING register indicates the active interrupt requests. This is convenient when multiple devices may raise requests at the
same time.

In a RISC-style processor, the special instructions may be of the type

MoveControl R2, PS
which loads the contents of the program status register into register R2,
and
MoveControl IENABLE, R3
which places the contents of R3 into the IENABLE register.

16 October 2024 CSE, BMSCE 100

Under Interrupt Driven I/O data transfer:
Examples of Interrupt Programs

 Let us consider again the task of reading a line of characters typed on a keyboard, storing
the characters in the main memory, and displaying them on a display device.
 We will use interrupts with the keyboard, but polling with the display.

16 October 2024 CSE, BMSCE 101

Under Interrupt Driven I/O data transfer:
Examples of Interrupt Programs

16 October 2024 CSE, BMSCE 102

Exceptions
 An exception is any interruption of execution.
 This includes interrupts for I/O transfers.
 But there are also other types of exceptions
◼ Recovery from errors: Detect division by zero, or instruction with an invalid OP code
◼ Debugging: Use of trace mode and Breakpoints
◼ Use of Exceptions in Operating Systems: The operating system (OS) software
coordinates the activities within a computer. It uses exceptions to communicate with and
control the execution of user programs.

16 October 2024 CSE, BMSCE 103

Concluding Remarks
 Two basic I/O-handling approaches: Program-controlled and Interrupt-based
◼ 1st approach has direct control of I/O transfers
◼ Drawback: wait loop to poll flag in status reg.
◼ 2nd approach suspends program when needed to service I/O interrupt with separate
routine
◼ Until then, processor performs useful tasks
 Exceptions cover all interrupts including I/O

16 October 2024 CSE, BMSCE 104

 Unit-2

Bus Structure, Bus Operation, Arbitration

16 October 2024 CSE, BMSCE 105

Bus
W.r.t to Computer System, a bus is a communication pathway connecting two or more devices

16 October 2024 CSE, BMSCE 106

Bus Structure
 The bus as shown in Figure, is a simple structure that implements the interconnection network. Only one source/destination pair of
units can use this bus to transfer data at any one time.
 The bus consists of three sets of lines used to carry address, data, and control signals. I/O device interfaces are connected to these
lines, as shown in Figure for an input device. Each I/O device is assigned a unique set of addresses for the registers in its interface.
When the processor places a particular address on the address lines, it is examined by the address decoders of all devices on the
bus. The device that recognizes this address responds to the commands issued on the control lines. The processor uses the control
lines to request either a Read or a Write operation, and the requested data are transferred over the data lines

A single-bus structure I/O interface for an input device.

16 October 2024 CSE, BMSCE 107
Bus Operation
 A bus requires a set of rules, often called a bus protocol, that govern how the bus is used by various
devices.
 The bus protocol determines when a device may place information on the bus, when it may load the
data on the bus into one of its registers, and so on.
 These rules are implemented by control signals that indicate what and when actions are to be taken.
 One control line, usually labelled R/W’, specifies whether a Read or a Write operation is to be
performed. As the label suggests, it specifies Read when set to 1 and Write when set to 0
 The bus control lines also carry timing information. They specify the times at which the processor and
the I/O devices may place data on or receive data from the data lines.
 A variety of schemes have been devised for the timing of data transfers over a bus. These can be
broadly classified as either synchronous or asynchronous schemes.
 In any data transfer operation, one device plays the role of a master. This is the device that initiates
data transfers by issuing Read or Write commands on the bus. Normally, the processor acts as the
master, but other devices may also become masters.The device addressed by the master is referred
to as a slave.

16 October 2024 CSE, BMSCE 108

Two different schemes for timing of data transfers over a bus

1. Synchronous scheme
2. Asynchronous scheme

1. Synchronous data transfer: sender and receiver use the same clock signal
◼ Needs clock signal between the sender and the receiver
◼ Supports high data transfer rate
2. Asynchronous data transfer: sender provides a synchronization signal to the
receiver before starting the transfer of each message
◼ Does not need clock signal between the sender and the receiver
◼ Slower data transfer rate

16 October 2024 CSE, BMSCE 109

Synchronous bus
 On a synchronous bus, all devices derive timing information from a control line called the bus clock, as
shown in the Figure below.
 The signal on this line has two phases: a high level followed by a low level. The two phases constitute
a clock cycle.
 The first half of the cycle between the low-to-high and high-to-low transitions is often referred to as a
clock pulse.

16 October 2024 CSE, BMSCE 110

Synchronous Data Transfer or Synchronous Bus

Timing of an input transfer

on a synchronous bus

16 October 2024 CSE, BMSCE 111

Synchronous Bus Example for Input Transfer or Read Operation

Before Executing the Instruction Move R1, LOCA

Processor
Address Bus Memory
Move R1, LOCA Addr Memory
Data Bus Contents
R1 LOCA 2000 38

After Executing the Instruction Move R1, LOCA

Processor
Address Bus Memory
Move R1, LOCA Addr Memory
Data Bus Contents
R1 38 LOCA 2000 38

16 October 2024 CSE, BMSCE 112

Synchronous Bus Example for Input Transfer or Read Operation

Processor Address Bus

Memory
Addr Memory
Mov R1, LOCA Contents
Data Bus
LOCA 2000 38
R1

By 2000
Processor Read
The Master
By
Memory
The Slave

16 October 2024 CSE, BMSCE 113

Synchronous Bus Example for Input Transfer or Read Operation

Processor Address Bus

Memory
Addr Memory
Mov R1, LOCA Contents
Data Bus
LOCA 2000 38
R1 38

By 2000
Processor Read
The Master
By
Memory
38 The Slave

Master places the

device address and
Master “strobes” the data
command on the bus,
Addressed slave places on the data lines into its
and indicates that
16 October 2024 CSE, BMSCE
data on the data lines input buffer, for a Read 114
it is a Read operation.
operation.
Synchronous Bus Example for Input Transfer or Read Operation

Timing Diagram of an input transfer on

a synchronous bus.

The clock pulse width, t1 – t0, must be longer It is important that slaves take no action or place any data on
than the maximum propagation delay between the bus before t1. The information on the bus is unreliable
two devices connected to the bus. It also has to be during the period t0 to t1 because signals are changing state.
long enough to allow all devices to decode the address The addressed slave places the requested input data on the
and control signals so that the addressed device data lines at time t1. At the end of the clock cycle, at time t2,
(the slave) can respond at time t1 the master strobes the data on the data lines into its input buffer.
In this context, “strobe” means to capture the values of the data
at a given instant and store them into a buffer

16 October 2024 CSE, BMSCE 115

Synchronous Bus: A detailed timing diagram for the input transfer

16 October 2024 CSE, BMSCE 116

Question
Consider a synchronous bus that operates according to the timing diagram as shown in Figure below. The
address transmitted by the processor appears on the bus after 4 ns. The propagation delay on the bus
wires between the processor and different devices connected varies from 1 to 5 ns, address decoding
takes 6 ns, and the addressed device takes between 5 and 10 ns to place the requested data on the bus.
The input buffer needs 3 ns of setup time. What is the maximum clock period at which this bus can
operate?

16 October 2024 CSE, BMSCE 117

Answer
Consider a synchronous bus that operates according to the timing diagram as shown in Figure below. The
address transmitted by the processor appears on the bus after 4 ns. The propagation delay on the bus
wires between the processor and different devices connected varies from 1 to 5 ns, address decoding
takes 6 ns, and the addressed device takes between 5 and 10 ns to place the requested data on the bus.
The input buffer needs 3 ns of setup time. What is the maximum clock period at which this bus can
operate?

Answer:
Minimum clock period = 4+5+6+10+3 = 28 ns

16 October 2024 CSE, BMSCE 118

A Synchronous Bus Example for Output Transfer or Write Operation

Before Executing the Instruction Store R1, LOCA

Processor
Address Bus Memory
Store R1, LOCA Addr Memory
Data Bus Contents
R1 38 LOCA 2000

After Executing the Instruction Store R1, LOCA

Processor
Address Bus Memory
Store R1, LOCA Addr Memory
Data Bus Contents
R1 38 LOCA 2000 38

16 October 2024 CSE, BMSCE 119

A Synchronous Bus Example for Output Transfer or Write Operation

Processor Address Bus

Memory
Addr Memory
Store R1, LOCA Contents
Data Bus
LOCA 2000
R1 38

By 2000
Processor Write
The Master
By
38 Memory
The Slave

•In case of a Write operation, the master places the data on the bus along with the
address and commands at time t0.
•The slave strobes the data into its input buffer at time t2.
16 October 2024 CSE, BMSCE 120
Synchronous bus
 Data transfer has to be completed within one clock cycle.
◼ Clock period t2 - t0 must be such that the longest propagation delay on the bus and the slowest device
interface must be accommodated.
◼ Forces all the devices to operate at the speed of the slowest device.
 Processor just assumes that the data are available at t2 in case of a Read operation, or are
read by the device in case of a Write operation.
◼ What if the device is actually failed, and never really responded?

16 October 2024 CSE, BMSCE 121

Synchronous bus (contd..)
 Most buses have control signals to represent a response from the slave.
 Control signals serve two purposes:
◼ Inform the master that the slave has recognized the address, and is ready to participate in a data transfer
operation.
◼ Enable to adjust the duration of the data transfer operation based on the speed of the participating slaves.
 High-frequency bus clock is used:
◼ Data transfer spans several clock cycles instead of just one clock cycle as in the earlier case.

16 October 2024 CSE, BMSCE 122

Synchronous bus :
Transfer by Multiple Clock Cycles

Address & command Time

requesting a Read
operation appear on 1 2 3 4
the bus.
Clock

Address

Command
Master strobes data
into the input buffer.
Data

Slave-ready

Slave places the data on the bus, Clock changes are seen by all the devices
and asserts Slave-ready signal. at the same time.

16 October 2024 CSE, BMSCE 123

Question
Consider a synchronous bus that operates according to the timing diagram in figure as given. The bus
and the interface circuitry connected to it have the following parameters:
Bus driver delay 2ns
Propagation delay on the bus 5 to 10 ns
Address decoder delay 6 ns
Time to fetch the requested data 0 to 25 ns
Setup time 1.5 ns
a. What is the maximum clock speed at which this bus can operate?

b. How many clock cycles are needed to complete an input operation?

16 October 2024 CSE, BMSCE 124

Answer
Consider a synchronous bus that operates according to the timing diagram in figure as given. The bus
and the interface circuitry connected to it have the following parameters:
Bus driver delay 2ns
Propagation delay on the bus 5 to 10 ns
Address decoder delay 6 ns
Time to fetch the requested data 0 to 25 ns
Setup time 1.5 ns
a. What is the maximum clock speed at which this bus can operate?
44.5 nano seconds
b. How many clock cycles are needed to complete an input operation?
4 clock cycles

16 October 2024 CSE, BMSCE 125

Question
The I/O bus of a computer uses the synchronous protocol as shown in Figure. Maximum propagation delay on this bus is
4 ns. The bus master takes 1.5 ns to place an address on the address lines. Slave devices require 3 ns to decode the
address and a maximum of 5 ns to place the requested data on the data lines. Input registers connected to the bus
have a minimum setup time of 1 ns. Assume that the bus clock has a 50% duty cycle; that is, the high and low phases
of the clock are of equal duration. What is the maximum clock frequency for this bus?.
Note: Let clock period or cycle time, Tc, is the time between rising edges of a repetitive clock signal. Its reciprocal, fc = 1/Tc, is the clock frequency.

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Question
The I/O bus of a computer uses the synchronous protocol as shown in Figure. Maximum propagation delay on this bus is
4 ns. The bus master takes 1.5 ns to place an address on the address lines. Slave devices require 3 ns to decode the
address and a maximum of 5 ns to place the requested data on the data lines. Input registers connected to the bus
have a minimum setup time of 1 ns. Assume that the bus clock has a 50% duty cycle; that is, the high and low phases
of the clock are of equal duration. What is the maximum clock frequency for this bus?.
Note: Let clock period or cycle time, Tc, is the time between rising edges of a repetitive clock signal. Its reciprocal, fc = 1/Tc, is the clock frequency.

Solution:
The minimum time for the high phase of the clock is the time for the address
to arrive and be decoded by the slave, which is 1.5 + 4 + 3 = 8.5 ns.
The minimum time for the low phase of the clock is the time for the slave to
place data on the bus and for the master to load the data into a register,
which is 5 + 4 + 1 = 10 ns.
Then, the minimum clock period is 2 × 10 = 20 ns, and
the maximum clock frequency is 50 MHz.

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Two different schemes for timing of data transfers over a bus

1. Synchronous scheme
2. Asynchronous scheme

1. Synchronous data transfer: sender and receiver use the same clock signal
◼ Needs clock signal between the sender and the receiver
◼ Supports high data transfer rate
2. Asynchronous data transfer: sender provides a synchronization signal to the
receiver before starting the transfer of each message
◼ Does not need clock signal between the sender and the receiver
◼ Slower data transfer rate

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Asynchronous bus
 Under Asynchronous bus, Data transfers on the bus is controlled by a handshake between the master and the slave. A handshake is
an exchange of command and response signals between the master and the slave.
 Common clock in the synchronous bus case is replaced by two timing control lines:
 Master-ready,
 Slave-ready.
 Master-ready signal is asserted by the master to indicate to the slave that it is ready to participate in a data transfer.
 Slave-ready signal is asserted by the slave in response to the master-ready from the master, and it indicates to the master that the
slave is ready to participate in a data transfer.

Master
Slave
Processor Address Bus
Memory
Data Bus

Master-Ready Control Signal

Slave-Ready Control Signal

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Asynchronous bus (contd..)

 Data transfer using the handshake protocol:

◼ Master places the address and command information on the bus.
◼ Asserts the Master-ready signal to indicate to the slave that the address and command
information has been placed on the bus.
◼ All devices on the bus decode the address.
◼ Addressed slave performs the required operation, and informs the processor it has done so by
asserting the Slave-ready signal.
◼ Master removes all the signals from the bus, once Slave-ready is asserted.
◼ If the operation is a Read operation, Master also strobes the data into its input buffer.

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Asynchronous Bus Example for Input Transfer or Read Operation

Before Executing the Instruction Move R1, LOCA

Processor Address Bus

Memory
Data Bus
Move R1, LOCA Addr Memory
Master-Ready Control Signal Contents
R1 Slave-Ready Control Signal LOCA 2000 38

After Executing the Instruction Move R1, LOCA

Processor Address Bus
Memory
Data Bus
Move R1, LOCA Addr Memory
Master-Ready Control Signal Contents
R1 38 Slave-Ready Control Signal LOCA 2000 38

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Asynchronous Bus: For Input Transfer or Read Operation

Address: 2000 Command: Read

Asynchronous bus Timing diagram:

Handshake control of data transfer
during Input operation

38

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Asynchronous Bus Example for Output Transfer or Write Operation

Address Bus
Processor Memory
Data Bus
Addr Memory
Store R1, LOCA Master-Ready Control Signal Contents
LOCA 2000 38
R1 38 Slave-Ready Control Signal

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Asynchronous Bus Example for Output Transfer or Write Operation

Address Bus
Processor Memory
Data Bus
Addr Memory
Store R1, LOCA Master-Ready Control Signal Contents
LOCA 2000 38
R1 38 Slave-Ready Control Signal

Address: 2000 Command: Write

38

Asynchronous bus Timing diagram:

Handshake control of data transfer
during Output operation

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Asynchronous vs. Synchronous bus

 Advantages of asynchronous bus:

◼ Eliminates the need for synchronization between the sender and the receiver.

◼ Can accommodate varying delays automatically, using the Slave-ready signal.

 Disadvantages of asynchronous bus:

◼ Data transfer rate with full handshake is limited by two-round trip delays.
◼ Data transfers using a synchronous bus involves only one round trip delay, and hence a
synchronous bus can achieve faster rates.

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Bus Arbitration
 There are occasions when two or more entities contend for the use of a single resource in a
computer system. For example, two devices may need to access a given slave at the same
time. In such cases, it is necessary to decide which device will access the slave first.
 The decision is usually made in an arbitration process performed by an arbiter circuit. The
arbitration process starts by each device sending a request to use the shared resource. The
arbiter associates priorities with individual requests. If it receives two requests at the same
time, it grants the use of the slave to the device having the higher priority first.

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Rough slide to explain Bus Arbitration
Example

Arbiter
Memory Circuit

Processor

Printer

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Bus Arbitration (Contd…)
To illustrate the arbitration process, we consider the case where a single bus is the shared resource. The device that initiates data transfer requests on the bus
is the bus master.
It is possible that several devices in a computer system need to be bus masters to transfer data. For example, an I/O device needs to be a bus master to
transfer data directly to or from the computer’s memory. Since the bus is a single shared facility, it is essential to provide orderly access to it by the bus
masters.
A device that wishes to use the bus sends a request to the arbiter. When multiple requests arrive at the same time, the arbiter selects one request and grants
the bus to the corresponding device. For some devices, a delay in gaining access to the bus may lead to an error. Such devices must be given high priority. If
there is no particular urgency among requests, the arbiter may grant the bus using a simple round-robin scheme. Figure below, illustrates an arrangement for
bus arbitration involving two masters. There are two Bus-request lines, BR1 and BR2, and two Bus-grant lines, BG1 and BG2, connecting the arbiter to the
masters.
A master requests use of the bus by activating its Bus-request line. If a single Bus-request is activated, the arbiter activates the corresponding Bus-grant. This
indicates to the selected master that it may now use the bus for transferring data. When the transfer is completed, that master deactivates its Bus-request, and
the arbiter deactivates its Bus-grant.

Bus Arbitration
16 October 2024 CSE, BMSCE 138
Bus Arbitration (Contd…)
Figure below, illustrates a possible sequence of events for the case of three masters. Assume that master 1 has the
highest priority, followed by the others in increasing numerical order. Master 2 sends a request to use the bus first.
Since there are no other requests, the arbiter grants the bus to this master by asserting BG2. When master 2 completes
its data transfer operation, it releases the bus by deactivating BR2. By that time, both masters 1 and 3 have activated
their request lines. Since device 1 has a higher priority, the arbiter activates BG1 after it deactivates BG2, thus granting
the bus to master 1. Later, when master 1 releases the bus by deactivating BR1, the arbiter deactivates BG1 and
activates BG3 to grant the bus to master 3. Note that the bus is granted to master 1 before master 3 even though
master 3 activated its request line before master 1.
Example

BR2 BG2 BR3 BR1 BR2 and BG2 BR1 and BG1 BG2
BG1
5:00am 5:01am 5:05am 5:10am are released are released 5:16am
5:16am
5:15am 5:20am

Granting use of the bus based on priorities:

BR1 > BR2 > BR3

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Question
An arbiter controls access to a common resource. It uses a rotating-priority scheme in responding to
requests on lines R1 through R4. Initially, R1 has the highest priority and R4 the lowest priority. After a
request on one of the lines receives service, that line drops to the lowest priority, and the next line in
sequence becomes the highest-priority line. For example, after R2 has been serviced, the priority order,
starting with the highest, becomes R3, R4, R1, R2. What will be the sequence of grants for the following
sequence of requests: R3, R1, R4, R2? Assume that the last three requests arrive while the first one is
being serviced.

16 October 2024 CSE, BMSCE 140

Answer
An arbiter controls access to a common resource. It uses a rotating-priority scheme in responding to
requests on lines R1 through R4. Initially, R1 has the highest priority and R4 the lowest priority. After a
request on one of the lines receives service, that line drops to the lowest priority, and the next line in
sequence becomes the highest-priority line. For example, after R2 has been serviced, the priority order,
starting with the highest, becomes R3, R4, R1, R2. What will be the sequence of grants for the following
sequence of requests: R3, R1, R4, R2? Assume that the last three requests arrive while the first one is
being serviced.

Answer:
R3 , R4 , R1 , R2

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Question

The device which is allowed to initiate data transfers on the

BUS at any time is called _____
a)Processor
b)BUS arbiter
c)Controller
d)BUS master

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Question

The device which is allowed to initiate data transfers on the

BUS at any time is called _____
a)Processor
b)BUS arbiter
c)Controller
d)BUS master

Answer : d

16 October 2024 CSE, BMSCE 143

 Thanks for Listening

16 October 2024 CSE, BMSCE 144

The asynchronous bus protocol in Figure 7.6 uses a full-handshake, in which the master maintains an asserted signal on
Master-ready until it receives Slave-ready, the slave keeps Slave-ready asserted until Master-ready becomes inactive,
and so on. Consider an alternative protocol in which each of these signals is a pulse of a fixed width of 4 ns. Devices
take action only on the rising edge of the pulse. Using the same parameters as in Problem 7.7, what is the minimum
and maximum time to complete one bus transfer?
Bus driver delay 2 ns Propagation delay on the bus 5 to 10 ns Address decoder delay 6 ns Time to fetch the requested data 0 t o 25 ns Setup time 1.5 ns

 minimum=2+5+4=11. we count the bus driver delay, propagation delay on the bus and the fixed with whcih is 4.
 maximum 2+10+4=16

16 October 2024 CSE, BMSCE 145

Question
The asynchronous bus protocol as shown in figure uses a full-handshake, in which the master maintains an asserted signal on master-ready until it receives
slave-ready, the slave keeps slave-ready asserted until master-ready becomes inactive, and so on. Consider an alternative protocol in which each of these
signals is a pulse of a fixed width of 4 ns. Devices take action only on the rising edge of the pulse. Using the same parameters as given below:
Bus driver delay 2ns
Propagation delay on the bus 5 to 10ns
Address decoder delay 6ns
Time to fetch the requested data 0 to 25ns
Setup time 1.5ns,
What is the minimum and maximum time to complete one bus transfer?

Wrong answer to cross check

Min Time
2+4+5+0=11 assuming no delay

Max Time
2+4+5+25=36 (25 because this would be the longest data fetch would take for this problem)

16 October 2024 CSE, BMSCE 146

Distributed Arbitration

 More than one device can place their 4-bit ID number to

indicate that they need to control of bus.
 If one device puts 1 on the bus line and another device
puts 0 on the same bus line, the bus line status will be 0.
 Device reads the status of all lines through inverters
buffers so device reads bus status 0 as logic 1.
 The device having highest ID number has highest
priority.
Distributed Arbitration
Distributed Arbitration

 Each device compares the code

formed on the arbitration line to its
own ID, starting from the most
significant bit.
 If it finds the difference at any bit
position, it disables its drives at that
bit position and for all lower-order
bits.
 It does so by placing a 0 at the
input of their drive.
Distributed Arbitration
 In our example, device detects a different on
line ARB2 and hence it disables its drives on line
ARB2, ARB1 and ARB0.
 This causes the code on the arbitration lines to
change to 0110. This means that device B has
won the race.
 The decentralized arbitration offers high
reliability because operation of the bus is not
dependent on any single device.
Distributed Arbitration