Digital Design & Computer Arch.

Lecture 6a: Hardware Description

Languages and Verilog II

Prof. Onur Mutlu

ETH Zürich
Spring 2023
10 March 2023
Agenda for Today
n Hardware Description Languages

n Implementing Combinational Logic (in Verilog)

n Implementing Sequential Logic (in Verilog)

n The Verilog slides constitute a tutorial. We may not cover all.

n All slides will be beneficial for your labs.

2
Why Specialized Languages for Hardware?
n HDLs enable easy description of hardware structures
q Wires, gates, registers, flip-flops, clock, rising/falling edge, …
q Combinational and sequential logic elements

n HDLs enable seamless expression of parallelism inherent in

hardware
q All hardware logic operates concurrently

n Both of the above ease specification, simulation &

synthesis

3
Hardware Design Using HDL

4
Structural (Gate-Level) HDL

5
Behavioral HDL

6
Recall: Two Main Styles of HDL Implementation
n Structural (Gate-Level)
q The module body contains gate-level description of the circuit
q Describe how modules are interconnected
q Each module contains other modules (instances)
q … and interconnections between those modules
q Describes a hierarchy of modules defined as gates

n Behavioral
q The module body contains functional description of the circuit
q Contains logical and mathematical operators
q Level of abstraction is higher than gate-level
n Many possible gate-level realizations of a behavioral description

n Many practical designs use a combination of both

7
Recall: What Happens with HDL Code?
n Synthesis (i.e., Hardware Synthesis)
q Modern tools are able to map synthesizable HDL code into
low-level cell libraries à netlist describing gates and wires
q They can perform many optimizations
q … however they can not guarantee that a solution is optimal
n Mainly due to computationally expensive placement and routing
algorithms
n Need to describe your circuit in HDL in a nice-to-synthesize way
q Most common way of Digital Design these days

n Simulation
q Allows the behavior of the circuit to be verified without actually
manufacturing the circuit
q Simulators can work on structural or behavioral HDL
q Simulation is essential for functional and timing verification
8
Implementing Sequential Logic
Using Verilog

9
Sequential = Combinational + Memory

Sequential Circuit

outputs
inputs

Combinational
Circuit

Storage
Element

10
Sequential Logic in Verilog
n We can describe hardware that has memory
q Flip-Flops, Latches, Finite State Machines

n Sequential Logic state transition is triggered by a “CLOCK”

signal
q Latches are sensitive to level of the signal
q Flip-flops are sensitive to the transitioning of signal

n Combinational HDL constructs are not sufficient to express

sequential logic
q We need new constructs:
n always
n posedge/negedge

11
The “always” Block

always @ (sensitivity list)

statement;

Whenever the event in the sensitivity list occurs,

the statement is executed

12
 Recall: The D Flip-Flop
n 1) state change on clock edge, 2) data available for full cycle

D Latch (First)
D D Latch (Second)

CLK
1
CLK:
0
n When the clock is low, 1st latch propagates D to the input of the 2nd (Q unchanged)
n Only when the clock is high, 2nd latch latches D (Q stores D)
q At the rising edge of clock (clock going from 0->1), Q gets assigned D
13
Recall: The D Flip-Flop
n 1) state change on clock edge, 2) data available for full cycle

D CLK Q

__
Q
D Flip-Flop

1
CLK:
0

n At the rising edge of clock (clock going from 0->1), Q gets assigned D
n At all other times, Q is unchanged

14
Recall: The D Flip-Flop
n 1) state change on clock edge, 2) data available for full cycle

D CLK Q

__
Q
We can use D Flip-Flops
D Flip-Flop
to implement the state register
1
CLK:
0

n At the rising edge of clock (clock going from 0->1), Q gets assigned D
n At all other times, Q is unchanged

15
Example: D Flip-Flop
module flop(input clk,
input [3:0] d,
output reg [3:0] q);

always @ (posedge clk)

q <= d; // pronounced “q gets d”

endmodule

n posedge defines a rising edge (transition from 0 to 1).

n Statement executed when the clk signal rises (posedge of clk)

n Once the clk signal rises: the value of d is copied to q

16
Example: D Flip-Flop
module flop(input clk,
input [3:0] d,
output reg [3:0] q);

always @ (posedge clk)

q <= d; // pronounced “q gets d”

endmodule

n assign statement is not used within an always block

n <= describes a non-blocking assignment
q We will see the difference between blocking assignment and
non-blocking assignment soon

17
Example: D Flip-Flop
module flop(input clk,
input [3:0] d,
output reg [3:0] q);

always @ (posedge clk)

q <= d; // pronounced “q gets d”

endmodule

n Assigned variables need to be declared as reg

n The name reg does not necessarily mean that the value is a
register (It could be, but it does not have to be)
n We will see examples later

18
Asynchronous and Synchronous Reset
n Reset signals are used to initialize the hardware to a known
state
q Usually activated at system start (on power up)

n Asynchronous Reset
q The reset signal is sampled independent of the clock
q Reset gets the highest priority
q Sensitive to glitches, may have metastability issues
n Will be discussed in the Timing & Verification Lecture

n Synchronous Reset
q The reset signal is sampled with respect to the clock
q The reset should be active long enough to get sampled at the
clock edge
q Results in completely synchronous circuit
19
Recall: Asynchronous vs. Synchronous State Changes
n Sequential lock we saw is an asynchronous “machine”
q State transitions occur when they occur
q There is nothing that synchronizes when each state transition
must occur

n Most modern computers are synchronous “machines”

q State transitions take place after fixed units of time
q Controlled in part by a clock, as we will see soon

n These are two different design paradigms, with tradeoffs

q Synchronous control can be easier to get correct when the
system consists of many components and many states
q Asynchronous control can be more efficient (no clock overheads)

We will assume synchronous systems in most of this course 20

D Flip-Flop with Asynchronous Reset
module flop_ar (input clk,
input reset,
input [3:0] d,
output reg [3:0] q);

always @ (posedge clk, negedge reset)

begin
if (reset == 0) q <= 0; // when reset
else q <= d; // when clk
end
endmodule

n In this example: two events can trigger the process:

q A rising edge on clk

q A falling edge on reset

21
D Flip-Flop with Asynchronous Reset
module flop_ar (input clk,
input reset,
input [3:0] d,
output reg [3:0] q);

always @ (posedge clk, negedge reset)

begin
if (reset == 0) q <= 0; // when reset
else q <= d; // when clk
end
endmodule

n For longer statements, a begin-end pair can be used

q To improve readability
q In this example, it was not necessary, but it is a good idea

22
D Flip-Flop with Asynchronous Reset
module flop_ar (input clk,
input reset,
input [3:0] d,
output reg [3:0] q);

always @ (posedge clk, negedge reset)

begin
if (reset == 0) q <= 0; // when reset
else q <= d; // when clk
end
endmodule

n First reset is checked: if reset is 0, q is set to 0.

q This is an asynchronous reset as the reset can happen
independently of the clock (on the negative edge of reset signal)
n If there is no reset, then regular assignment takes effect

23
D Flip-Flop with Synchronous Reset
module flop_sr (input clk,
input reset,
input [3:0] d,
output reg [3:0] q);

always @ (posedge clk)

begin
if (reset == ‘0’) q <= 0; // when reset
else q <= d; // when clk
end
endmodule

n The process is sensitive to only clock

q Reset happens only when the clock rises. This is a
synchronous reset

24
D Flip-Flop with Enable and Reset
module flop_en_ar (input clk,
input reset,
input en,
input [3:0] d,
output reg [3:0] q);

always @ (posedge clk, negedge reset)

begin
if (reset == ‘0’) q <= 0; // when reset
else if (en) q <= d; // when en AND clk
end
endmodule

n A flip-flop with enable and reset

q Note that the en signal is not in the sensitivity list

n q gets d only when clk is rising and en is 1

25
Example: D Latch

module latch (input clk,

input [3:0] d,
output reg [3:0] q);

always @ (clk, d)
if (clk) q <= d; // latch is transparent when
// clock is 1
endmodule

26
Summary: Sequential Statements So Far
n Sequential statements are within an always block

n The sequential block is triggered with a change in the

sensitivity list

n Signals assigned within an always must be declared as reg

n We use <= for (non-blocking) assignments and do not use

assign within the always block.

27
Basics of always Blocks
module example (input clk,
input [3:0] d,
output reg [3:0] q);

wire [3:0] normal; // standard wire

reg [3:0] special; // assigned in always

always @ (posedge clk)

special <= d; // first FF array

assign normal = ~special; // simple assignment

always @ (posedge clk)

q <= normal; // second FF array
endmodule

You can have as many always blocks as needed

Assignment to the same signal in different always blocks is not allowed!

28
Why Does an always Block Remember?
module flop (input clk,
input [3:0] d,
output reg [3:0] q);

always @ (posedge clk)

begin
q <= d; // when clk rises copy d to q
end
endmodule

n This statement describes what happens to signal q

n … but what happens when the clock is not rising?
n The value of q is preserved (remembered)

29
An always Block Does NOT Always Remember
module comb (input inv,
input [3:0] data,
output reg [3:0] result);

always @ (inv, data) // trigger with inv, data

if (inv) result <= ~data;// result is inverted data
else result <= data; // result is data

endmodule

n This statement describes what happens to signal result

q When inv is 1, result is ~data
q When inv is not 1, result is data
n The circuit is combinational (no memory)
q result is assigned a value whenever an input value changes & in all
cases of the if .. else block
30
always Blocks for Combinational Circuits
n An always block defines combinational logic if:
q All outputs are always (continuously) updated
1. All right-hand side signals are in the sensitivity list
n You can use always @* for short
2. All left-hand side signals get assigned in every possible condition
of if .. else and case blocks

n It is easy to make mistakes and unintentionally describe

memorizing elements (latches)
q Vivado will most likely warn you. Make sure you check the
warning messages

n Always blocks allow powerful combinational logic statements

q if .. else
q case
31
Sequential or Combinational?

wire enable, data; wire enable, data;

reg out_a, out_b; reg out_a, out_b;

always @ (*) begin always @ (data) begin

out_a = 1’b0; out_a = 1’b0;
if(enable) begin out_b = 1’b0;
out_a = data; if(enable) begin
out_b = data; out_a = data;
end out_b = data;
end end
No assignment for ~enable
end Not in the sensitivity list

Sequential Sequential

32
The always Block is NOT Always Practical/Nice
reg [31:0] result;
wire [31:0] a, b, comb;
wire sel,

always @ (a, b, sel) // trigger with a, b, sel

if (sel) result <= a; // result is a
else result <= b; // result is b

assign comb = sel ? a : b;

n Both statements describe the same multiplexer

n In this case, the always block is more work

33
always Block for Case Statements (Handy!)
module sevensegment (input [3:0] data,
output reg [6:0] segments);

always @ ( * ) // * is short for all signals

case (data) // case statement
4'd0: segments = 7'b111_1110; // when data is 0
4'd1: segments = 7'b011_0000; // when data is 1
4'd2: segments = 7'b110_1101;
4'd3: segments = 7'b111_1001;
4'd4: segments = 7'b011_0011;
4'd5: segments = 7'b101_1011;
// etc etc
default: segments = 7'b000_0000; // required
endcase

endmodule

34
Summary: always Block
n if .. else can only be used in always blocks

n The always block is combinational only if all regs within the

block are always assigned to a signal
q Use the default case to make sure you do not forget an
unimplemented case, which may otherwise result in a latch

n Use casex statement to be able to check for don’t cares

35
Non-Blocking and Blocking Assignments
Non-blocking (<=) Blocking (=)
always @ (a) always @ (a)
begin begin
a <= 2’b01; a = 2’b01;
b <= a; // a is 2’b01
// all assignments are made here b = a;
// b is not (yet) 2’b01 // b is now 2’b01 as well
end end

n All assignments are made n Each assignment is made

at the end of the block immediately
n All assignments are made n Process waits until the first
in parallel, process flow is assignment is complete, it
not-blocked blocks progress
n Similar to sequential programs
36
Why Use (Non)-Blocking Statements
n Non-blocking statements allow operating on “old” values
q Enable easy sequential logic descriptions

n Blocking statements allow a sequence of operations

q Allow operating on immediately updated values
q More like a “software” programming language

n If the sensitivity list is correct, a block with non-blocking

statements will eventually evaluate to the same result as
the same block with blocking statements
q This may require some additional iterations
Example: Blocking Assignment

n Assume all inputs are initially ‘0’

always @ ( * )
begin
p = a ^ b ; // p = 0 1
g = a & b ; // g = 0 0
s = p ^ cin ; // s = 0 1
cout = g | (p & cin) ; // cout = 0 0
end

n If a changes to ‘1’
q All values are updated in order

38
The Same Example: Non-Blocking Assignment

n Assume all inputs are initially ‘0’

always @ ( * )
begin
p <= a ^ b ; // p = 0 1
g <= a & b ; // g = 0 0
s <= p ^ cin ; // s = 0 0
cout <= g | (p & cin) ; // cout = 0 0
end

n If a changes to ‘1’
q All assignments are concurrent
q When s is being assigned, p is still 0

39
The Same Example: Non-Blocking Assignment

n After the first iteration, p has changed to ‘1’ as well

always @ ( * )
begin
p <= a ^ b ; // p = 1 1
g <= a & b ; // g = 0 0
s <= p ^ cin ; // s = 0 1
cout <= g | (p & cin) ; // cout = 0 0
end

n Since there is a change in p, the process triggers again

n This time s is calculated with p=1

40
Rules for Signal Assignment
n Use always @(posedge clk) and non-blocking
assignments (<=) to model synchronous sequential logic

always @ (posedge clk)

q <= d; // non-blocking

n Use continuous assignments (assign) to model simple

combinational logic

assign y = a & b;

41
Rules for Signal Assignment (Cont.)

n Use always @ (*) and blocking assignments (=) to model

more complicated combinational logic

n You cannot make assignments to the same signal in more

than one always block or in a continuous assignment
always @ (*) always @ (*)
a = b; a = b;

always @ (*) assign a = c;

a = c;

42
Recall: Finite State Machines (FSMs)
n Each FSM consists of three separate parts:
q next state logic
q state register
q output logic

CLK
M next
next k state k output N
inputs state
state
outputs
logic
logic

state register

At the beginning of the clock cycle, next state is latched into the state register

43
Recall: Finite State Machines (FSMs) Consist of:
n Sequential Circuits CLK

q State register(s)
n Store the current state and S’ S
Next Current
n Load the next state at the clock edge State State

n Combinational Circuits Next State

Logic
q Next state logic
n Determines what the next state will be CL Next
State

Output
q Output logic Logic
n Generates the outputs
CL Outputs

44
FSM Example 1: Divide the Clock Frequency by 3

The output Y is HIGH for one clock cycle out of every 3. In other
words, the output divides the frequency of the clock by 3.

45
Implementing FSM Example 1: Definitions
module divideby3FSM (input clk,
input reset,
output q);

reg [1:0] state, nextstate;

parameter S0 = 2'b00;
parameter S1 = 2'b01;
parameter S2 = 2'b10;

n We define state and nextstate as 2-bit reg

n The parameter descriptions are optional, it makes reading
easier

46
Implementing FSM Example 1: State Register
CLK

S’ S
Next Current
State State

// state register
always @ (posedge clk, posedge reset)
if (reset) state <= S0;
else state <= nextstate;

n This part defines the state register (memorizing process)

n Sensitive to only clk, reset
n In this example, reset is active when it is ‘1’ (active-high)

47
Implementing FSM Example 1: Next State Logic

CLK
M next
next k state k output N
inputs state
state
outputs
logic
logic

// next state logic

always @ (*)
case (state)
S0: nextstate = S1;
S1: nextstate = S2;
S2: nextstate = S0;
default: nextstate = S0;
endcase

48
Implementing FSM Example 1: Output Logic

CLK
M next
next k state k output N
inputs state
state
outputs
logic
logic

// output logic
assign q = (state == S0);

n In this example, output depends only on state

q Moore type FSM
49
Implementation of FSM Example 1
module divideby3FSM (input clk, input reset, output q);
reg [1:0] state, nextstate;

parameter S0 = 2'b00; parameter S1 = 2'b01; parameter S2 = 2'b10;

always @ (posedge clk, posedge reset) // state register

if (reset) state <= S0;
else state <= nextstate;

always @ (*) // next state logic

case (state)
S0: nextstate = S1;
S1: nextstate = S2;
S2: nextstate = S0;
default: nextstate = S0;
endcase
assign q = (state == S0); // output logic
endmodule

50
FSM Example 2: Recall the Smiling Snail
n Alyssa P. Hacker has a snail that crawls down a paper tape
with 1’s and 0’s on it
n The snail smiles whenever the last four digits it has crawled
over are 1101
n Design Moore and Mealy FSMs of the snail’s brain

Moore

Mealy

51
Implementing FSM Example 2: Definitions
module SmilingSnail (input clk,
input reset,
input number,
output smile);

reg [1:0] state, nextstate;

parameter S0 = 2'b00;
parameter S1 = 2'b01;
parameter S2 = 2'b10;
parameter S3 = 2’b11;

digit/smile

52
Implementing FSM Example 2: State Register

// state register
always @ (posedge clk, posedge reset)
if (reset) state <= S0;
else state <= nextstate;

n This part defines the state register (memorizing process)

n Sensitive to only clk, reset

n In this example reset is active when ‘1’ (active-high)

53
Implementing FSM Example 2: Next State Logic
// next state logic
always @ (*)
case (state)
S0: if (number) nextstate = S1;
else nextstate = S0;
S1: if (number) nextstate = S2;
else nextstate = S0;
S2: if (number) nextstate = S2;
else nextstate = S3;
S3: if (number) nextstate = S1;
else nextstate = S0;
default: nextstate = S0;
endcase

54
Implementing FSM Example 2: Output Logic

// output logic
assign smile = (number & state == S3);

n In this example, output depends on state and input

q Mealy type FSM

n We used a simple combinational assignment

55
Implementation of FSM Example 2
module SmilingSnail (input clk, always @ (*) // next state logic
input reset, case (state)
input number, S0: if (number)
output smile); nextstate = S1;
else nextstate = S0;
reg [1:0] state, nextstate; S1: if (number)
nextstate = S2;
parameter S0 = 2'b00; else nextstate = S0;
parameter S1 = 2'b01; S2: if (number)
parameter S2 = 2'b10; nextstate = S2;
parameter S3 = 2’b11; else nextstate = S3;
S3: if (number)
// state register nextstate = S1;
always @ (posedge clk, posedge else nextstate = S0;
reset) default: nextstate = S0;
if (reset) state <= S0; endcase
else state <= nextstate; // output logic
assign smile = (number & state==S3);

endmodule

56
What Did We Learn?
n Basics of describing sequential circuits in Verilog

n The always statement

q Needed for describing memorizing elements (flip-flops, latches)
q Can also be used to describe combinational circuits

n Blocking vs Non-blocking statements

q = assigns the value immediately
q <= assigns the value at the end of the block

n Describing FSMs in Verilog

q Next state logic
q State assignment
q Output logic
57
Next Lecture:
Timing and Verification

58
Digital Design & Computer Arch.
Lecture 6a: Hardware Description
Languages and Verilog II

Prof. Onur Mutlu

ETH Zürich
Spring 2023
10 March 2023