Brainkart - 215 - EE64031 Discrete Time Systems and Signal Processing - Notes - Bin
Brainkart - 215 - EE64031 Discrete Time Systems and Signal Processing - Notes - Bin
UNIT I INTRODUCTION 9
Classification of systems: Continuous, discrete, linear, causal, stable, dynamic, recursive, time
variance; classification of signals: continuous and discrete, energy and power; mathematical
representation of signals; spectral density; sampling techniques, quantization, quantization error,
Nyquist rate, aliasing effect.
TOTAL : 45 PERIODS
OUTCOMES:
Ability to understand and apply basic science, circuit theory, Electro-magnetic field
theory control theory and apply them to electrical engineering problems.
TEXT BOOKS:
1. J.G. Proakis and D.G. Manolakis, ‗Digital Signal Processing Principles, Algorithms
and Applications‘, Pearson Education, New Delhi, PHI. 2003.
2. S.K. Mitra, ‗Digital Signal Processing – A Computer Based Approach‘, McGraw
Hill Edu, 2013.
3. Robert Schilling & Sandra L.Harris, Introduction to Digital Signal Processing using Matlab‖,
Cengage Learning,2014.
REFERENCES:
1. Poorna Chandra S, Sasikala. B ,Digital Signal Processing, Vijay Nicole/TMH,2013.
2. B.P.Lathi, ‗Principles of Signal Processing and Linear Systems‘, Oxford University Press, 2010
3. Taan S. ElAli, ‗Discrete Systems and Digital Signal Processing with Mat Lab‘, CRC Press, 2009.
4. Sen M.kuo, woonseng…s.gan, ―Digital Signal Processors, Architecture, Implementations &
Applications, Pearson,2013
5. Dimitris G.Manolakis, Vinay K. Ingle, applied Digital Signal Processing,Cambridge,2012
6. Lonnie C.Ludeman ,‖Fundamentals of Digital Signal Processing‖,Wiley,2013
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CONTENT PG.NO
CHAPTER -1
Introduction 7
Classification of signals processing 8
Advantages of DSP over ASP
Disadvantages of DSP over ASP
Classification of signals 11
Discrete time systems 11
CHAPTER – 2
CHAPTER – 4
Introduction 61
Types of digital filters 65
Structure for FIR system 65
Structure for IIR system 68
IIR Filter design (Impulse invariance) 73
IIR Filter design (BZT) 76
Butterworth approximation 80
Frequency Transformation 87
FIR Filter design 89
Design filter for pole zero placement 93
CHAPTER – 5
References
Glossary Terms
Tutorial Problems
Worked Out Problems
Question Bank
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CHAPTER 1
PREREQISTING DISCUSSION
A Signal is defined as any physical quantity that changes with time, distance, speed, position, pressure,
temperature or some other quantity. A Signal is physical quantity that consists of many sinusoidal of
different amplitudes and frequencies.
Ex x(t) = 10t
X(t) = 5x2+20xy+30y
A System is a physical device that performs an operations or processing on a signal. Ex Filter or
Amplifier.
2) DSP (Digital signal Processing) : If the input signal given to the system is digital then system does
digital signal processing. Ex Digital Computer, Digital Logic Circuits etc. The devices called as ADC
(analog to digital Converter) converts Analog signal into digital and DAC (Digital to Analog Converter)
does vice-versa.
Most of the signals generated are analog in nature. Hence these signals are converted to digital form by
the analog to digital converter. Thus AD Converter generates an array of samples and gives it to the
digital signal processor. This array of samples or sequence of samples is the digital equivalent of input
analog signal. The DSP performs signal processing operations like filtering, multiplication,
transformation or amplification etc operations over this digital signals. The digital output signal from the
DSP is given to the DAC.
6. Mathematical signal processing algorithm can be routinely implemented on digital signal processing
systems. Digital controllers are capable of performing complex computation with constant accuracy
at high speed.
7. Digital signal processing systems are upgradeable since that are software controlled.
8. Possibility of sharing DSP processor between several tasks.
9. The cost of microprocessors, controllers and DSP processors are continuously going down. For some
complex control functions, it is not practically feasible to construct analog controllers.
10. Single chip microprocessors, controllers and DSP processors are more versatile and powerful.
CLASSIFICATION OF SIGNALS
1. Single channel and Multi-channel signals
2. Single dimensional and Multi-dimensional signals
3. Continuous time and Discrete time signals.
4. Continuous valued and discrete valued signals.
5. Analog and digital signals.
6. Deterministic and Random signals
7. Periodic signal and Non-periodic signal
8. Symmetrical(even) and Anti-Symmetrical(odd) signal
9. Energy and Power signal
exponential waveforms.
Note: Digital signals (DISCRETE TIME & DISCRETE AMPLITUDE) are obtained by sampling the
ANALOG signal at discrete instants of time, obtaining DISCRETE TIME signals and then by
quantizing its values to a set of discrete values & thus generating DISCRETE AMPLITUDE signals.
Sampling process takes place on x axis at regular intervals & quantization process takes place along y
axis. Quantization process is also called as rounding or truncating or approximation process.
Tutorial problems:
a) cos (0.01 ∏ n) Periodic N=200 samples per cycle.
b) cos (3 ∏ n) Periodic N=2 samples
c) sin(3n) Non-Periodic
d) cos(n/8) cos( ∏n/8) Non-Periodic
𝑋 𝑛 + (𝑛) 2
𝑋 𝑛 =
𝑋 𝑛 =
Thus X(n)= Xe(n) + Xo(n)
Even component of discrete time signal is given by
𝑋 𝑛 + (𝑛) 2
𝑋𝑒 𝑛 =
𝑋𝑜 𝑛 =
Test whether the following CT waveforms is periodic or not. If periodic find out the fundamental period.
a) 2 sin(2/3)t + 4 cos (1/2)t + 5 cos((1/3)t Ans: Period of x(t)= 12
b) a cos(t √2) + b sin(t/4) Ans: Non-Periodic
a) Find out the even and odd parts of the discrete signal x(n)={2,4,3,2,1}
b) Find out the even and odd parts of the discrete signal x(n)={2,2,2,2}
∞
E= 𝑛=−∞ 𝑥2(𝑛)
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If Energy is finite and power is zero for x(n) then x(n) is an energy signal. If power is finite and energy
is infinite then x(n) is power signal. There are some signals which are neither energy nor a power signal.
Tutorial problems:
a) Find the power and energy of u(n) unit step function.
b) Find the power and energy of r(n) unit ramp function.
c) Find the power and energy of an u(n).
n=0
δ (n) = 1 n=0
0 n=0 i.e δ(n)={1}
u(n) = 1 n≥0
0 n<0
ur (n) = n n≥0
0 n<0
4) Exponential signal
x(n) = a n = (re j Ø ) n = r n e j Ø n = r n (cos Øn + j sin Øn)
4) Sinusoidal waveform
x(n) = A Sin wn
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1) Shifting : signal x(n) can be shifted in time. We can delay the sequence or advance the sequence.
This is done by replacing integer n by n-k where k is integer. If k is positive signal is delayed in time by
k samples (Arrow get shifted on left hand side) And if k is negative signal is advanced in time k samples
(Arrow get shifted on right hand side)
X(n) = { 1, -1 , 0 , 4 , -2 , 4 , 0 ,……}
n=0
Delayed by 2 samples : X(n-2)= { 1, -1 , 0 , 4 , -2 , 4 , 0 ,……}
n=0
Advanced by 2 samples : X(n+2) = { 1, -1 , 0 , 4 , -2 , 4 , 0 ,……}
n=0
2) Folding / Reflection : It is folding of signal about time origin n=0. In this case replace n by –n.
Original signal:
X(n) = { 1, -1 , 0 , 4 , -2 , 4 , 0}
n=0
Folded signal:
X(-n) = { 0 , 4 , -2 , 4 , 0 , -1 , 1}
n=0
3) Addition : Given signals are x1(n) and x2(n), which produces output y(n) where y(n) = x1(n)+ x2(n).
Adder generates the output sequence which is the sum of input sequences.
4) Scaling: Amplitude scaling can be done by multiplying signal with some constant. Suppose original
signal is x(n). Then output signal is A x(n)
2. Unit advance
Z+1
x(n) y(n) = x(n+1)
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3. Addition
x1(n)
+
y(n) =x1(n)+x2(n)
x2(n)
4. Multiplication
x1(n)
×
y(n) =x1(n)*x2(n)
x2(n)
5. Scaling (constant multiplier)
A
x(n) y(n) = A x(n)
It is very easy to find out that given system is static or dynamic. Just check that output of the system
solely depends upon present input only, not dependent upon past or future.
S. No System [y(n)] Static / Dynamic
1 x(n) Static
2 A(n-2) Dynamic
3 X2(n) Static
2
4 X(n ) Dynamic
5 n x(n) + x2(n) Static
6 X(n)+ x(n-2) +x(n+2) Dynamic
It is very easy to find out that given system is Shift Invariant or Shift Variant.
Suppose if the system produces output y(n) by taking input x(n)
x(n) y(n)
If we delay same input by k units x(n-k) and apply it to same systems, the system produces output y(n-k)
x(n-k) y(n-k)
a1
x1(n)
SYSTEM
y(n)= T[a1x1[n] + a2x2(n) ]
x2(n)
a2
x1(n) SYSTEMa1
y(n)=T[a1x1(n)+a2x2(n)]
x2(n) SYSTEM a2
1 ex(n) Non-Linear
2 x2 (n) Non-Linear
3 m x(n) + c Non-Linear
5 X(-n) Linear
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It is very easy to find out that given system is causal or non-causal. Just check that output of the system
depends upon present or past inputs only, not dependent upon future.
S.No System [y(n)] Causal /Non-Causal
1 x(n) + x(n-3) Causal
2 X(n) Causal
3 X(n) + x(n+3) Non-Causal
4 2 x(n) Causal
5 X(2n) Non-Causal
6 X(n)+ x(n-2) +x(n+2) Non-Causal
It is very easy to find out that given system is stable or unstable. Just check that by providing input
signal check that output should not rise to ∞.
Step 2) y(n)= { y(-1) , y(0) , y(1), y(2), ….} It goes up to length(xn)+ length(yn) -1.
X1 x2 x3
h1
h1x1 h1x2 h1x3
h2
y(-1) = h1 x1
y(0) = h2 x1 + h1 x2
y(1) = h1 x3 + h2x2 + h3 x1 …………
y1 y2 y3
The output of causal system at n= n0 depends upon the inputs for n< n0 Hence
h(-1)=h(-2)=h(-3)=0
Thus LSI system is causal if and only if
h(n) =0 for n<0
This is the necessary and sufficient condition for causality of the system.
Linear convolution of the causal LSI system is given by
n
The input x(n) is said to bounded if there exists some finite number Mx such that |x(n)| ≤ Mx < ∞. The
output y(n) is said to bounded if there exists some finite number My such that |y(n)| ≤ My < ∞.
Linear convolution is given by
∞
The absolute values of total sum is always less than or equal to sum of the absolute values of
individually terms. Hence
∞
k=-∞
The input x(n) is said to bounded if there exists some finite number Mx such that |x(n)| ≤ Mx < ∞.
Hence bounded input x(n) produces bounded output y(n) in the LSI system only if ∞
∑ |h(k)| < ∞
k=-∞
With this condition satisfied, the system will be stable. The above equation states that the LSI system is
stable if its unit sample response is absolutely summable. This is necessary and sufficient condition for
the stability of LSI system.
CORRELATION:
It is frequently necessary to establish similarity between one set of data and another. It means we
would like to correlate two processes or data. Correlation is closely related to convolution, because the
correlation is essentially convolution of two data sequences in which one of the sequences has been
reversed.
Applications are in
1) Images processing for robotic vision or remote sensing by satellite in which data from
different image is compared
2) In rad.arandsonarsystems for range and position finding in which transmitted and reflected
waveforms are compared.
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k= -∞
4 Linear convolution is commutative Not commutative.
TYPES OF CORRELATION
Under Correlation there are two classes.
1) CROSS CORRELATION: When the correlation of two different sequences x(n) and y(n) is
performed it is called as Cross correlation. Cross-correlation of x(n) and y(n) is rxy(l) which can
be mathematically expressed as
OR
∞
rxy(l) = ∑ x (n + l) y(n)
n= -∞
2) AUTO CORRELATION: In Auto-correlation we correlate signal x(n) with itself, which can be
mathematically expressed as
∞
OR
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rxx(l) = ∑ x (n + l) x(n)
n= -∞
PROPERTIES OF CORRELATION
1) The cross-correlation is not commutative.
rxy(l) = ryx(-l)
2) The cross-correlation is equivalent to convolution of one sequence with folded version of another
sequence.
rxy(l) = x(l) * y(-l).
3) The autocorrelation sequence is an even function.
rxx(l) = rxx(-l)
Examples:
Q) Determine cross-correlation sequence
x(n)={2, -1, 3, 7,1,2, -3} & y(n)={1, -1, 2, -2, 4, 1, -2 ,5}
Answer: rxy(l) = {10, -9, 19, 36, -14, 33, 0,7, 13, -18, 16, -7, 5, -3}
Q) Determine autocorrelation sequence
x(n)={1, 2, 1, 1} Answer: rxx(l) = {1, 3, 5, 7, 5, 3, 1}
A/D CONVERSION
BASIC BLOCK DIAGRAM OF A/D CONVERTER
1. SAMPLING THEOREM
It is the process of converting continuous time signal into a discrete time signal by taking samples of the
continuous time signal at discrete time instants.
When sampling at a rate of fs samples/sec, if k is any positive or negative integer, we cannot distinguish
between the samples values of fa Hz and a sine wave of (fa+ kfs) Hz. Thus (fa + kfs) wave is alias or
image of fa wave.
Thus Sampling Theorem states that if the highest frequency in an analog signal is Fmax and the
signal is sampled at the rate fs > 2Fmax then x(t) can be exactly recovered from its sample values. This
sampling rate is called Nyquist rate of sampling. The imaging or aliasing starts after Fs/2 hence folding
frequency is fs/2. If the frequency is less than or equal to 1/2 it will be represented properly.
Example:
Case 1: X1(t)=cos2.(10) t
Fs= 40 Hz i.e t= n/Fs
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Thus the frequency 50 Hz, 90 Hz , 130 Hz … are alias of the frequency 10 Hz at the sampling rate of 40
samples/sec
2. QUANTIZATION
The process of converting a discrete time continuous amplitude signal into a digital signal by expressing
each sample value as a finite number of digits is called quantization. The error introduced in
representing the continuous values signal by a finite set of discrete value levels is called quantization
error or quantization noise.
Quantization Step/Resolution : The difference between the two quantization levels is called quantization
step. It is given by Δ = XMax – xMin / L-1 where L indicates Number of quantization levels.
3. CODING/ENCODING
Each quantization level is assigned a unique binary code. In the encoding operation, the quantization
sample value is converted to the binary equivalent of that quantization level. If 16 quantization levels are
present, 4 bits are required. Thus bits required in the coder is the smallest integer greater than or equal to
Log2 L. i.e b= Log2 L
Thus Sampling frequency is calculated as fs=Bit rate / b.
4. ANTI-ALIASING FILTER
When processing the analog signal using DSP system, it is sampled at some rate depending upon the
bandwidth. For example if speech signal is to be processed the frequencies upon 3khz can be used.
Hence the sampling rate of 6khz can be used. But the speech signal also contains some frequency
components more than 3khz. Hence a sampling rate of 6khz will introduce aliasing. Hence signal should
be band limited to avoid aliasing.
The signal can be band limited by passing it through a filter (LPF) which blocks or attenuates all
the frequency components outside the specific bandwidth. Hence called as Anti aliasing filter or pre-
filter. (Block Diagram).
5. SAMPLE-AND-HOLD CIRCUIT:
The sampling of an analogue continuous-time signal is normally implemented using a device called an
analo guew-tow- wdig.iptaal cdoenveeprtezr.(nAe/Dt ). The continuous-time signal is first passed
through a device called a sample-and-hold (S/H) whose function is to measure the input signal value at
the clock instant and hold
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it fixed for a time interval long enough for the A/D operation to complete. Analogue-to-digital conversion
is potentially a slow operation, and a variation of the input voltage during the conversion may disrupt the
operation of the converter. The S/H prevents such disruption by keeping the input voltage constant during
the conversion. This is schematically illustrated by Figure.
After a continuous-time signal has been through the A/D converter, the quantized output may differ from
the input value. The maximum possible output value after the quantization process could be up to half the
quantization level q above or q below the ideal output value. This deviation from the ideal output value is
called the quantization error. In order to reduce this effect, we increases the number of bits.
Tutorial problems:
Q) Calculate Nyquist Rate for the analog signal x(t)
1) x(t)= 4 cos 50 ∏t + 8 sin 300∏t –cos 100∏t Fn=300 Hz
2) x(t)= 2 cos 2000∏t+ 3 sin 6000∏t + 8 cos 12000∏t Fn=12KHz
3) x(t)= 4 cos 100∏t Fn=100 Hz
Q) The following four analog sinusoidal are sampled with the fs=40Hz. Find out corresponding time
signals and comment on them
X1(t)= cos 2∏(10)t
X2(t)= cos 2∏(50)t
X3(t)= cos 2∏(90)t
X4(t)= cos 2∏(130)t
Q) Signal x1(t).=10coe2∏(100n0)t+5 cos2∏(5000)t. Determine Nyquist rate. If the signal is sampled at
4khz will the signal be recovered from its samples.
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Q) Signal x1(t)=3 cos 600∏t+ 2cos800∏t. The link is operated at 10000 bits/sec and each input sample
is quantized into 1024 different levels. Determine Nyquist rate, sampling frequency, folding frequency
& resolution.
DIFFERENCE EQUATION
n
y(n) = a n+1
y(-1) + ∑ a k x (n -k) n≥0
k= 0
Zero state response (Forced response) : Consider initial condition are zero. (System is relaxed at time
n=0) i.e y(-1) =0
Zero Input response (Natural response) : No input is forced as system is in non-relaxed initial
condition. i.e y(-1) != 0
Total response is the sum of zero state response and zero input response.
Q) Determine zero input response for y(n) – 3y(n-1) – 4y(n-2)=0; (Initial Conditions are y(-1)=5 &
y(-2)= 10) Answer: y(n)= 7 (-1)n + 48 (4)n
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CHAPTER 2
n=-∞
Z transform is an infinite power series because summation index varies from -∞ to ∞. But it is useful
for values of z for which sum is finite. The values of z for which f (z) is finite and lie within the region
called as ―region of convergence (ROC).
ADVANTAGES OF Z TRANSFORM
1. The DFT can be determined by evaluating z transform.
2. Z transform is widely used for analysis and synthesis of digital filter.
3. Z transform is used for linear filtering. z transform is also used for finding Linear convolution,
cross-correlation and auto-correlations of sequences.
4. In z transform user can characterize LTI system (stable/unstable, causal/anti- causal) and its
response to various signals by placements of pole and zero plot.
|z|<a
Fig showthep.lot ofztransforms. The z transform has real and imaginary parts. Thus a plot of imaginary
part versus real part is called complex z-plane. The radius of circle is 1 called as unit circle.
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This complex z plane is used to show ROC, poles and zeros. Complex variable z is also expressed in
polar form as Z= rejω where r is radius of circle is given by |z| and ω is the frequency of the sequence in
radians and given by ∟z.
1- 2z-1cosω0+z-2
15 sin(ω0n) u(n) z-1sinω0 |z| > 1
1- 2z-1cosω0+z-2
16 an cos(ω0n) u(n) Time scaling 1- (z/a)-1cosω0 |z| > |a|
1- 2(z/a)-1cosω0+(z/a)-2
1- 2(z/a)-1cosω0+(z/a)-2
Tutorial problems:
Q) Determine z transform of following signals. Also draw ROC.
i) x(n) = {1,2,3,4,5}
ii) x(n)={1,2,3,4,5,0,7}
Q) Determine z transform and ROC for x(n) = (-1/3)n u(n) –(1/2)n u(-n-1).
Q) Determine z transform and ROC for x(n) = [ 3.(4 n)–4(2n)] u(n).
Q) Determine z transform and ROC for x(n) = (1/2) n u(-n).
Q) Determine z transform and ROC for x(n) = (1/2) n {u(n) – u(n-10)}.
Q) Find linear convolution using z transform. X(n)={1,2,3} & h(n)={1,2}
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Then z
a1 x1(n) + a2 x2(n) a1 X1(z) + a2 X2(z)
z Transform of linear combination of two or more signals is equal to the same linear combination of z
transform of individual signals.
2) Time shifting
The Time shifting property states that if
z
x(n) X(z) And
z
Then x(n-k) X(z) z–k
–k
Thus shifting the sequence circularly by ‗k‘ samples is equivalent to multiplying its z transform by z
3) Scaling in z domain
This property states that if
z
x(n) X(z) And
z
Then an x(n) x(z/a)
Thus scaling in z transform is equivalent to multiplying by a n in time domain.
5) Differentiation in z domain
The Differentiation property states that if
z
x(n) X(z) And
z
Then n x(n) -z d/dz (X(z))
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6) Convolution Theorem
The Circular property states that if
z
x1(n) X1(z) And
z
x2(n) X2(z) Then
z
Then x1(n) * x2(n) X1(z) X2(z)
N
Convolution of two sequences in time domain corresponds to multiplication of its Z transform sequence
in frequency domain.
7) Correlation Property
The Correlation of two sequences states that if
z
x1(n) X1(z) And
z
x2(n) X2(z) Then
∞ z
n=-∞
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n=-∞
Complex variable z is expressed in polar form as Z= rejω where r= |z| and ω is ∟z. Thus we can be
written as
∞
n=-∞
X(z) z =e
jw
= ∑ x (n) e–jωn
n=-∞
jw
X(z) z =e = x(ω) at |z| = unit circle.
Thus, X(z) can be interpreted as Fourier Transform of signal sequence (x(n) r –n). Here r–n grows with n if
r<1 and decays with n if r>1. X(z) converges for |r|= 1. hence Fourier transform may be viewed as Z
transform of the sequence evaluated on unit circle. Thus The relationship between DFT and Z transform
is given by
The frequency ω=0 is along the positive Re(z) axis and the frequency ∏/2 is along the positive Im(z)
axis. Frequency ∏ is along the negative Re(z) axis and 3∏/2 is along the negative Im(z) axis.
Im(z)
ω=∏/2
z(0,+j)
z=rejω
ω=∏ ω=0
z(-1,0) z(1,0) Re(z)
ω=3∏/2
z(0,-j)
Frequencyscale on unit circle X(z)= X(ω) on unit circle
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b0 zn + b1 znn-1+ …….+ bn
First find the roots of the denominator polynomial
a0 zm+ a1 zm-1+ …….+ am
X(z) =
1 –(0.5) z-1 4(-1/2)n u(n) – 3 (-1/4)n u(n) for |z|>1/2 causal system
7
1-3/4 z-1+1/8 z-2
z–a
2 z (2n -1 ) u(n)
(z–1)(z-2)
3 z2 + z (2n+1) u(n)
(z – 1)2
4 z3 4 – (n+3)(0.5)n u(n)
(z-1) (z–0.5)2
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n=-∞
z3 -3z2+3z -1
4. RECURSIVE ALGORITHM
The long division method can be recast in recursive form.
a0 + a1 z-1+ a2 z-2
X(z) =
b0 + b1 z-1+ b2 z-2
1-z-1 +0.3561z2
z2-3/4z+ 1/8
2. ROC dos not contain any poles of X(z). This is because x(z) becomes infinite at
the locations of the poles. Only poles affect the causality and stability of the system.
With this condition satisfied, the system will be stable. The above equation states that the LSI
system is stable if its unit sample response is absolutely summable. This is necessary and
sufficient condition for the stability of LSI system.
n=-∞
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n=-∞
Magnitudes of overall sum is less than the sum of magnitudes of individual sums.
∞
n=-∞
n=-∞
Im(z)
z-Plane
Re(z)
Poles inside unit circle gives stable system. Poles outside unit circle gives unstable system.
Poles on unit circle give marginally stable system.
6. A causal and stable system must have a system function that converges for
|z| > r < 1.
EE6403 DISCRETE TIME SYSTEMS & SIGNAL PROCESSING
z–a
2 z u(n) u(-n-1)
z–1
3 z2 (n+1)an -(n+1)an
(z – a)2
(z – a)k
5 1 δ(n) δ(n)
6 Zk δ(n+k) δ(n+k)
n=-∞ n=0
2 z transform is applicable for relaxed One sided z transform is applicable for those systems
systems (having zero initial condition). which are described by differential equations with non zero
initial conditions.
3 z transform is also applicable for non- One sided z transform is applicable for causal systems
causal systems. only.
4 ROC of x(z) is exterior or interior to ROC of x(z) is always exterior to circle hence need not to
circle hence need to specify with z be specified.
trawnswforwm.opfasidgneaelsp.
EE6403 DISCRETE TIME SYSTEMS & SIGNAL PROCESSING
Properties of one sided z transform are same as that of two sided z transform except shifting property.
1) Time delay
z+
x(n) X+(z) and
z+ k
Then x(n-k) z –k
[ X (z) + ∑ x(-n) zn]
+
k>0
n=1
2) Time advance
z+
x(n) X+(z) and
z+ k-1
Then x(n+k) z k [ X+(z) - ∑ x(n) z-n] k>0
n=0
Examples:
Q) Determine one sided z transform for following signals
1) x(n)={1,2,3,4,5} 2) x(n)={1,2,3,4,5}
One sided Z transform is very efficient tool for the solution of difference equations with nonzero
initial condition. System function of LSI system can be obtained from its difference equation.
∞
Z{x(n-1)} = ∑ x(n-1) z-n (One sided Z transform)
n=0
= x(-1) + x(0) z-1 + x(1) z-2 + x(2) z-3 +………………
1. Difference equations are used to find out the relation between input and output sequences. It
is also used to relate system function H(z) and Z transform.
2. The transfer function H(ω) can be obtained from system function H(z) by putting z=e jω.
Magnitude and phase response plot can be obtained by putting various values of ω.
Tutorial problems:
Q) A difwferwenwce.peqauadtieonepofzth.ne esytstem is given below
Y(n)= 0.5 y(n-1) + x(n)
EE6403 DISCRETE TIME SYSTEMS & SIGNAL PROCESSING
BN BJ
3. This process will continue until you obtain 2N-3 rows with last two having 3
elements. Y0,Y1,Y2
A digital filter with a system function H(z) is stable, if and only if it passes the following terms.
a. D(Z)|Z=1 >0
b. (-1)N D(Z)|Z=-1 >0
c. |b0|>|bN|, |C0|
EE6403 DISCRETE TIME SYSTEMS & SIGNAL PROCESSING
CHAPTER 3
Any signal can be decomposed in terms of sinusoidal (or complex exponential) components. Thus
the analysis of signals can be done by transforming time domain signals into frequency domain and
vice-versa. This transformation between time and frequency domain is performed with the help of
Fourier Transform(FT) But still it is not convenient for computation by DSP processors hence Discrete
Fourier Transform(DFT) is used.
Time domain analysis provides some information like amplitude at sampling instant but does not
convey frequency content & power, energy spectrum hence frequency domain analysis is used.
For Discrete time signals x(n) , Fourier Transform is denoted as x(ω) & given by
n=-∞
n=0
IDFT is given as
N-1
k=0
1 FT x(ω) is the continuous function DFT x(k) is calculated only at discrete values of ω.
of x(n). Thus DFT is discrete in nature.
4 FT equations are applicable to most DFT equations are applicable to causal, finite
of infinite sequences. duration sequences
5 In DSP processors & computers In DSP processors and computers DFT‘s are mostly
applications of FT are limited used.
because x(ω) is continuous function APPLICATION
of ω. a) Spectrum Analysis
b) Filter Design
Tutorial problems:
Q) Prove that FT x(ω) is periodic with period 2∏.
Q) Determine FT of x(n)= an u(n) for -1< a < 1.
Q) Determine FT of x(n)= A for 0 ≤ n ≤ L-1.
For calculation of DFT & IDFT two different methods can be used. First method is using mathematical
equation & second method is 4 or 8 point DFT. If x(n) is the sequence of N samples then consider W N=
e –j2 ∏ / N (twiddle factor)
k=0 W4 0 W4 0 W4 0 W4 0
[WN] =k=1 W4 0 W4 1 W4 2 W4 3
0 2 4
k=2 W4 W4 W4 W4 6
k=3 W4 0 W4 3 W4 6 W4 9
1 1 1 1
[WN] = 1 –j -1 j
-1 1 -1
1 j -1 -j
DISCRETE TIME SYSTEMS & SIGNAL PROCESSING
Tutorial problems:
Q) Compute DFT of x(n) = {0,1,2,3} Ans: x4=[6, -2+2j, -2, -2-2j ]
Q) Compute DFT of x(n) = {1,0,0,1} Ans: x4=[2, 1+j, 0, 1-j ]
Q) Compute DFT of x(n) = {1,0,1,0} Ans: x4=[2, 0, 2, 0 ]
Q) Compute IDFT of x(k) = {2, 1+j, 0, 1-j } Ans: x4=[1,0,0,1]
N-1
N-1
x(n) = 1/N ∑ X (k)e j2 ∏ kn / N
n=0 n=0
4 Thus DFT is given by In DFT and IDFT difference is of factor 1/N & sign
X(k)= [WN][xn] of exponent of twiddle factor.
Thus
t x(n)= 1/N [ WN]-1[XK]
DISCRETE TIME SYSTEMS & SIGNAL PROCESSING
PROPERTIES OF DFT
DFT
x(n) x(k)
N
1. Periodicity
Let x(n) and x(k) be the DFT pair then if
x(n+N) = x(n) for all n then
X(k+N) = X(k) for all k
Thus periodic sequence xp(n) can be given as
∞
xp(n) = ∑ x(n-lN)
l=-∞
2. Linearity
The linearity property states that if
DFT
x1(n) X1(k) And
N
DFT
x2(n) X2(k) Then
N
Then DFT
a1 x1(n) + a2 x2(n) a1 X1(k) + a2 X2(k)
N
DFT of linear combination of two or more signals is equal to the same linear combination of DFT of
individual signals.
A) A sequence is said to be circularly even if it is symmetric about the point zero on the circle. Thus
X(N-n) = x(n)
B) A sequence is said to be circularly odd if it is anti symmetric about the point zero on the circle. Thus
X(N-n) = - x(n)
D) Anticlockwise direction gives delayed sequence and clockwise direction gives advance sequence.
Thus delayed or advances sequence x`(n) is related to x(n) by the circular shift.
This property states that if the sequence is real and even x(n)= x(N-n) then DFT becomes
N-1
n=0
This property states that if the sequence is real and odd x(n)=-x(N-n) then DFT becomes
N-1
n=0
This property states that if the sequence is purely imaginary x(n)=j X I(n) then DFT becomes
N-1
n=0
N-1
n=0
5. Circular Convolution
The Circular Convolution property states that if
DFT
x1(n) X1(k) And
N
DFT
x2(n) X2(k) Then
N
DFT
Then x1(n) x2(n) x1(k) x2(k)
N
It meansthat circular convolutionof x1(n) & x2(n) is equal to multiplication of their DFT‘s. Thus
circular convolution of two periodic discrete signal with period N is given by
DISCRETE TIME SYSTEMS & SIGNAL PROCESSING
N-1
n=0
Multiplication of two sequences in time domain is called as Linear convolution while Multiplication of
two sequences in frequency domain is called as circular convolution. Results of both are totally different
but are related with each other.
DFT
x(n) x(k) x(k)*h(k) x(n)*h(n)
IDFT
*
DFT h(n) h(k)
There are two different methods are used to calculate circular convolution
1) Graphical representation form
2) Matrix approach
4 Linear Convolution of two signals returns N-1 Circular convolution returns same number of
elements where N is sum of elements in both elements that of two signals.
sequences.
Tutorial problems:
Q) The two sequences x1(n)={2,1,2,1} & x2(n)={1,2,3,4}. Find out the sequence x3(m) which is equal
to circular conv.olutioetwo.sequences. Ans: X3(m)={14,16,14,16}
DISCRETE TIME SYSTEMS & SIGNAL PROCESSING
Q) x1(n)={1,1,1,1,-1,-1,-1,-1} & x2(n)={0,1,2,3,4,3,2,1}. Find out the sequence x3(m) which is equal to
circular convolution of two sequences. Ans: X3(m)={-4,-8,-8,-4,4,8,8,4}
Q) Perform Linear Convolution of x(n)={1,2} & h(n)={2,1} using DFT & IDFT.
Q) Perform Linear Convolution of x(n)={1,2,2,1} & h(n)={1,2,3} using 8 Pt DFT & IDFT.
6. Multiplication
The Multiplication property states that if
DFT
X1(n) x1(k) and
N
DFT
X2(n) x2(k) then
N
DFT
Then x1(n) x2(n) 1/N x1(k) x2(k)
N
It means that multiplication of two sequences in time domain results in circular convolution of their
DFT‘s in frequency domain.
DFT
Then x((-n))N = x(N-n) x((-k))N = x(N-k)
N
It means that the sequence is circularly folded its DFT is also circularly folded.
Thus shifting the sequence circularly by ‗l‘ samples is equivalent to multiplying its DFT by
e –j2 ∏ k l / N
DISCRETE TIME SYSTEMS & SIGNAL PROCESSING
N-1
This means multiplication of DFT of one sequence and conjugate DFT of another sequence is equivalent
to circular cross-correlation of these sequences in time domain.
N-1 N-1
This equation give energy of finite duration sequence in terms of its frequency components.
APPLICATION OF DFT
Consider that input sequence x(n) of Length L & impulse response of same system is h(n) having M
samples. Thus y(n) output of the system contains N samples where N=L+M-1. If DFT of y(n) also
contains N samples then only it uniquely represents y(n) in time domain. Multiplication of two DFT‘s is
equivalent to circular convolution of corresponding time domain sequences. But the length of x(n) &
h(n) is less than N. Hence these sequences are appended with zeros to make their length N called as
―Zero padding‖. The N point circular convolution and linear convolution provide the same sequence.
Thus linear convolution can be obtained by circular convolution. Thus linear filtering is provided by
DFT.
When the input data sequence is long then it requires large time to get the output sequence. Hence other
techniques are used to filter long data sequences. Instead of finding the output of complete input
sequence it is broken into small length sequences. The output due to these small length sequences are
computed fast. The outputs due to these small length sequences are fitted one after another to get the
final output response.
Step 1> In this method L samples of the current segment and M-1 samples of the previous segment
forms the input data block. Thus data block will be
Step2> Unit sample response h(n) contains M samples hence its length is made N by padding zeros.
Thus h(n) also contains N samples.
Step3> The N point DFT of h(n) is H(k) & DFT of mth data block be xm(K) then corresponding DFT of
output be Y`m(k)
Step 4> The sequence ym(n) can be obtained by taking N point IDFT of Y` m(k). Initial
(M-1) samples in the corresponding data block must be discarded. The last L samples are the correct
output samples. Such blocks are fitted one after another to get the final output.
DISCRETE TIME SYSTEMS & SIGNAL PROCESSING
X(n) of Size N
Size L
X1(n)
M-1 Size L
Zeros
X2(n)
Size L
X3(n)
Y1(n)
Discard M-1 Points
Y2(n)
Discard M-1 Points
Y3(n)
Y(n) of Size N
Step 1> In this method L samples of the current segment and M-1 samples of the previous segment
forms the input data block. Thus data block will be
X1(n) ={x(0),x(1),…………….x(L-1),0,0,0,…........ }
X2(n) ={x(L),x(L+1),x(2L-1),0,0,0,0}
X3(n) ={x(2L),x(2L+2),,,,,,,,,,,,,x(3L-1),0,0,0,0}
Step2> Unit sample response h(n) contains M samples hence its length is made N by padding zeros.
Thus h(n) also contains N samples.
Step3> The N point DFT of h(n) is H(k) & DFT of mth data block be xm(K) then corresponding DFT of
output be Y`m(k)
Step 4> The sequence ym(n) can be obtained by taking N point IDFT of Y` m(k). Initial
DISCRETE TIME SYSTEMS & SIGNAL PROCESSING
(M-1) samples are not discarded as there will be no aliasing. The last (M-1) samples of current output
block must be added to the first M-1 samples of next output block. Such blocks are fitted one after
another to get the final output.
X(n) of Size N
Size L
M-1
X1(n) Zeros
Size L
M-1
X2(n) Zeros
Size L
M-1
Zeros X3(n)
Y1(n)
M-1
Points add Y2(n)
together
Y3(n)
Y(n) of Size N
1 In this method, L samples of the current In this method L samples from input
segment and (M-1) samples of the previous sequence and padding M-1 zeros forms data
segment forms the input data block. block of size N.
2 Initial M-1 samples of output sequence are There will be no aliasing in output data
discarded which occurs due to aliasing blocks.
effect.
3 To avoid loss of data due to aliasing last M- Last M-1 samples of current output block
1 samples of each data record are saved. must be added to the first M-1 samples of
next output block. Hence called as overlap
add method.
DISCRETE TIME SYSTEMS & SIGNAL PROCESSING
DFT of the signal is used for spectrum analysis. DFT can be computed on digital computer or digital
signal processor. The signal to be analyzed is passed through anti-aliasing filter and samples at the rate
of Fs≥ 2 Fmax. Hence highest frequency component is Fs/2.
Frequency spectrum can be plotted by taking N number of samples & L samples of waveforms. The
total frequency range 2∏ is divided into N points. Spectrum is better if we take large value of N & L But
this increases processing time. DFT can be computed quickly using FFT algorithm hence fast processing
can be done. Thus most accurate resolution can be obtained by increasing number of samples.
1. Large number of the applications such as filtering, correlation analysis, spectrum analysis require
calculation of DFT. But direct computation of DFT require large number of computations and hence
processor remain busy. Hence special algorithms are developed to compute DFT quickly called as Fast
Fourier algorithms (FFT).
3. The radix-2 FFT algorithms are based on divide and conquer approach. In this method, the N-point
DFT is successively decomposed into smaller DFT‘s. Because of this decomposition, the number of
computations are reduced.
N point sequence x(n) be splitted into two N/2 point data sequences f1(n) and f2(n). f1(n) contains even
numbered samples of x(n) and f2(n) contains odd numbered samples of x(n). This splitted operation is
called decimation. Since it is done on time domain sequence it is called ―Decimation in Time‖. Thus
f1(m)=x(2m) where n=0,1,… ........... N/2-1
f2(m)=x(2m+1) where n=0,1,… ............ N/2-1
N point DFT is given as
N-1
Since the sequence x(n) is splitted into even numbered and odd numbered samples, thus
N/2-1 N/2-1
Fig 1 shows that 8-point DFT can be computed directly and hence no reduction in computation.
x(0) X(0)
x(1) X(1)
x(2) X(2)
x(3) X(3)
8 Point DFT
x(7) X(7)
Fig 3 shows N/2 point DFT base separated in N/4 boxes. In such cases equations become
g1(k) =P1(k) + WN2k P2(k) ------- (5)
2k
g1(k+N/2) =p1(k) - WN P2(k) -------- (6)
DISCRETE TIME SYSTEMS & SIGNAL PROCESSING
x(0) F(0)
a A= a + WNr b
b WNr B= a - WNr b
x(0) A1 A2 X(0)
2 Point
Combine 2
DFT
Point DFT’s
2 Point
DFT Combine 4
Point DFT
2 Point
DFT Combine 2
Point DFT’s
2 Point
DFT
V= log10 N / log10 2
= log2 N
Thus if value of N is 8 then the value of v=3. Thus three stages of decimation. Total number of
butterflies will be Nv/2 = 12.
If value of N is 16 then the value of v=4. Thus four stages of decimation. Total number of butterflies
will be Nv/2 = 32.
Each butterfly operation takes two addition and one multiplication operations. Direct computation
requires N2 multiplication operation & N2 – N addition operations.
DISCRETE TIME SYSTEMS & SIGNAL PROCESSING
8 64 52 12 24 5.3 times
a A= a + WNr b
b WNr B= a - WNr b
From values a and b new values A and B are computed. Once A and B are computed, there is no need to
store a and b. Thus same memory locations can be used to store A and B where a and b were stored
hence called as In place computation. The advantage of in place computation is that it reduces memory
requirement.
Thus for computation of one butterfly, four memory locations are required for storing two complex
numbers A and B. In every stage there are N/2 butterflies hence total 2N memory locations are required.
2N locations are required for each stage. Since stages are computed successively these memory
locations can be shared. In every stage N/2 twiddle factors are required hence maximum storage
requirements of N point DFT will be (2N + N/2).
BIT REVERSAL
For 8 point DIT DFT input data sequence is written as x(0), x(4), x(2), x(6), x(1), x(5), x(3), x(7) and the
DFT sequence X(k) is in proper order as X(0), X(1), X(2), X(3), X(4), x(5), X(6), x(7). In DIF FFT it is
exactly opposite. This can be obtained by bit reversal method.
DISCRETE TIME SYSTEMS & SIGNAL PROCESSING
Decimal Memory Address x(n) in Memory Address in bit reversed New Address
binary (Natural Order) order in decimal
0 0 0 0 0 0 0 0
1 0 0 1 1 0 0 4
2 0 1 0 0 1 0 2
3 0 1 1 1 1 0 6
4 1 0 0 0 0 1 1
5 1 0 1 1 0 1 5
6 1 1 0 0 1 1 3
7 1 1 1 1 1 1 7
Table shows first column of memory address in decimal and second column as binary. Third column
indicates bit reverse values. As FFT is to be implemented on digital computer simple integer division by
2 method is used for implementing bit reversal algorithms. Flow chart for Bit reversal algorithm is as
follows,
DISCRETE TIME SYSTEMS & SIGNAL PROCESSING
DECIMAL NUMBER
B TO BE REVERSED
I=1
B1=B
B2=Int(B1/2)
B1=B2;
Is
I > log2N
Store BR as Bit
reversal of B
FLOW CHART
N/2-1 N/2-1
N/2-1 N/2-1
N/2-1 N/2-1
N/2-1
N/2-1
N/2-1
b WN r B= (a –b)WNr
BUTTERFLY COMPUTATION
DISCRETE TIME SYSTEMS & SIGNAL PROCESSING
Fig 2 shows signal flow graph and stages for computation of radix-2 DIF FFT algorithm of N=4
x(0) A X(0)
X(1) x(1)
x(0) A1 A2 X(0)
x(1) B1 B2 w8X(4)
1 DITFFT algorithms are based upon DIFFFT algorithms are based upon
decomposition of the input sequence into decomposition of the output sequence into
smaller and smaller sub sequences. smaller and smaller sub sequences.
2 In this input sequence x(n) is splitted into In this output sequence X(k) is considered to
even and odd numbered samples be splitted into even and odd numbered
samples
4 In DIT FFT input sequence is in bit In DIFFFT, input sequence is in natural order.
reversed order while the output sequence is And DFT should be read in bit reversed order.
in natural order.
1 Direct computation requires large number Radix-2 FFT algorithms requires less number
of computations as compared with FFT of computations.
algorithms.
2 Processing time is more and more for large Processing time is less hence these algorithms
number of N hence processor remains busy. compute DFT very quickly as compared with
direct computation.
3 Direct computation does not requires Splitting operation is done on time domain
splitting operation. basis (DIT) or frequency domain basis (DIF)
4 As the value of N in DFT increases, the As the value of N in DFT increases, the
efficiency of direct computation decreases. efficiency of FFT algorithms increases.
Tutorial problems:
Q) x(n)={1,2,2,1} Find X(k) using DITFFT.
Q) x(n)={1,2,2,1} Find X(k) using DIFFFT.
Q) x(n)={0.3535,0.3535,0.6464,1.0607,0.3535,-1.0607,-1.3535,-0.3535} Find X(k) using DITFFT.
Q) Using radix 2 FFT algorithm, plot flow graph for N=8.
FFT algorithms are used to compute N point DFT for N samples of the sequence x(n). This requires N/2
log2N number of complex multiplications and N log2N complex additions. In some applications DFT is
to be computed only at selected values of frequencies and selected values are less than log 2N, then direct
computations of DFT becomes more efficient than FFT. This direct computations of DFT can be
realized through linear filtering of x(n). Such linear filtering for computation of DFT can be
implemented using Goertzel algorithm.
.
By definitionNpoint DFTis given as
DISCRETE TIME SYSTEMS & SIGNAL PROCESSING
N-1
Thus for LSI system which has input x(n) and having unit sample response
yk(n) = ∑ x (m) W N
-k(n-m)
u(n–m) (3)
m=-∞
yk(n)|n=N = ∑ x (m) W N
-k(N-m)
(5)
m=-∞
Thus DFT can be obtained as the output of LSI system at n=N. Such systems can give X(k) at selected
values owf k Thus DaFdTeies cpozmpnuetetd as linear filtering operations by Goertzel Algorithm.
DISCRETE TIME SYSTEMS & SIGNAL PROCESSING
CHAPTER 4
To remove or to reduce strength of unwanted signal like noise and to improve the quality of
required signal filtering process is used. To use the channel full bandwidth we mix up two or more
signals on transmission side and on receiver side we would like to separate it out in efficient way. Hence
filters are used. Thus the digital filters are mostly used in
There are two main kinds of filter, analog and digital. They are quite different in their physical makeup
and in how they work.
An analog filter uses analog electronic circuits made up from components such as resistors,
capacitors and op amps to produce the required filtering effect. Such filter circuits are widely used in
such applications as noise reduction, video signal enhancement, graphic equalizers in hi-fi systems, and
many other areas.
In analog filters the signal being filtered is an electrical voltage or current which is the direct analogue of
the physical quantity (e.g. a sound or video signal or transducer output) involved.
A digital filter uses a digital processor to perform numerical calculations on sampled values of
the signal. The processor may be a general-purpose computer such as a PC, or a specialized DSP
(Digital Signal Processor) chip.
The analog input signal must first be sampled and digitized using an ADC (analog to digital
converter). The resulting binary numbers, representing successive sampled values of the input signal, are
DISCRETE TIME SYSTEMS & SIGNAL PROCESSING
transferred to the processor, which carries out numerical calculations on them. These calculations
typically involve multiplying the input values by constants and adding the products together. If
necessary, the results of these calculations, which now represent sampled values of the filtered signal,
are output through a DAC (digital to analog converter) to convert the signal back to analog form.
In a digital filter, the signal is represented by a sequence of numbers, rather than a voltage or
current.
The following diagram shows the basic setup of such a system.
These digital Filters are designed with digital hardware and software and are represented by
difference equation.
DIFFERENCE BETWEEN ANALOG FILTER AND DIGITAL FILTER
S. No Analog Filter Digital Filter
1 Analog filters are used for filtering Digital filters are used for filtering digital sequences.
analog signals.
2 Analog filters are designed with various Digital Filters are designed with digital hardware like FF,
components like resistor, inductor and counters shift registers, ALU and software‘s like C or
capacitor assembly language.
3 Analog filters less accurate & because of Digital filters are less sensitive to the environmental
component tolerance of active changes, noise and disturbances. Thus periodic
components & more sensitive to calibration can be avoided. Also they are extremely
environmental changes. stable.
4 Less flexible These are most flexible as software programs & control
programs can be easily modified. Several input signals
can be filtered by one digital filter.
5 Filter representation is in terms of Digital filters are represented by the difference equation.
system components.
6 An analog filter can only be changed by A digital filter is programmable, i.e. its operation is
redesigning the filter circuit. determined by a program stored in the processor's
memory. This means the digital filter can easily be
changed without affecting the circuitry (hardware).
|H (ω)|
1
ω
-ωc ωc
2. Highpass Filter
A highpass filter is made up of a stopband and a passband where the lower frequencies
of the input signal are attenuated while the higher frequencies are passed.
|H(ω)|
ω
-ωc ωc
3. Bandpass Filter
A bandpass filter is made up of two stopbands and one passband so that the lower and
higher frequencies of the input signal are attenuated while the intervening
frequencies are passed.
|H(ω)|
1
ω
-ω2 -ω1 ω2 ω1
4. Bandstop Filter
A bandstop filter is made up of two passbands and one stopband so that the lower and higher
frequencies of the input signal are passed while the intervening frequencies are attenuated. An idealized
bandstop filter frequency response has the following shape.
|H(ω)|
1
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DISCRETE TIME SYSTEMS & SIGNAL PROCESSING
ω
5. Multipass Filter
A multipass filter begins with a stopband followed by more than one passband. By default, a multipass
filter in Digital Filter Designer consists of three passbands and four stopbands. The frequencies of the
input signal at the stopbands are attenuated while those at the passbands are passed.
6. Multistop Filter
A multistop filter begins with a passband followed by more than one stopband. By default, a
multistop filter in Digital Filter Designer consists of three passbands and two stopbands.
7. All Pass Filter
An all pass filter is defined as a system that has a constant magnitude response for all frequencies.
|H(ω)| = 1 for 0 ≤ ω < ∏
The simplest example of an all pass filter is a pure delay system with system function
H(z) = Z-k. This is a low pass filter that has a linear phase characteristic.
All Pass filters find application as phase equalizers. When placed in cascade with a system that
has an undesired phase response, a phase equalizers is designed to compensate for the poor phase
characteristic of the system and therefore to produce an overall linear phase response.
IDEAL FILTER CHARACTERISTIC
1. Ideal filters have a constant gain (usually taken as unity gain) passband characteristic and
zero gain in their stop band.
2. Ideal filters have a linear phase characteristic within their passband.
3. Ideal filters also have constant magnitude characteristic.
4. Ideal filters are physically unrealizable.
4.2 TYPES OF DIGITAL FILTER
Digital filters are of two types. Finite Impulse Response Digital Filter & Infinite Impulse Response
Digital Filter.
DIFFERENCE BETWEEN FIR FILTER AND IIR FILTER
S. No FIR Digital Filter IIR Digital Filter
1 FIR system has finite duration unit sample IIR system has infinite duration unit sample
response. i.e h(n) = 0 for n<0 and n ≥ M response. i. e h(n) = 0 for n<0
Thus the unit sample response exists for the Thus the unit sample response exists for the
duration from 0 to M-1. duration from 0 to ∞.
2 FIR sypstaemdseaer zno.nn eretcursive. Thus IIR systems are recursive. Thus they use
output of
DISCRETE TIME SYSTEMS & SIGNAL PROCESSING
FIR filter depends upon present and past inputs. feedback. Thus output of IIR filter depends
upon present and past inputs as well as past
outputs
3 Difference equation of the LSI system for FIR Difference equation of the LSI system for IIR
filters becomes filters becomes
M N M
y(n)=∑ bk x(n–k) y(n)=-∑ ak y(n–k)+∑ bk x(n–k)
k=0 k=1 k=0
4 FIR systems has limited or finite memory IIR system requires infinite memory.
requirements.
5 FIR filters are always stable Stability cannot be always guaranteed.
6 FIR filters can have an exactly linear phase IIR filter is usually more efficient design in
response so that no phase distortion is terms of computation time and memory
introduced in the signal by the filter. requirements. IIR systems usually requires less
processing time and storage as compared with
FIR.
7 The effect of using finite word length to Analogue filters can be easily and readily
implement filter, noise and quantization errors transformed into equivalent IIR digital filter.
are less severe in FIR than in IIR. But same is not possible in FIR because that
have no analogue counterpart.
8 All zero filters Poles as well as zeros are present.
9 FIR filters are generally used if no phase IIR filters are generally used if sharp cutoff and
distortion is desired. high throughput is required.
Example: Example:
System described by System described by
Y(n) = 0.5 x(n) + 0.5 x(n-1) is FIR filter. Y(n) = y(n-1) + x(n) is IIR filter.
h(n)={0.5,0.5} h(n)=an u(n) for n≥0
4. 3 STRUCTURES FOR FIR SYSTEMS
FIR Systems are represented in four different ways
1. Direct Form Structures
2.
DISCRETE TIME SYSTEMS & SIGNAL PROCESSING
3. Frequency-Sampling Structures
4. Lattice structures.
1. DIRECT FORM STRUCTURE OF FIR SYSTEM
The convolution of h(n) and x(n) for FIR systems can be written as
M-1
y(n)=∑ h(k) x(n–k) (1)
k=0
The above equation can be expanded as,
Y(n)= h(0) x(n) + h(1) x(n-1) + h(2) x(n-2) + …………… + h(M-1) x(n-M+1) (2)
Implementation of direct form structure of FIR filter is based upon the above equation.
x(n) Z-1 x(n-1) Z-1 Z-1 x(n-M+1)
+ +
+ +
h(0)x(n) h(0)x(n)+
h(1)x(n) y(n)
FIG - DIRECT FORM REALIZATION OF FIR SYSTEM
1) There are M-1 unit delay blocks. One unit delay block requires one memory location.
Hencedirect form structure requires M-1 memory location
2) The multiplication of h(k) and x(n-k) is performed for 0 to M-1 terms. Hence M multiplications
and M-1 additions are required.
3) Direct form structure is often called as transversal or tapped delay line filter.
2. CASCADE FORM STRUCTURE OF FIR SYSTEM
In cascade form, stages are cascaded (connected) in series. The output of one system is input to another.
Thus total K number of stages are cascaded. The total system function 'H' is given by
H= H1(z) . H2(z)……………………. Hk(z) (1)
H= Y1(z)/X1(z). Y2(z)/X2(z). ……………Yk(z)/Xk(z) (2)
k
H(z)=π Hk(z) (3)
k=1
DISCRETE TIME SYSTEMS & SIGNAL PROCESSING
+ +
y(n) y(n-1)
FIG - DIRECT FORM REALIZATION OF FIR SECOND ORDER SYSTEM
4. 4 STRUCTURES FOR IIR SYSTEMS
IIR Systems are represented in four different ways
1. Direct Form Structures Form I and Form II
2. Cascade Form Structure
3. Parallel Form Structure
4. Lattice and Lattice-Ladder structure.
DIRECT FORM STRUCTURE FOR IIR SYSTEMS
IIR systems can be described by a generalized equations as
N M
y(n)=-∑ ak y(n–k)+∑ bk x(n–k) (1)
k=1 a
k=d0
DISCRETE TIME SYSTEMS & SIGNAL PROCESSING
Z transform is given as
M N
H(z) = ∑ bk z–k / 1+ ∑ ak z–k (2)
K=0 k=1
M N
Here H1(z) = ∑ bk z–k And H2(z) = 1+ ∑ ak z–k
K=0 k=0
Overall IIR system can be realized as cascade of two function H1(z) and H2(z). Here H1(z) represents
zeros of H(z) and H2(z) represents all poles of H(z).
1. Direct form I realization of H(z) can be obtained by cascading the realization of H1(z)
which is all zero system first and then H2(z) which is all pole system.
2. There are M+N-1 unit delay blocks. One unit delay block requires one memory location.Hence direct
form structure requires M+N-1 memory locations.
3. Direct Form I realization requires M+N+1 number of multiplications and M+N numberof
additions and M+N+1 number of memory locations.
DIRECT FORM – I
X(n) bo y(n)
+ +
Z-1 Z-1
b1 -a1
+ +
Z-1 Z-1
b2 -a2
+ +
bM-1 -aN-1
+ +
-1
Z Z-1
bM -aN
DIRECT FORM - II
1. Direct form realization of H(z) can be obtained by cascading the realization of H1(z) which is all
pole system and H2(z) which is all zero system.
2. Two delay elements of all pole and all zero system can be merged into single delay element.
3. Direct Form II structure has reduced memory requirement compared to Direct form I structure. Hence
it is called canonic form.
4. The direct form II requires same number of multiplications(M+N+1) and additions (M+N) as that of
direct form I.
b0
X(n) + Y(n)
+
-a1
Z-1 b1
+
+
Z-1
-a2 b2
+ +
-aN-1 bN-1
+
+
Z-1
-aN bN
Z-1
+
+
-ak1 bk1
Z-1
+
+
-ak2 bk2
+
WW
DISCRETE TIME SYSTEMS & SIGNAL PROCESSING
H1(z) +
H2(z) +
X(n)
k1(z) +
Z-1
+
-ak1
Z-1
-ak2
+
+
FIG - DIRECT FORM REALIZATION OF IIR SECOND ORDER SYSTEM (PARALLEL)
WW
DISCRETE TIME SYSTEMS & SIGNAL PROCESSING
1) If σ = 0 then r=1
2) If σ < 0 then 0 < r < 1
3) If σ > 0 then r> 1
Thus
1) Left side of s-plane is mapped inside the unit circle.
2) Right side of s-plane is mapped outside the unit circle.
3) jΩ axis is in s-plane is mapped on the unit circle.
Im(z)
1 jΩ
Re(z) σ
Im(z)
1 jΩ
Re(z) σ
n
Ha(s)= Σ Ck / s-pk (1)
k=1
where pk are the poles of the analog filter and ck are the coefficients of partial fraction expansion. The
impulse response of the analog filter ha(t) is obtained by inverse Laplace transform and given as
n
ha(t) = Σ Ck epkt (2)
k=1
The unit sample response of the digital filter is obtained by uniform sampling of ha(t).
h(n) = ha(nT) n=0,1,2. ………….
n
h(n) =Σ Ck epknT (3)
k=1
System function of digital filter H(z) is obtained by Z transform of h(n).
N ∞
H(z) =Σ Ck Σ epkT z-1 n
(4)
k=1 n=0
Using the standard relation and comparing equation (1) and (4) system function of digital filter is given
as
1 1
s - pk 1- epkT z-1
STANDARD RELATIONS IN IIR DESIGN
S. No Analog System Function Digital System function
1
1
1
1- eaT z-1
s–a
2
1- e-aT (cos bT) z-1
s+a
1-2e-aT (cos bT)z-1+ e-2aTz-2
(s+a)2 + b2
DISCRETE TIME SYSTEMS & SIGNAL PROCESSING
2 1
(s+1) (s+2) 0.148 z
(for sampling frequency of 5 z2 - 1.48 z + 0.548
samples/sec)
3 10
(s+2) 10
(for sampling time is 1 - z-1
0.01 sec)
5. But the main disadvantage of frequency warping is that it does change the shape of the desired filter
frequency response. In particular, it changes the shape of the transition bands.
CONVERSION OF ANALOG FILTER INTO DIGITAL FILTER
Z is represented as rejω in polar form and relationship between Z plane and S plane in BZT method is
given as
2z-1
S=
T z+1
2 rejω - 1
S=
T rejω + 1
2 r (cos ω + j sin ω) -1
S=
T r (cos ω + j sin ω) +1
2 r2 -1 + 2r j 2 r sin ω
S
T 1+r2+2r cos ω p11+r2+2r cos ω
Comparing the above equation with S= σ + j Ω. We have
σ= 2 r2 -1
T 1+ r2+2r cos ω
Ω= 2 2 r sin ω
T 1+ r2+2r cos ω
Here we have three condition
1) If σ < 0 then 0 < r < 1
2) If σ > 0 then r > 1
3) If σ = 0 then r=1
When r =1
Ω=
2 sin ω
T 1+cos ω
Ω=
= (2/T) tan (ω/2)
ω=
2 tan -1 (ΩT/2)
The above equations shows that in BZT frequency relationship is non-linear. The frequency relationship
is plotted as
DISCRETE TIME SYSTEMS & SIGNAL PROCESSING
Ω 2 tan -1 (ΩT/2)
ΩT
3 3 1 / s3 + 2 s2 + 2s +1 s3 / s3 + 2 s2 + 2s +1
METHOD FOR DESIGNING DIGITAL FILTERS USING BZT
step 1. Find out the value of ωc*.
Step 4. Find out the digital filter transfer function. Replace s by (z-1)/(z+1)
H(z)= z-1
1.325z -0.675
Tutorial problems:
Q) Design second order low pass butterworth filter whose cutoff frequency is 1 kHz at sampling
frequency of 104 sps.
Q) First order low pass butterworth filter whose bandwidth is known to be 1 rad/sec . Use BZT method
to design digital filter of 20 Hz bandwidth at sampling frequency 60 sps.
Q) Second order low pass butterworth filter whose bandwidth is known to be 1 rad/sec . Use BZT
method to obtain transfer function H(z) of digital filter of 3 DB cutoff frequency of 150 Hz and
sampling frequency 1.28 kHz.
Q) The transfer function is given as s2+1 / s2+s+1 The function is for Notch filter with frequency 1
rad/sec. Design digital Notch filter with the following specification
(1) Notch Frequency= 60 Hz
(2) Sampling frequency = 960 sps.
|H(𝜔)|2
fC f
1
|Ha(Ω)|2=
1 + (Ω/Ωc)2N
The squared magnitude function for an analog butterworth filter is of the form.
1
|Ha(Ω)|2=
1 + (Ω/Ωc)2N
N indicates order of the filter and Ωc is the cutoff frequency (-3DB frequency).
At s = j Ω magnitude of H(s) and H(-s) is same hence
Ha(s) Ha(-s) = 1
1 + (-s2/Ωc2)N
To find poles of H(s). H(-s) , find the roots of denominator in above equation.
-s2 = (-1)1/N
Ωc2
As e j(2k+1) ∏ = -1 where k = 0,1,2,… ...... N-1.
-s2 = (e j(2k+1) ∏ 1/N
)
Ωc2
s2 = (-1) Ωc2 e j(2k+1) ∏ / N
Taking the square root we get poles of s.
j(2k+1) ∏ / N 1/2
pk = + √-1 Ωc [ e ]
Pk = + j Ωc e j(2k+1) ∏ / 2N
As e j∏/2 = j
DISCRETE TIME SYSTEMS & SIGNAL PROCESSING
Pk = + Ωc e j(N+2k+1) ∏ / 2N (1)
This equation gives the pole position of H(s) and H(-s).
FREQUENCY RESPONSE CHARACTERISTIC
The frequency response characteristic of |Ha(Ω)|2 is as shown. As the order of the filter N increases, the
butterworth filter characteristic is more close to the ideal characteristic. Thus at higher orders like N=16
the butterworth filter characteristic closely approximate ideal filter characteristic. Thus an infinite order
filter (N ∞) is required to get ideal characteristic.
|Ha(Ω)|2 N=18
N=6
N=2
|Ha(Ω)|
Ap
0.5
Ω
Ωp Ωc Ωs
Ap= attenuation in passband.
As= attenuation in stopband.
Ωp = passband edge frequency
Ωs = stopbandedge frequency
DISCRETE TIME SYSTEMS & SIGNAL PROCESSING
(Ωs/Ωc)2N = (1/As2) – 1
Ωs 2N = (1/As2)-1
Ωp (1/Ap2)-1
Hence order of the filter (N) is calculated as
(1/As2)-1
log
(1/Ap2)-1
(2)
N= 0.5
log (Ωs/ Ωp)
log((1/As2) -1) (2A)
N= 0.5
log (Ωs/ Ωc)
And cutoff frequency Ωc is calculated as
Ωc = Ωp (3)
[(1/Ap2) -1]1/2N
If As and Ap values are given in DB then
As (DB) = - 20 log As
log As = -As /20
As = 10 -As/20
(As)-2 = 10 As/10
(As)-2 = 10 0.1 As DB
Hence equation (2) is modified as
DISCRETE TIME SYSTEMS & SIGNAL PROCESSING
100.1 As -1
log
100.1 Ap -1
(4)
N= 0.5
log (Ωs/ Ωp)
Q) Design a digital filter using a butterworth approximation by using impulse invariance.
Example
|Ha(Ω)|
0.89125
0.1778
0.2∏ 0.3∏ Ω
(1/As2)-1
log
(1/Ap2)-1
N= 0.5
log (Ωs/ Ωp)
N= 5.88
A) Order of the filter should be integer.
B) Always go to nearest highest integer vale of N.
Hence N=6
Step 3) To find out the cutoff frequency (-3DB frequency)
Ωc = Ωp
[(1/Ap2) -1]1/2N
cutoff frequency Ωc = 0.7032
Step 4) To find out the poles of analog filter system function.
Pk = + Ωc e j(N+2k+1) ∏ / 2N
As N=6 the value of k = 0,1,2,3,4,5.
K Poles
-0.182 + j 0.679
0 P0= + 0.7032 e j7∏/12
0.182 - j 0.679
-0.497 + j 0.497
1 P1= + 0.7032 e j9∏/12
0.497 - j 0.497
-0.679 + j 0.182
2 P2= + 0.7032 e j11∏/12
0.679 - j 0.182
5
-0.182 - j 0.679
P5= + 0.7032 e j17∏/12
0.182 + j 0.679
For stable filter all poles lying on the left side of s plane is selected. Hence
S1 = -0.182 + j 0.679 S1* = -0.182 - j 0.679
S2 = -0.497 + j 0.497 S2* = -0.497 - j 0.497
S3 = -0.679 + j 0.182 S3* = -0.679 - j 0.182
Step 5) To determine the system function (Analog Filter)
Ha(s) = Ωc6
(s-s1)(s-s1*) (s-s2)(s-s2*) (s-s3)(s-s3*)
Hence
Ha(s) = (0.7032)6
(s+0.182-j0.679)(s+0.182+j0.679) (s+0.497-j0.497)
(s+0.497+j0.497) (s+0.679-j0.182)(s+0.679-j0.182)
Ha(s) = 0.1209
[(s+0.182)2 +(0.679)2] [(s+0.497)2+(0.497)2] [(s+0.679)2-(0.182)2]
Tutorial problems:
Q) Given for low pass butterworth filter
Ap= -1 db at 0.2∏
As= -15 w atw0..3p∏BrainKart.com
dbw
DISCRETE TIME SYSTEMS & SIGNAL PROCESSING
FREQUENCY TRANSFORMATION
When the cutoff frequency Ωc of the low pass filter is equal to 1 then it is called normalized filter.
Frequency transformation techniques are used to generate High pass filter, Bandpass and bandstop filter
from the lowpass filter system function.
FREQUENCY TRANSFORMATION (ANALOG FILTER)
S. No Type of transformation Transformation ( Replace s by)
s
1 Low Pass
ωlp
ωlp - Password edge frequency of another LPF
ωhp
2 High Pass
s
ωhp = Password edge frequency of HPF
(s2 + ωl ωh )
s (ωh - ωl )
3 Band Pass
ωh - higher band edge frequency
ωl - Lower band edge frequency
4 wBand Stop
s (ωh - ωl)
DISCRETE TIME SYSTEMS & SIGNAL PROCESSING
s2+ ωh ωl
ωh - higher band edge frequency
ωl - Lower band edge frequency
z-1 - a
1 Low Pass
1 - az-1
- (z-1+ a)
2 High Pass
1 + az-1
z-2 - a1z-1 + a2
4 Band Stop
a2z-2 - a1z-1 + 1
Example:
Q) Design high pass butterworth filter whose cutoff frequency is 30 Hz at sampling frequency of 150
Hz. Use BZT and Frequency transformation.
Step 1. To find the prewarp cutoff frequency
ωc* = tan (ωcTs/2)
= 0.7265
Step 2. LPF to HPFtransformation
DISCRETE TIME SYSTEMS & SIGNAL PROCESSING
H(z)= z-1
1.7265z - 0.2735
Tutorial problems:
Q) Design second order band pass butterworth filter whose passband of 200 Hz and 300 Hz and
sampling frequency is 2000 Hz. Use BZT and Frequency transformation.
Q) Design second order band pass butterworth filter which meet following specification
Lower cutoff frequency = 210 Hz
Upper cutoff frequency = 330 Hz
Sampling Frequency = 960 sps
Use BZT and Frequency transformation.
M-1
y(n)=∑ bk x(n–k) (1)
DISCRETE TIME SYSTEMS & SIGNAL PROCESSING
k=0
And the coefficient bk are related to unit sample response as
H(n) = bn for 0 ≤ n ≤ M-1
= 0 otherwise.
We can expand this equation as
Y(n)= b0 x(n) + b1 x(n-1) + …….. + bM-1 x(n-M+1) (2)
System is stable only if system produces bounded output for every bounded input. This is stability
definition for any system.
Here h(n)={b0, b1, b2, } of the FIR filter are stable. Thus y(n) is bounded if input x(n) is bounded. This
means FIR system produces bounded output for every bounded input. Hence FIR systems are always
stable.
Symmetric and Anti-symmetric FIR filters
1. Unit sample response of FIR filters is symmetric if it satisfies following condition
h(n)= h(M-1-n) n=0,1,2… ................M-1
2. Unit sample response of FIR filters is Anti-symmetric if it satisfies following condition
h(n)= -h(M-1-n) n=0,1,2…………….M-1
FIR Filter Design Methods
The various method used for FIR Filer design are as follows
1. Fourier Series method
2. Windowing Method
3. DFT method
4. Frequency sampling Method. (IFT Method)
GIBBS PHENOMENON
Consider the ideal LPF frequency response as shown in Fig 1 with a normalizing angular cut off
frequency Ωc.
1. In Fourier series method, limits of summation index is -∞ to ∞. But filter must have finite terms.
Hence limit of summation index change to -Q to Q where Q is some finite integer. But this type of
truncation may result in poor convergence of the series. Abrupt truncation of infinite series is equivalent
to multiplying infinite series with rectangular sequence. i.e at the point of discontinuity some oscillation
may be observed in resultant series.
2. Consider the example of LPF having desired frequency response H d (ω) as shown in figure. The
oscillations or ringing takes place near band-edge of the filter.
3. This oscillation or ringing is generated because of side lobes in the frequency response W(ω) of the
window function. This oscillatory behavior is called "Gibbs Phenomenon".
Truncated response and ringing effect is as shown in fig 3.
WINDOWING TECHNIQUE
Windowing is the quickest method for designing an FIR filter. A windowing function simply
truncates the ideal impulse response to obtain a causal FIR approximation that is non causal and
infinitely long. Smoother window functions provide higher out-of band rejection in the filter response.
However this smoothness comes at the cost of wider stopband transitions.
Various windowing method attempts to minimize the width of the main lobe (peak) of the
frequency response. In addition, it attempts to minimize the side lobes (ripple) of the frequency
responsew
.
DISCRETE TIME SYSTEMS & SIGNAL PROCESSING
Rectangular Window: Rectangular This is the most basic of windowing methods. It does not require
any operations because its values are either 1 or 0. It creates an abrupt discontinuity that results in sharp
roll-offs but large ripples.
Kaiser Window: This windowing method is designed to generate a sharp central peak. It has reduced
side lobes and transition band is also narrow. Thus commonly used in FIR filter design.
Hamming Window: This windowing method generates a moderately sharp central peak. Its ability to
generate a maximally flat response makes it convenient for speech processing filtering.
DISCRETE TIME SYSTEMS & SIGNAL PROCESSING
Hanning Window: This windowing method generates a maximum flat filter design.
ωo ω1 ω
DIGITAL RESONATOR
A digital resonator is a special two pole bandpass filter with a pair of complex conjugate poles
located near the unit circle. The name resonator refers to the fact that the filter has a larger magnitude
response in the vicinity of the pole locations. Digital resonators are useful in many applications,
including simple bandpass filtering and speech generations.
IDEAL FILTERS ARE NOT PHYSICALLY REALIZABLE. Why?
Ideal filters are not physically realizable because Ideal filters are anti-causal and as only causal systems
are physically realizable.
Proof:
Let take example of ideal lowpass filter.
H(ω) = 1 for - ωc ≤ ω ≤ ωc
= 0 elsewhere
The unit sample response of this ideal LPF can be obtained by taking IFT of H(ω).
h(n)=. 𝐻(𝑗𝑤
∞
−∞
)𝑒 𝑗𝑤𝑛𝑑𝑤 (1)
DISCRETE TIME SYSTEMS & SIGNAL PROCESSING
1_
[ω]ωc
2∏ -ωc
sin (ωcn )
h(n) = for n≠0
∏n
𝑤𝑐
for n=0
𝑛
LSI system is causal if its unit sample response satisfies following condition.
h(n) = 0 for n<0
In above figure h(n) extends -∞ to ∞. Hence h(n) ≠0 for n<0. This means causality condition is not
satisfied by the ideal low pass filter. Hence ideal low pass filter is non causal and it is not physically
realizable.
EXAMPLESOF SIM
PLED
IG
ITAL FILTERS:
DISCRETE TIME SYSTEMS & SIGNAL PROCESSING
This is again a first order filter, since one previous input value is required to give the current output.
Example (5): yn = (xn + xn-1) / 2
The order of this filter is again equal to 1 since it uses just one previous input value.
Example (6): yn = (xn + xn-1 + xn-2) / 3
To compute the current output yn, two previous inputs (xn-1 and xn-2) are needed; this is therefore a
second-order filter.
Example (7): yn = (xn - xn-2) / 2
The filter order is again 2, since the processor must store two previous inputs in order to compute the
current output. This is unaffected by the absence of an explicitxn-1 term in the filter expression.
Q) For each of the following filters, state the order of the filter and identify the values of its coefficients:
(a) yn = 2xn - xn-1 A) Order = 1: a0 = 2, a1 = -1
(b) yn = xn-2 B) Order = 2: a0 = 0, a1 = 0, a2 = 1
(c) yn = xn - 2xn-1 + 2xn-2 + xn-3 C) Order = 3: a0 = 1, a1 = -2, a2 = 2, a3 = 1
DISCRETE TIME SYSTEMS & SIGNAL PROCESSING
CHAPTER 5
The most fundamental mathematical operation in DSP is sum of products also called as dot of products.
Y(n)= h(0)*x(n) + h(1)*x(n-1) +………+ h(N-1)*x(n-N)
This operation is mostly used in digital filter designing, DFT, FFT and many other DSP applications. A
DSP is optimized to perform repetitive mathematical operations such as the dot product. There are five
basic requirements of s DSP processor to optimize the performance They are
1) Fast arithmetic
2) Extended precision
3) Fast Execution - Dual operand fetch
4) Fast data exchange
5) Fast operations
6) Circular buffering
S. No Requirements Features of DSP processor
1 Fast Arithmetic Faster MACs means higher bandwidth.
Able to support general purpose math functions, should have ALU
and a programmable shifter function for bit manipulation.
Powerful interrupt structure and timers
2 Extended precision A requirement for extended precision in the accumulator register.
High degree of overflow protection.
3 Fast Execution Parallel Execution is required in place of sequential.
Instructions are executed in single cycle of clock called as True
instruction cycle as oppose to multiple clock cycle.
Multiple operands are fetched simultaneously. Multi-processing
Ability and queue, pipelining facility
Address generation by DAG's and program sequencer.
4 Fast data Exchange Multiple registers, Separate program and data memory and Multiple
operands fetch capacity
5 Fast Operations Program and data memories are on chip memory and extendable off-
chip
No multiplexing is used. Separate address, data and control bus.
Powerful instruction set and various addressing modes.
6 Circular shift operations Circular Buffers
3. This architecture is giving good performance when all the required tasks can be executed serially.
4.For large processing applications like DSP applications Von-Neumann architecture is not suitable as
processing speed is less. Processing speed can be increased by pipelining up to certain extend which is
not sufficient for DSP applications. In order to perform a single FIR filter multiply-accumulate, an
instruction is fetched from the program memory, and during the same cycle, a coefficient can be fetched
from the data memory. A second cycle is required to fetch the data word from data memory
HARVARD
B: PROGRAM PM Address Bus DM Address Bus DATA
MEMORY:
CPU MEMORY:
Instruction
Only PM Data Bus DM Data Bus Data Only
ADI MODIFIED
C: PROGRAM PM Address Bus CPU DM Address Bus DATA
MEMORY: MEMORY:
HARVARD Instructions Data Only
and Data PM Data Bus Instructio
Cache
n DM Data Bus
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Figure: MICROPROCESSOR ARCHITECTURES
DISCRETE TIME SYSTEMS & SIGNAL PROCESSING
1. Data and program instructions each have separate memories and buses as shown.
Program memory address and data buses for program memory and data memory
address and data buses for data memory.
2. Since the buses operate independently, program instructions and data can be
fetched at the same time. Therefore improving speed over the single bus Von
Neumann design.
ADSP-21xx family DSP's are used in high speed numeric processing applications.
PROCESSOR CORE
Address Bus 1
MEMORY A
Data Bus 1
Address Bus 2
Data Bus 2
MEMORY A
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MEMORY B
SCE 100
DISCRETE TIME SYSTEMS & SIGNAL PROCESSING
Instruction
Data Register
Address Cache Program
Generator 1 Generator 2 Memory Sequencer
PMA BUS
DMA BUS
PMD BUS
Bus
Exchange
DMD BUS
R BUS
The ADSP-21xx processors have five internal buses to ensure data transfer.
1. PMA and DMA buses are used internally for addresses associated with Program
and data memory. The PMD and DMD are used for data associated with memory
spaces. Off Chip, the buses are multiplexed into a single external address bus and a
single external data bus. The address spaces are selected by the appropriate
control signal.
101
DISCRETE TIME SYSTEMS & SIGNAL PROCESSING
2. The result (R) bus transfers the intermediate results directly between various
computational units.
3. PMA bus is 14-bits wide allowing direct access of up to 16k words of code and
data. PMD bus is 24 bits wide to accommodate the 24 bit instruction width.
The DMA bus 14 bits wide allowing direct access of up to 16k words of data.The
DMD bus is 16 bit wide.
4. The DMD bus provides a path for the contents of any register in the processor to
be transferred to any other register or to any external data memory location in a
single cycle. DMA address comes from two sources. An absolute value specified in
the instruction code (direct addressing) or the output of DAG (Indirect addressing).
The PMD bus can also be used to transfer data to and from the
computational units thro direct path or via PMD-DMD bus exchange unit.
COMPUTATIONAL UNITS:
The processor contains three -independent computational units. ALU, MAC
(Multiplier-accumulator) and the barrel shifter. The computational units process 16-
bit data directly. ALU is 16 bits wide with two 16 bit input ports and one output
port. The ALU provides a standard set of arithmetic and logic functions.
ALU Features
1. Add, subtract, Negate, increment, decrement, Absolute value, AND, OR, EX-OR,
Not etc.
2. Bitwise operators, Constant operators
3. Multi-precision Math Capability
4. Divide Primitives and overflow support.
MAC:
The MAC performs high speed single-cycle multiply/add and multiply/subtract
operations. MAC has two 16 bit input ports and one 32 bit product output port. 32
bit product is passed to a 40 bit adder/subtractor which adds or subtracts the new
product from the content of the multiplier result (MR). It also contains a 40 bit
accumulator which provides 8 bit overflow in successive additions to ensure that no
loss of data occurs. 256 overflows would have to occur before any data is lost. A set
of background registers is also available in the MAC for interrupts service routine.
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SHIFTER:
The shifter performs a complete set of shifting functions like logical and arithmetic
shifts (circular or linear shift) , normalization (fixed point to floating point
conversion), demoralization (floating point to fixed point conversion) etc
ALU, MAC and shifter are connected to DMD bus on one side and to R bus on
other side. All three sections contains input and output registers which are
accessible from the internal DMD bus. Computational operations generally take the
operands from input registers and load the result into an output register.
DATA ADDRESS GENERATORS (DAG):
Two DAG's and a powerful program sequencer ensure efficient use of these
computational units. The two DAG's provides memory addresses when memory
data is transferred to or from the input or output registers. Each DAG keeps track of
up to four address pointers. Hence jumps, branching types of instructions are
implemented within one cycle. With two independent DAG's, the processor can
generate two address simultaneously for dual operand fetches.
DAG1 can supply addresses to data memory only. DAG2 can supply addresses to
either data memory or program memory. When the appropriate mode bit is set in
mode status register (MSTAT), the output address of DAG1 is bit-reversed before
being driven onto the address bus. This feature facilitates addressing in radix-2 FFT
algorithm.
PROGRAM SEQUENCER:
The program sequencer exchanges data with DMD bus. It can also take from
PMD bus. It supplies instruction address to program memory. The sequencer is
driven by the instruction register which holds the currently executing instruction.
The instruction register introduces a single level of pipelining into the program
flow. Instructions are fetched and loaded into the instruction register during one
processor cycle, and executed during the following cycle while the next instruction
is pre-fetched. The cache memory stores up to 16 previously executed instructions.
Thus data memory on PMD bus is more efficient because of cache memory. This
also makes pipelining and increase the speed of operations.
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.SEG/RAM/ABS=0X800/DM/DATA PRIVATE
MEMORY
.PORT/RAM/ABS=0x100 DATA MEMORY IO
PORT
.PORT/RAM/ABS=0x200 AD PORT
.PORT/RAM/ABS=0x300 DA PORT
.ENDSYS
The sample system configuration file (.SYS) is shown. .SEG directive is used to
declare the system's physical memory segments and its characteristics. .PORT
directive declares the memory mapped IO port. .ENDSYS indicates the end of .SYS
file.
ASSEMBLER
The assembler translated source code into object code modules. The source code is
written in assembly language file (.DSP) Assembler reads .DSP file and generates
four
output filed with the same root name. Object file(.OBJ), Code File(.CDE),
Initialization File (.INT), List File(.LST) etc. The file can be assembled by the
following command.
ASM21FILTER
S.No File Extension Application
1 .OBJ Binary codes for instruction, Memory allocation
and symbol declaration, Addresses of the
instructions
2 .CDE Instruction opcodes
3 .INT Initialization information
4 .LST Documentation
LINKER
The linker is a program used to join together object files into one large
object file. The linker produces a link file which contains the binary codes for all
the combined modules. The linker uses .INT, .CDE, .OBJ and .ACH file and
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generates three files. Map listing file (.MAP), Memory Image File (.EXE) and
Symbol table (.SYM).
LD21 FILTER -a SAMPLE -e FILTER
Here Filter is the input file name, sample.ACH file is system architecture file name
and FILTER.EXE is output file name.
DEBUGGER
A debugger is a program which allows user to load object code program into system
memory, execute the program and debug it. The debugger allows the user to look at
the contents of registers and memory locations etc. We can change the contents of
registers and memory locations at run time, generates breakpoints etc.
SIMULATOR
The multiprogramming environment can be tested using the simulator. When
simulated, the filter program produces output data and stores in common data
memory. Simulator command is used to dump form data memory to store the dual
port data memory image on disk which can be reloaded and tested.
APPLICATIONS OF DSP
1. SPEECH RECOGNITION
Basic block diagram of a speech recognition system is shown in Fig 1
1. In speech recognition system using microphone one can input speech or voice.
The analog speech signal is converted to digital speech signal by speech digitizer.
Such digital signal is called digitized speech.
2. The digitized speech is processed by DSP system. The significant features of
speech such as its formats, energy, linear prediction coefficients are extracted.The
template of this extracted features are compared with the standard reference
templates.The closed matched template is considered as the recognized word.
3. Voice operated consumer products like TV, VCR, Radio, lights, fans and voice
operated telephone dialing are examples of DSP based speech recognized
devices.
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Impulse Voiced
Synthetic
Train speech
Generator Time
× varying
Random digital filter
number
generator Unvoiced
Pulse
Voiced
Generator Synthetic
speech
Digital Time
filter varying
digital
White
filter
Noise
generator Unvoiced
Filter Coefficients
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3. SOUND PROCESSING
1. In sound processing application, Music compression(MP3) is achieved by
converting the time domain signal to the frequency domain then removing
frequencies which are no audible.
2. The time domain waveform is transformed to the frequency domain using a filter
bank. The strength of each frequency band is analyzed and quantized based on how
much effect they have on the perceived decompressed signal.
3. The DSP processor is also used in digital video disk (DVD) which uses MPEG-2
compression, Web video content application like Intel Indeo, real audio.
4. Sound synthesis and manipulation, filtering, distortion, stretching effects are also
done by DSP processor. ADC and DAC are used in signal generation and recording.
4. ECHO CANCELLATION
In the telephone network, the subscribers are connected to telephone exchange by
two wire circuit. The exchanges are connected by four wire circuit. The two wire
circuit is bidirectional and carries signal in both the directions. The four wire circuit
has separate paths for transmission and reception. The hybrid coil at the exchange
provides the interface between two wire and four wire circuit which also provides
impedance matching between two wire and four wire circuits. Hence there are no
echo or reflections on the lines. But this impedance matching is not perfect because
it is length dependent. Hence for echo cancellation, DSP techniques are used as
follows.
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microphone. The sound going through the echo-loop is transformed and delayed,
and noise is added, which complicate the substraction process.
2. Let be the input signal going to the loudspeaker; let be the signal picked up
by the microphone, which will be called the desired signal. The signal after
substraction will be called the error signal and will be denoted by . The adaptive
filter will try to identify the equivalent filter seen by the system from the
loudspeaker to the microphone, which is the transfer function of the room
the loudpeaker and microphone are in.
3. This transfer function will depend heavily on the physical characteristics of the
environment.In broad terms, a small room with absorbing walls will origninate
just a few, first order reflections so that its transfer function will have a short
impulse response. On the other hand, large rooms with reflecting walls will have
a transfer function whose impulse response decays slowly in time, so that
echo cancellation will be much more difficult.
5. VIBRATION ANALYSIS
1. Normally machines such as motor, ball bearing etc systems vibrate depending
upon the speed of their movements.
2. In order to detect fault in the system spectrum analysis can be performed. It
shows fixed frequency pattern depending upon the vibrations. If there is fault in the
machine, the predetermined spectrum is changes. There are new frequencies
introduced in the spectrum representing fault.
3. This spectrum analysis can be performed by DSP system. The DSP system can
also be used to monitor other parameters of the machine simultaneously.
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There are one sided(right and left sequences) and two sided sequences are
present in the Z Transform pair.
It cosists of two duration they are
Finite duration
Infinite duration
IF ITS RIGHT SIDED SEQUENCE ------ROC LIES BETWEEN Z = ∞
IF ITS LEFT SIDED SEQUENCES ----- ROC LIES BETWEEN Z = 0
IF ITS BOTH SIDED SEQUENCES ----- ROC LIES BETWEEN Z= 0 &
Z = ∞.
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REFERENCES:
1. Poorna Chandra S, Sasikala. B ,Digital Signal Processing, Vijay
Nicole/TMH,2013.
2. B.P.Lathi, ‗Principles of Signal Processing and Linear Systems‘, Oxford
University Press, 2010
3. Taan S. ElAli, ‗Discrete Systems and Digital Signal Processing with Mat Lab‘,
CRC Press, 2009.
4. Sen M.kuo, woonseng…s.gan, ―Digital Signal Processors, Architecture,
Implementations &
Applications, Pearson,2013
5. Dimitris G.Manolakis, Vinay K. Ingle, applied Digital Signal
Processing,Cambridge,2012
6. Lonnie C.Ludeman ,‖Fundamentals of Digital Signal Processing‖,Wiley,2013
7. R.L Lekha , Digital Signal Processing by Lakshmi publications.
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GLOSSARY TERMS:
DDC:
Digital Down ConverterTuner Mix a signal down to baseband. A DDC operates in
the complex domain and consists of a frequency mixer, a LPF, and a decimator.
SeethedownmixerinInputDevicewindow.
Decimation:
A decimator reduces the sample rate by discarding samples. It is important to low
passfilterinordertopreventaliasing.
DSP:
Digital Signal Processing. The art of manipulating signals in the discrete digital
domain.
FFT:
Fast Fourier Transform. A mathematical operation that converts between the time
andthefrequencydomains. O(n*logn).
FIR:
Finite Impulse Response filter. Performs convolution in the time domain. A DSP
algorithmic construct made up of cascaded MAC units and filter taps. FIR filters
are stable and have linear phase. Both the decimator in Input Devices and Hilbert
filtersareimplementedwithFIRfilters.
Address: The logical location of program code or data stored in memory.
Addressing mode: The method by which an instruction interprets its operands to
acquire the data it needs.
Address stage: The second stage of the parallel processor‘s fetch, address, execute
(FAE) pipeline during which addresses are calculated and supplied to the crossbar.
(TMS320C8x)
Address unit: Hardware on the parallel processor that computes a bit address
during each cycle. Each parallel processor has two address units: a global address
unit and a local address unit. (TMS320C8x)
Address unit arithmetic: The parallel processor‘s use of the local and global
address units to perform general-purpose arithmetics in parallel with the data unit.
The computed address is not used for memory access, but is stored in the
destination register. (TMS320C8x)
Address visibility (AVIS) bit: A bit field that allows the internal program address
to appear at the external address pins. This enables the internal program address to
be tracpedadanedethpenteerrupt vector to be decoded in conjunction with the interrupt
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acknowledge (IACK) signal when the interrupt vectors reside in on-chip memory.
At reset, AVIS = 0. (TMS320C5x, TMS320C54x, TMS320C2xx)
Administrative privileges: Authority to set software and hardware access; includes
access and privileges to install, manage, and maintain system and application
software and directories on a network server or individual computer systems.
ADTR: Asynchronous data transmit and receive register. See also receive (ADTR)
register.
AFB: See auxiliary register file bus.
Aggregate type: A C data type, such as a structure or an array, in which a variable
is composed of multiple other variables, called members.
AIC: See analog interface circuit.
A-Law companding: See companded.
lias disambiguation: A technique that determines when two pointer expressions
cannot point to the same location, allowing the compiler to freely optimize such
expressions. (TMS320C6200)
Aliasing: 1) A method of customizing debugger commands; aliasing provides a
shorthand method for entering often-used command strings. 2) A method of
accessing a single data object in more than one way, as when a pointer points to a
named object. The optimizer has logic to detect aliasing, but aliasing can cause
problems for the optimizer. 3) Aliasing occurs when a single object can be accessed
in more than one way, such as when two pointers point to a single object. It can
disrupt optimization, because any indirect reference could refer to any other object.
Alignment: A process in which the linker places an output section at an address
that falls on an n-byte boundary, where n is a power of 2. You can specify
alignment with the SECTIONS linker directive.
Allocation: A process in which the linker calculates the final memory addresses of
output sections.
Allocation node: The processor node into which an internode message is allocated.
ALU: See arithmetic logic unit.
ALU function: For the parallel processor, an action performed on the three inputs
to the arithmetic logic unit (ALU), which includes any arithmetic or Boolean
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combination of the three inputs, as well as mixed arithmetic and Boolean functions.
(TMS320C8x)
ALU function modifier: For the parallel processor, a 4-bit code that specifies
modifications to the functions performed by the arithmetic logic unit (ALU) data
path (such as carry-in or multiple arithmetic). These function modifiers are
specified in the opcode or in the D0 register, depending on the application.
(TMS320C8x)
ALU operation: For the parallel processor, an action performed by the arithmetic
logic unit (ALU) data path (that is, the result of the ALU function, the operation
class, and any function modifiers). (TMS320C8x) analog interface circuit (AIC):
Integrated circuit that performs serial analog- to-digital (A/D) and digital-to-analog
(D/A) conversions.
Analog mixing: The mixing together of two analog signals; the multiplexing of two
analog signals into one.
Analog repeater: Analog Repeater is telecommunications equipment used to boost
and clarify analog signals on telephone lines.
Analog-to-digital (A/D): Conversion of continuously variable electrical signals to
discrete or discontinuous electrical signals.
Analog-to-digital (A/D) converter: A converter that changes real-world analog
signals such as light and sound into digital code.
ANSI: American National Standards Institute. An organization that establishes
standards voluntarily followed by industries.
ANSI C: A version of the C programming language that conforms to the C
standards defined by the American National Standards Institute (ANSI).
annul: Any instruction that is annulled does not complete its pipeline stages.
API: See application programming interface.
application programming interface (API): Used for proprietary application
programs to interact with communications software or to conform to protocols from
another vendor‘s product. (TMS320C8x)
Application-Specific ICs (ASICs): Application-Specific ICs (ASICs) are chips
designed by our customers for specific applications by integrating cells from a TI
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standard library of pre-tested code. ASIC design is faster than designing a chip from
scratch, and design changes can be made more easily.
AR0–AR7: Auxiliary Registers 0–7. Eight registers that are used as pointers to an
address within the data space address range. The registers are operated on by the
auxiliary register arithmetic unit (ARAU) and are selected by the auxiliary register
pointer (ARP).
AR: See auxiliary register.
ARAU: See auxiliary register arithmetic unit.
ARB: See auxiliary register pointer buffer.
Architecture: The software or hardware structure of all or part of a computer
system; includes all the detailed components of the system.
Archive library: A collection of individual files grouped into a single file by the
archiver.
Archiver: A software program that collects several individual files into a single file
called an archive library. With the archiver, you can add, delete, extract, or replace
members of the archive library.
ARCR: See auxiliary register compare register.
Argument buffer: A memory block into which argument values are placed that
accompany a command to a server parallel processor.
Arithmetic logic unit (ALU): The section of the computer that carries out all
arithmetic operations (addition, subtraction, multiplication, division, or comparison)
and logic functions.
ARP: See auxiliary register pointer.
ARR: See BSP address receive register.
ARSR: See asynchronous serial port receive shift register.
ASCII: American Standard Code for Information Interchange, 1968. The standard
set of 7-bit coded characters ( 8-bit including parity check) used for information
interchange among data processing systems, communications systems, and
associated equipment. The ASCII set consists of control characters and graphics
characters.
ASPCR: See asynchronous serial port control register.
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