International Journal of Electronics Communication and Computer Engineering

Volume 3, Issue 4, ISSN (Online): 2249–071X, ISSN (Print): 2278–4209

Impact of MOSFET Non Ideal Characteristic

Breakdown on Digital Circuit Operation and Reliability
Prof. Jaikaran Singh Prof. Mukesh Tiwari Ms. Madhu Singh
Department of Electronics and Department of Electronics and Department of Electronics and
Communication Engineering Communication Engineering Communication Engineering
Sri Satya Sai Institute of Science & Sri Satya Sai Institute of Science & Sri Satya Sai Institute of Science &
Technology, Sehore (M.P.), India Technology, Sehore (M.P.), India Technology, Sehore (M.P.), India
Email ID : [email protected] Email ID : [email protected]

Abstract — In semiconductor perspective reliability is the 1. MOS SCALING THEORY

ability of a device to conform to its electrical and
visual/mechanical specifications over a specified period of
time under specified conditions at a specified confidence The basic MOS transistor structure could be scaled to
level. Since the beginning reliability has been remained an smaller physical dimensions. One could postulate a
important part of semiconductor industry. For the last six “scaling factor” of λ, the fractional size reduction from one
decades device reliability have improved with each scaled generation to the next generation, and this scaling factor
generation of technology. Manufacturers of devices with could then be directly applied to the structure and behavior
critical applications like military, automotive and medical of the MOS transistor in a straightforward multiplicative
mainly contributed to initiate and develop semiconductor fashion. For example, a CMOS technology generation
reliability field.
could have a minimum channel length Lmin, along with
The reliability of semiconductor products as a function of
time is commonly described by a bathtub curve .This is technology parameters such as the oxide thickness tox, the
because the plot of the product failure rate as a function of substrate doping NA, the junction depth xj, the power
time has the shape of a cross sectioned bathtub as shown in supply voltage Vdd, the threshold voltage Vth, etc. The
fig. 1. Three failure regimes can be distinguished in the basic “mapping” to the next process, Lmin→ λLmin,
bathtub curve. In the ‘infant mortality’ or ‘early failure’ involved the concurrent mappings of tox→λtox, NA→
period, the products show a high, but decreasing failure rate λNA, xj→ λxj, Vdd→ λVdd, Vth→ λVth, etc. Thus, the
as a function of time until the failure rate stabilizes. This structure of the next generation process could be known
period is referred to as the ‘random failure’ period. Finally, beforehand, and the behavior of circuits in that next
in the ‘wear-out’ period, the failure rate increases again
generation could be predicted in a straightforward fashion
when end-of-life of the products is reached. The nature of the
failures in the three periods is generally very different. The from the behavior in the present generation. The scaling
majority of the failures in the ‘early failure’ period are theory developed by Mead and Dennard is solidly
caused by manufacturing defects like e.g. particles, near grounded in the basic physics and behavior of the MOS
opens and shorts in metal lines, weak spots in isolating transistor. Scaling theory allows a “photocopy reduction”
dielectrics or poorly bonded bond wires in the package. In approach to feature size reduction in CMOS technology,
the ‘random failure’ period many different root causes occur and while the dimensions shrink, scaling theory causes the
but failures related to specific events like lightning, load field strengths in the MOS transistor to remain the same
dump spikes occurring during disconnection of car batteries across different process generations. Thus, the “original”
or other overstress situations are most notable. Failures in
form of scaling theory is constant field scaling. Constant
the ‘wear out’ period are related to intrinsic properties of the
materials and devices used in the product in combination field scaling requires a reduction of the power supply
with the product use conditions like temperature, voltage and voltage with each technology generation. In the 1980s,
currents including their time dependence. CMOS adopted the 5V power supply, which was
The major long-term reliability concerns include the compatible with the power supply of bipolar TTL logic.
wear-out mechanisms of time dependent dielectric Constant field scaling was replaced with constant voltage
breakdown (TDDB) of gate dielectrics, hot carrier injection scaling, and instead of remaining constant, the fields
(HCI), negative bias temperature instability (NBTI), electro inside the device increased from generation to generation
migration (EM), and stress induced voiding (SIV). Among until the early 1990s, when excessive power dissipation
the wear-out mechanisms, TDDB and NBTI seem to be the
and heating, gate dielectrics TDDB and channel hot carrier
major reliability concerns as devices scale. The gate oxide has
been scaled down to only a few atomic layers thick with aging caused serious problems with the increasing electric
significant tunneling leakage. While the gate leakage current field. As a result, constant field scaling was applied to
may be at a negligible level compared with the on-state technology scaling in the 1990s. Constant field scaling
current of a device, it will first have an effect on the overall requires that the threshold voltage be scaled in proportion
standby power. For a total active gate area of 0.1 cm2, chip to the feature size reduction. However, ultimately
standby power limits the maximum tolerable gate leakage threshold voltage scaling is limited by the sub-threshold
current to approximately 1-10 A/cm2, which occurs for gate slope of the MOS transistor, which itself is limited by the
oxides in the range of 15-18A. thermal voltage kT/q, where the Boltzmann constant, k and
the electron charge, q are fundamental constants of nature
Keywords – Logic design, Scaling, reliability, MOS
and cannot be changed. The choice of the threshold
devices.
voltage in a particular technology is determined by the off-
state current goal per transistor and the sub-threshold

Copyright © 2012 IJECCE, All right reserved

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 International Journal of Electronics Communication and Computer Engineering
Volume 3, Issue 4, ISSN (Online): 2249–071X, ISSN (Print): 2278–4209

slope. With off-current requirements remaining the same

(or even tightening) and the sub-threshold slope limited by
basic physics, the difficulty with scaling the threshold
voltage is clear. Because of this, the power supply voltage
decreased corresponding with the constant field scaling,
but the threshold voltage was unable to scale as
aggressively. This situation worsens as feature sizes and
power supply voltages continue to scale. This is a
fundamental problem with further CMOS technology
Fig.1. HCI and NBTI
scaling.
Thus design of high density chips in MOS VLSI
technology requires that the packing density of MOSFETs 2.3 Electro Migration
use in circuits is as high as possible and, consequently, Electro migration is the phenomena of interconnect
that the transistor are as small as possible. The reduction metal self-diffusion along an interconnection as high
of the size i.e dimensions of MOSFETs can change the current density is passing through the interconnection. As
MOSFET characteristic in this paper we will examine in a result of the metal movement, voids will be formed on
detail the non ideal effects on MOS characteristic. These some parts of the interconnection, and hillock due to the
are mainly due to the limitation impose on electrons drift accumulation of the metal atoms will be formed on
characteristic in the channel and the modification of the different parts of the interconnection[6]. The presence of
threshold voltage due to the shortening channel length. voids will increase the resistance of the interconnection,
and the presence of hillock will cause short circuit
2. NON IDEALITIES between the adjacent interconnections if the hillock is
developed side-way and short circuit between the different
levels of interconnections if the hillock is developed
2.1 Channel length modulation: vertically and punch through the inter-metal dielectric.
Biasing the gate by coupling the gate voltage to the Electromigration has been a subject of scientific study for
input reduces Vt by aiding the onset of snapback through over 100 years, but the interest remained academic until it
increased drain current. Fig 2 shows the I-V characteristic became a major failure mechanism for integrated circuits
for the transistor for different variable gate voltages. The (IC) in 1959 as thin and narrow metal films are used for
current is zero for gate voltage below Vt. For higher gate interconnections. Indeed, electro migration was the one of
voltage, current increases linearly with Vds. As Vds the first few failure mechanisms found in IC. Unlike the
reaches at the saturation point Vgs- vt, current roll off and bulk conductor which will melt from Joule heating at 104
eventually become independent of Vds When the A/cm2, the metallization in IC can sustain current densities
transistor is saturated, the MOSFET is a perfect current greater than 107 A/cm2 due to the good thermal contact
source and junction between drain and body forms with the silicon substrate. It is this high current density
depletion width which reduces channel length. Shorter that makes the effect of electro migration becomes
channel length results in higher current[3],[4],[7]. significant.
2.2 HCI and NBTI 2.4 Drain-Induced Barrier Lowering (DIBL)
With the geometric scale down, HCI and NBTI In the weak inversion regime, there is a potential barrier
problems become worse. In the channel of the MOS, a between the source and the channel region. The height of
high electrical field is created close to the drain. The gatethis barrier is a result of the balance between drift and
oxide thickness is also reduced to allow low threshold diffusion current between these two regions. The barrier
voltages. When the channel is conducting, the high height for channel carriers should ideally be controlled by
electrical field close to the drain generates an injection ofthe gate voltage to maximize transconductance. The DIBL
hot carriers into the (SiO2) gate oxide layer[2],[6]. This effect occurs when the barrier height for channel carriers
inserts charges in the oxide by trapping carriers (electrons at the edge of the source reduces due to the influence of
and holes). These carriers can cause permanent changes in drain electric field, upon application of a high drain
the oxide-interface charge distribution. This can also voltage. This increases the number of carriers injected into
degrade the device’s drain current capability. The the channel from the source leading to an increased drain
accumulation of trapped charge will lower saturation off-current. Thus, the drain current is controlled not only
current Idsat, cause Vt drift, lower the linear region by the gate voltage, but also by the drain voltage. For
transconductance, and degrade the subthreshold slope. As device modeling purposes, this parasitic effect can be
the geometry scales down, these problems become worse. accounted for by a threshold voltage reduction depending
Some IC manufacturers have already reported HCI on the drain voltage. In addition to the surface DIBL, there
problems for 0.5 um processes. are two unique features determining SCEs in thin-film SOI
devices: 1) positive bias effect to the body due to the
accumulation of holes generated by impact ionization near
the drain and 2) the DIBL effect on the barrier height for
holes at the edge of the source near the bottom of thin
film. Holes generated near the drain due to impact
ionization accumulate in the body region, and then
Copyright © 2012 IJECCE, All right reserved
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 International Journal of Electronics Communication and Computer Engineering
Volume 3, Issue 4, ISSN (Online): 2249–071X, ISSN (Print): 2278–4209

positively bias the body, reducing threshold voltage . This degrade. Here, the gate width is 10 m, and the body
positive bias effect leads to lowering for all gate lengths. potential is fixed from the both side of the gate electrode
The hole generation rate due to impact ionization increases Due to the reversly biased parasitic pn junction, the
as gate length decreases. This effect is predominant in threshold voltage increases by reducing channel width
nMOSFETs and results in so-called floating body effects. which affects channel current, it is called as Body effect.
The DIBL effect on the barrier height for holes reduces the 2.7 Time Dependent Dielectric Breakdown (TDDB)
positive bias effect to the body because the accumulated TDDB is wear-out of the insulating properties of silicon
holes in the body can more easily surmount the barrier and dioxide in the CMOS gate leading to the formation of a
flow to the source. As a result, fewer number of conducting path through the oxide to the substrate. With a
accumulated holes remains, which weakens the lowering. conducting path between the gate and the substrate, it is no
The potential near the bottom in the body region increases longer possible to control current flow between the drain
as gate length decreases due to the drain electric field. This and source by means of the gate electric field. TDDB
leads to the lowering of the barrier height for holes at the lifetime is strongly affected by the number of defects in
source edge near the bottom with shorter gate lengths. the gate oxide produced during wafer fabrication.
With shorter gate lengths, the barrier height for holes near Therefore, foundries strive to produce an ultra-clean oxide
the bottom is lowered by the influence of the drain electric in their process to maximize the TDDB lifetime. Even if a
field, and holes accumulated in the body region can more foundry could produce a perfectly defect free oxide,
easily flow into the source. Due to these three TDDB would remain a concern for ASIC designers.
mechanisms, dependence upon gate length in fully TDDB occurs at all gate voltage bias conditions. The goal
depleted (FD) nMOSFETs becomes small. of the foundry is to trade off gate oxide thickness with
2.5 Substrate Bias Effect in Body-Tied MOSFET’s operating voltage specifications to achieve both speed and
It shows that the threshold voltage of the characteristics lifetime targets for the technology. The lifetime of a
does not change very much as the body is reverse-biased, particular gate oxide thickness is determined by the total
while it becomes lower as the body is forward-biased. The amount of charge that flows through the gate oxide by
threshold voltage becomes higher as the body is reverse- tunneling current[5].
biased and stops rising when the body bias exceeds a It is clear that operating a CMOS device at voltages
certain value, while the threshold voltage becomes lower greater than foundry specification results in an exponential
as the body is forward-biased. It also shows the increase in the amount of oxide current. Once electrons
dependence on the channel impurity concentration, drain have breached the oxide potential barrier they are
voltage, and gate length. It is clear that a higher impurity accelerated through the oxide by the electric field which is
concentration requires a higher body-bias to reach a determined by the applied voltage and the oxide thickness.
constant threshold voltage[1]. The higher drain bias and a Charge accelerated in the gate oxide achieves greatest
shorter gate length decrease the body bias for the threshold energy at the oxide-silicon interface presuming there have
voltage saturation. We think that this is because it is easy been no collisions in transit. At the end of its travel
for the body region near the drain edge to become fully through the oxide, it deposits its energy at the oxide silicon
depleted by the drain bias and this affects all the interface. The oxide-silicon interface has some special
characteristics of the short-channel device. In addition, properties produced by the fact that there is a large thermal
when the threshold voltage becomes constant with a coefficient of expansion (TCE) difference between silicon
reverse body-bias, the - factor simultaneously becomes dioxide and silicon .This large difference in TCE leads to
small and constant. This also indicates that the device strained chemical bonds that can be broken by the
becomes fully depleted due to the reverse body-bias. Here, accelerated charge. Once the chemical bonds have been
although the -factor does not reach the ideal value 60 broken, the sites become locations where charge can
mV/dec, the discrepancy is considered to be mainly due to become trapped. This trapped charge will have an
the influence of the capacitance between channel and influence upon the channel carrier mobility in transistors
source/drain through the buried oxide . and reduce their gain. This trapped charge also has the
2.6 Source–Drain Breakdown Characteristics at effect of increasing the electric field locally and therefore
Reverse Body-Bias Condition increasing the local tunneling current. The process has
Fig. 5 plots the source–drain breakdown voltage versus positive feedback that leads to rapid charge build-up until
the gate length. This shows that for body-tied cases the tunneling current is large enough to literally burn a
including reverse-bias, the breakdown voltage is very high hole through the gate oxide. Modeling TDDB lifetime has
down to the gate length of 0.3 m, while for a floating been a challenging task. The specific physical process
structure, the breakdown voltage gradually becomes lower details leading to failure are somewhat complex, and as a
as the gate length becomes shorter. This breakdown result, simple models tend to be inaccurate if the gate
voltage degradation is due to the source–drain punch- oxide is substantially different from the thickness used for
through assisted by parasitic bipolar action [1]. Therefore, collecting the data used to develop the model. A great deal
it is suggested that the all body tied configurations well of material has been published about TDDB modeling
suppress the parasitic bipolar action. with various relationships of electric field to lifetime.
Fig. 2 shows the drain current—drain voltage Debate has raged for some time over whether the lifetime
characteristics. The gate voltage was set to be 1.2 V, is related to E (electric field), or 1/E, or just applied gate
where the on-regime breakdown voltage was expected to Voltage. Currently it appears that simple models will only

Copyright © 2012 IJECCE, All right reserved

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 International Journal of Electronics Communication and Computer Engineering
Volume 3, Issue 4, ISSN (Online): 2249–071X, ISSN (Print): 2278–4209

be valid over certain ranges of gate oxide thickness.

Moderately thick oxides seem to have a lifetime related to
1/E (at high electric field) or E (at low electric field) while
for very thin oxides (thinner than 5nm) the lifetime
appears to be related to applied Voltage. All of the
following models are based upon data fitting from
experimental data under different amounts of electric field
stress with different oxide thickness. Tests are performed
at very high electric field (greater than under normal use
conditions) and at elevated temperature to reduce testing Fig.5 MOSFET Ids-Vgs Characteristic at tox=1.1um,
time to a few weeks instead of tens of years. These models vt=0.4v, Vds=Vgs=0.0 to 1.2,
include the temperature dependence.

RESULTS

Fig.2. MOSFET Characteristic at tox=2um, vt=0.4v,

Vds=Vgs=0.0 to 1.2, at different gate voltages. Fig.6. CMOS Layout of decoder logic with glitch at output

Fig.3. MOSFET Characteristic of oxide breakdown at

tox=1.1um, vt=0.4v, Vds=Vgs=0.0 to 1.2

Fig.7. CMOS Layout of decoder logic output wave with

glitch at output

Fig.4. MOSFET Ids-Vgs Characteristic at tox=2um,

vt=0.4v, Vds=Vgs=0.0 to 1.2

Fig.8. CMOS Layout of decoder logic current output wave

with glitch at output

The decrease in device dimensions increases substrate

doping densities results in significant increase in
horizontal and vertical electrical field in the channel
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 International Journal of Electronics Communication and Computer Engineering
Volume 3, Issue 4, ISSN (Online): 2249–071X, ISSN (Print): 2278–4209

region. Electrons and hole gaining high kinetic energies in region. This effect is due to the formation of a localized
the electric field may, however, get injected in to the gate oxide damaged region likely trapping negative charge over
oxide, and cause permanent changes in the oxide interface a large portion of the channel width, around the SB
charge distribution, degrading the current voltage conductive path, as the damaged oxide region becomes
characteristic of the MOSFET (see fig 7 and fig 8 CMOS wider due to thermal dissipation and defect generation.
Layout of decoder logic output wave with glitch at
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diffusion of holes to the source which triggers snapback
becomes less efficient and more impact ionization must be AUTHOR’S PROFILE
provided by increased current and electric field.(see Fig 3
and fig 4) . Prof. Jaikaran Singh
Generally, oxide reliability is assessed by accelerated is working as an Assistant Professor & HOD in Electronics and
life tests performed in large area capacitors and most of Communication Department at SSSIST, Sehore, India. He is pursuing
the reports in literature starts by the assumption that device PhD Degree from RGPV Bhopal in Optoelectronics. M.Tech. Degree
from RGPV Bhopal in Microelectronics and VLSI design .His areas of
failure occurs when the gate current exceeds a maximum
interest are VLSI, DSP, Nanoelectronics, Embedded System Design,
tolerable value, but a point is missed: the role of Optoelectronics, Matlab .He has 8.5 years experience in Teaching and
breakdown on the MOSFET drain current. Nevertheless, Research. He has published more than 30 research papers in journals and
when considering long-term device reliability. conferences and he has reviewed more than 15 research papers for
different journals including IEEE Sensor journal. He has also guided 25
postgraduate students.
CONCLUSION
Prof. Mukesh Tiwari
In this paper, we show that the non ideal effects on the is working as an Associated Professor & Dean Academic in Electronics
and Communication Department at SSSIST, Sehore, India. He was
MOSFET characteristics strongly depend on the transistor awarded his ME Degree from RGPV Bhopal in Digital Communication.
aspect ratio and in particular on the transistor channel His areas of interest are Communication. He has 9 years experience in
width, so that even digital applications may be strongly Teaching and Research. He has published more than 35 research papers
disturbed by these effects. In fact, the transconductance in journals and conferences. He has also guided 10 postgraduate research
scholars.
and drain saturation current of MOSFETs with 2-nm and
2.5-nm gate oxides may dramatically drop in transistors Ms. Madhu Singh
with very narrow channels after these effects, i.e., is pursuing M.Tech. From RGPV Bhopal in VLSI design from SSSIST,
MOSFETs largely used for digital circuits. It affects the Sehore. Her area of interest is VLSI,DSP & microprocessor
transistor electrical characteristics to a degree depending
on the degradation level and area of the gate oxide broken
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