Fall Semester 2024-2025

Digital IC Design
Digital Assessment Report

(Digital Assessment No.2)

Course Code: MVLD502L
Slot: F1+TF1

Submitted by: Aswin P

Reg. No: 24MVD0080
Submitted to: Dr. Sakthivel R
 1. Perform the VTC analysis of a three-input NAND and NOR gate and
sketch its data dependence. Size the NMOS and PMOS devices for
unit inverter delay in 45nm Technology.

Unit Inverter Sizing:

To achieve a unit delay, sized the inverter made of one pmos and one nmos is sized
based on the VTC characteristics analysis.

Procedure:
:

The schematics of inverter is created in Cadence Virtuoso simulation environment using

the GPDK90nm technology.

Figure 1: Inverter Layout

By performing VTC Parametric analysis with varying width W of PMOS, the ratio of width of
PMOS and NMOS is calculated. The VTC graph.

Figure 2: Parametric VTC. Highlighted line Corresponds to PMOS width of 1.22u

From this ratio of PMOS width VS NMOS width is calculated to be 1.22.

So, for 120n of NMOS width I took 145n of PMOS width. Using this with NAND and NOR
Circuits are created.

Figure 3: NAND Schematics

 Figure 4: NOR Schematics

Keeping A,B,C as a DC Variable voltage, VTC of NAND and NOR are Plotted.

VTC of 3 input NAND Gate:

VTC of NAND is plotted by Firstly keeping all the input as 1 in ADEL and then varying
either one of the inputs from 0 to 1 at a time, each time the result is appended with the
previous one hence getting the following VTC, where,

 Red line is the VTC when Voltage A is Varying.

 Pink Line is when B Varies.
 Yellow line when C varies
 Figure 5: VTC of NAND Gate

Figure 6: VTC of NAND Gate Enlarged

From the simulation result, it’s clearly observable that, the behavior of the output is slightly
affected by the choice of the input.

When Varying A, the pullup circuit is performing better, while using input C, pull down circuit is
performing better, in comparison, input B provides an optimal DC response.

But based on the graph, these effects and variations are very small for NAND Gate.
VTC of 3 input NOR Gate:

VTC of NOR is plotted by Firstly keeping all the input as 0 in ADEL and then varying
either one of the inputs from 1 to 0 at a time, each time the result is appended with the
previous one hence getting the following VTC, where,

 Red line is the VTC when Voltage C is Varying.

 Blue Line is when A Varies.
 Yellow line when B varies.

Figure 7: VTC of NOR Gate

 Figure 8: VTC of NOP Gate Enlarged

From the simulation result, it is observable that, the behavior of the output is slightly affected by
the choice of the input.

When Varying A, the pulldown circuit is performing better, while using input C, pull up circuit is
performing better, in comparison, input B provides an optimal DC response.

Based on the graph, these effects and variations are very small for NOR Gate also.
 2. Analyze the pull-up and pull-down delay for the same three-input
NAND and NOR gate for different data dependencies of 000 to 111.

To analyze the rise and fall time of NAND and NOR Gates for the full range of inputs, The pulse
values of inputs A,B,C are changed along with the period and pulse width of the inputs, the
values are summarized in the following table along with the observation of rise time and fall time
for both NAND and NOR gates.

A B C NOR NAND
Rise Fall Rise Fall
Pulse Pulse Pulse Time Time Time Time
V1 V2 Period V1 V2 Period V1 V2 Period
Width Width Width (Peco (Peco (Peco (Peco
Second) Second) Second) Second)
1 0 40n 40n 1 0 40n 40n 1 0 40n 40n 56.42 NA 50.16 NA
1 0 40n 20n 1 0 40n 40n 1 0 40n 40n 22.536 9.28 3.34 NA
1 0 40n 20n 1 0 40n 20n 1 0 40n 40n 22.536 4.12 3.34 NA
1 0 40n 20n 1 0 40n 20n 1 0 40n 20n 22.536 NA 3.34 21.8
0 1 40n 20n 1 0 40n 20n 1 0 40n 20n NA NA NA NA
0 1 40n 20n 0 1 40n 20n 1 0 40n 20n NA NA NA NA
0 1 40n 20n 0 1 40n 20n 0 1 40n 20n 9.28 2.36 3.34 21.7
0 1 40n 40n 0 1 40n 20n 0 1 40n 20n NA 2.36 5.3 21.7
0 1 40n 40n 0 1 40n 40n 0 1 40n 20n NA 2.36 11.64 21.7
0 1 40n 40n 0 1 40n 40n 0 1 40n 40n NA 2.36 NA 15.6
0 1 40n 10n 0 1 40n 20n 0 1 40n 40n NA 2.36 9.7 21.7

Following are some of the screen shots of the simulation results.

 111

ADEL Window 111

101

ADEL Window 101

ADEL Window 111 → 000

 100

ADEL Window 011

000 → 111
3. Implement a Boolean function y=(AB+C)’ in domino logic and
study the impact of the following through simulation.

a) Sketch the Schematic and transient response.

Figure 9: Schematic for Y=(AB+C)′ utilizing domino logic

The above schematic is realized using the inputs A′,B′, and C′ in the domino circuit,
resulting in the equation Y=(((A′+B′)C′)′)′=(AB+C)′.

Figure 10: Transient response of the logic function

 b) Effect of an input glitch on the output.

Figure 11: Effect of input glitch, Output parametric graph.

The influence of an input glitch on the output is contingent on the evaluation time. A
larger glitch can be managed if the evaluation time is minimized. In this instance, the
input glitches to a high state during evaluation and remains elevated throughout the
period. The graph illustrates an input glitch occurring when B and C experience a delay
of 0.4 ns, along with multiple values of reduced switching threshold, for that a
parametric analysis has done varying the switch threshold values from 250mV to 1V.

c) Impact of charge leakage.

Ideally, if the pull-down network is inactive, the output should stay at the precharged
level of VDD during evaluation. However, this charge can gradually dissipate due to
leakage currents, leading to potential gate failure. The graph shows that when
A=B=C=1(indicating the circuit is OFF) during evaluation, the output declines from 1V to
values between 950mV and 650mV based on the duration of the evaluation stage, ie,
clock pulse width. The longer the clock duration the larger the leakage.

d) Charge sharing effect in dynamic logic.

Transient Analysis of Charge Sharing effect

During the pre-charge phase, the output node is charged to VDD. If all inputs are set to
0 during this phase and A and C remain at 1 while B transitions from 1 to 0, the output
voltage drops due to the shared capacitance between B and C. The node voltage
“Node” (situated between B and C) increases.
The graph shows this behaviour with OUT representing the output voltage of the
dynamic logic and Node indicating the voltage at the shared capacitance node.
Phenomenon can be observed between 10n to 15n , 50n to 55n and 90n to 95ns oxf the
time in the x axis.
 e) Clock feedthrough effect.

This effect arises from capacitive coupling between the clock input of the pre-charge
device and the dynamic output node. The coupling capacitance, which includes both
overlap and channel capacitances from the gate-to-drain of the pre-charge device,
results in the dynamic output node exceeding VDD during the low-to-high clock
transition, provided that the pull-down network is off. The graph illustrates that during
pre-charge, the output reaches VDD and during evaluation, it surpasses VDD (from 1V
to 1.0212V).
References:

1. J. M. Rabaey, A. P. Chandrakasan, and B. Nikolić, Digital

Integrated Circuits: A Design Perspective, 2nd ed. Upper
Saddle River, NJ: Pearson Education, 2003.
2. N. H. E. Weste and D. M. Harris, CMOS VLSI Design: A Circuits
and Systems Perspective, 4th ed. Upper Saddle River, NJ:
Pearson, 2011. ISBNs: 9780133001471, 0133001474,
9780321547743, 0321547748.
3. Cadence Design Systems, Inc., “Cadence Tools,” [Online].
Available: https://www.cadence.com [10.110.5.59]. [Accessed:
Oct. 24, 2024].