Test Generation

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 Test Generation
• Introduction
• Random Test Generation
• Theoretical Foundations
• Deterministic Combinational ATPG
• Deterministic Sequential ATPG
• Untestable Fault Identification
• Simulation-based ATPG
• ATPG for Delay and Bridge Faults

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 Introduction
• Test generation is the bread-and-butter in VLSI
Testing
▪ Efficient and powerful ATPG can alleviate high costs of DFT
▪ Goal: generation of a small set of effective vectors at a low
computational cost
• ATPG is a very challenging task
▪ Exponential complexity
▪ Circuit sizes continue to increase (Moore’s Law)
– Aggravate the complexity problem further
▪ Higher clock frequencies
– Need to test for both structural and delay defects

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 Conceptual View of ATPG
• Generate an input vector that can distinguish the
defect-free circuit from the hypothetically defective one

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 Simple illustration of ATPG
• Consider the fault d/1 in the defective circuit
• Need to distinguish the output of the defective circuit
from the defect-free circuit
• Need: set d=0 in the defect-free circuit
• Need: propagate effect of fault to output
• Vector: abc=001 (output = 0/1)

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 Stuck-at fault test generation
s-a-0
PI justify y
propagate PO

• To generate a test for y stuck-at 0, we need to find

an vector of primary inputs which sets signal y to 1
(justify) and such that some primary output differs
between the good circuit and the faulty circuit
(propagate)

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 Basic Problem
• Inputs
○ Acircuit netlist
○ A fault list F
• Outputs
○ A set of test vectors T to detect the faults in F
○ A list of undetected faults

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 Motivation
• Drastically reduce the number of required test vectors
as compared to naive approach
• Some example
○ 4 input AND gate
■ Need 5 vectors as compared to 16
● {0111,1011,1101,1110,1111}
○ 5 input XOR gate
■ Need 2 vectors as compared to 32
● {00000,11111}

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 A Typical ATPG System
• Given a circuit and a fault model
▪ Repeat
■ Generate a test for each undetected fault
■ Drop all other faults detected by the test using a fault
simulator
■ Until all faults have been considered

• Note 1: a fault may be untestable, in which no test

would be generated

• Note 2: an ATPG may abort on a fault if the

resources needed exceed a preset limit

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 How to arrive at a test set?

● A test set is to be developed that can detect any

possible fault in the given circuit.
● There are two approaches:
1) Random Test Generation (RTG)
2) Fault-targeted Test Generation (FTG)

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Generating test vector from Truth Table
● How to generate test for s-a-0 fault ?

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 Random Test Generation
• Take a random vector as test vector.
• Calculate the performance of the circuit with & without
faults.
• Identify all the faults that can affect the output for this
test vector.
• Remove the covered faults from the fault list.
• If there are some more faults in the fault list, take
another random vector and repeat the process until the
fault list becomes empty.

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 Random Test Generation
• Simplest form of test generation
▪ N tests are randomly generated

• Level of confidence on random test set T

▪ The probability that T can detect all stuck-at faults in the
given circuit
▪ Quality of a random test set highly depends on the underlying
circuit
▪ Some circuits have many random-resistant faults

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Flow diagram of RTG

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 Fault-targeted Test Generation(FTG)
• Here we start with a vector which can detect a specified fault.

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 RTG & FTG
• The fault targeted simulation is a slow process
initially compared to RTG.

• If the number of faults is high, then a random test vector

can detect more faults. If we use FTG then we need to
generate a test for each single fault.

• If the number of faults still left to be tested is less, then

FTG is used.

• Hence one adopts RTG in the initial stage when the

number of faults to be tested are very high and when the
number gets reduced, FTG is used.
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 Theoretical Foundations: Boolean
Difference
• Let the target fault be y/0, then the function for the faulty circuit is f’ = f(y=0)

• Goal of test generation: find a vector that makes f XOR f’ = 1

• The function for the circuit is

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 Boolean Difference Example
• To excite the fault y/0, set y=1
• Thus, synonymous to propagating
the fault effect at node y to
the primary output f

xyz= 110 or 011 can

detect the fault

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 Boolean Difference Equation
• The Boolean difference of f with respect to y is written
as

• For a Target fault at w (s-a-0) the set of test vectors that

can detect w/0 is defined as:

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 Another Example

• Let target fault be w/0

xyz=001, 101
can detect w/0

But:

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 A Third Example

• Fault: z/0

This fault is untestable!

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 Deterministic ATPG
• In general, we don’t need an entire set of vectors that can detect
the target fault

• Instead, we just want to compute one vector quickly

• Rather than using Boolean Difference that can obtain all vectors
▪ Simply use a branch-and-bound search to find one vector quickly

• Deterministic ATPG has two main goals

▪ Excite the target fault
▪ Propagate the corresponding fault effect to an output

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 Exhaustive Algorithm
n
• For n-input circuit, generate all 2 input patterns
• Infeasible, unless circuit is partitioned into cones of
logic, with 15 inputs
≤
– Perform exhaustive ATPG for each cone
– Misses faults that require specific activation patterns for multiple
cones to be tested

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 Algorithm Completeness
• Definition: Algorithm is complete if it ultimately can
search entire binary (decision) space, as needed, to
generate a test

• Untestable fault or Undetectable fault – no test for it even

after entire space is searched

• Combinational circuits only – untestable faults are

redundant, showing the presence of unnecessary
hardware

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 5-valued Algebra for Comb. Circuits
• Instead of using two circuits (fault-free and the
faulty)
▪ We will solve the ATPG problem on one single circuit

• To do so, every signal value must be able to capture

fault-free and faulty values simultaneously

• 5-Value Algebra: 0, 1, X, D, D-bar

• D: 1/0
• D-bar: 0/1

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Boolean Operators on 5-Valued Algebra
● Five valued logic (0,1,D,D’,X)
○ D = 1/0, 1 in fault free circuit and 0 in faulty circuit
○ D’ = 0/1, 0 in fault free circuit and 1 in faulty circuit
○ X means ‘Not yet specified’ in ATPG

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 Terms used
• Singular Cover

• D Drive

• D Frontier

• J Frontier

• Consistency

• Backtracking

• Implications

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 D-Frontier

• D-Frontier: All gates whose outputs are X but has at

least one D or D-bar at the input of the gates

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 J-Frontier
• J-Frontier: All gates whose outputs are specified by
are not justified by the input assignments

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 Idea Behind D Algorithm
● Create D frontier (fault activation)
● Drive D-frontier towards output (fault effect propagation)
● Justify J-frontier
● Backtrack if any conflict occurs

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 Primitive D-Cubes for a Fault (PDCF)
•

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 Singular Cover (SC)
● Minimum gate assignments for gate output = 0 or
=1

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 Propagation D-Cube (PDC)
● Minimum gate assignments required to propagate
a D or D’ from gate input to gate output

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 D-Drive
● D-Drive selects an element in D-frontier
○ an attempts to propagate D or D’ from gate input to
gate output
○ using propagation D-Cube

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 Implications
● Forward Implications
○ partially (or fully) specified input values uniquely determines
the output values
● Backward Implications
○ Knowing the output values (and some input values) can
uniquely determine the unspecified input values
● Examples

Note: Implication means NO choice

Implication is done anytime a decision is made
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 Justification
• Definition: find a valid primary input assignment for desired
values
• Justification is easy inside a fanout-free circuit.
• No decision needed
○ always find answer if it exists
• Example

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 Justification
• Justification may fail when there are fanout branches

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 D Algorithm
• Can handle arbitrary combinational circuits, with
internal fanout structures

• Main idea: always maintain a non-empty D-frontier and

try to propagate at least a fault effect to a primary
output

• Initially, all circuit nodes are X, except for the fault cite,
where a fault effect (D or D-bar) is placed.

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 D-Algorithm Steps
• Use D-algebra
• Activate fault
• Place a D or D’ at fault site
• Justify all signals
• Repeatedly propagate D-chain toward POs through a gate
• Justify all signals
• Backtrack if
• A conflict occurs, or
• All D-chains die
• Stop when
• D or D’ at a PO, i.e., test found, or
• Search exhausted, no test possible

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 Step 1 - Fault A sa0
• Step 1 – Fault activation – Set A = 1

D
1 D

D-frontier = {e, h}

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 Step 2 – D Drive
• Step 2 – D Drive – Set f = 0

D 0
1 D
D

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 Step 3 – D Drive
• Step 3 – D Drive – Set k = 1

D
D 0
1 D
D

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 Step 4 – Consistency
• Step 4 – Consistency – Set g = 1

1 1

D
D 0
1 D
D

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 Step 5 – Consistency
• Step 5 – Consistency – f = 0 already set

1 1

D
D 0
1 D
D

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 Step 6 – Consistency
• Step 6 – Consistency – set c = 0, e = 0

1 1
0
D
0 0
D
1 D
D

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 Step 7 – Test Found
• Step 7 – Consistency – Set B = 0
• Test: A = 1, B = 0, C = 0, D = X

1 1
0
0 D
0 0
D
1 D
D

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D Algorithm

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 D Algorithm drawback
• Decision making process involves entire circuit
• Every gate could be a decision point

• In the end an ATPG algorithm has to provide a vector

for PI’s and PO’s

• D Algorithm can be an overkill for decision making at

the gate level and unproductive (J-Frontier is
unnecessary??)

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 PODEM (Path-Oriented Decision Making)
• Also a branch-and-bound search

• Decisions only on PIs - Less decision points as

compared to D Algo
▪ No J-Frontier needed
▪ No internal conflicts

• D-frontier may still become empty

▪ Backtrack whenever D-frontier becomes empty
▪ Backtrack also when no X-path exists from any D/D-bar to a PO

• Decisions selected based on a backtrace from the

current objective
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 PODEM (Path-Oriented Decision Making)
• Idea
○ Only allow assignments to Pi
■ Doesn’t assign internal nodes
■ Greatly reduces search tree
○ Assigned Pi then forward implications
■ no Justification needed
○ Flip the Pi when
■ Fault not activated
■ no propagation path to Po

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 X-Path used by PODEM

• The D in the circuit has no path of X’s to any PO

▪ i.e., the D is blocked by every path to any PO

• PODEM checks if there is an

X-path from fault to PO

• X-path means D can be

propagated otherwise D-Frontier
is blocked

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 PODEM Example

Target fault: f/0

• 1st Objective: f=1 in order to excite the target fault Backtrace

from the object: c=0
• Simulate(c=0): D-Frontier = {g}, some gates have been
assigned {c=d=e=h=0, f=D}
• 2nd Objective: advance D-frontier, a=1
• Backtrace from the object: a=1
• Simulate(a=0): Fault detected at z
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PODEM Example

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 Another PODEM Example

Target fault: b/0

• 1st Objective: excite fault: b=1

• Backtrace from objective: a=0
• Simulate(a=0): b=D, c=0, d=0: empty D-frontier.
• Must backtrack
• Change decision to a=1
• Simulate(a=1): b=0, c=1, d=1, D-frontier still empty
• Backtrack, no more decisions. Fault untestable.

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 FAN (Fanout Oriented)
• PODEM reduced the number of decision points
significantly but it is still high

• PODEM targets only one objective at a time, too

localized and might miss big picture

• FAN Extends PODEM for an improved ATPG

• Concept of headlines to reduce the number
decisions

• Multiple Objectives to reduce later conflicts

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