Namal University Mianwali

Department of Electrical Engineering

COURSE OUTLINE – Spring 2025

1. COURSE DETAILS
Title: Digital Logic Design
Code: EEN-216
Credit(s): 4 Credit Hours (3 Hrs Theory and 1 Hrs Lab/Project Work)
Pre-requisite(s): None
Co-requisite(s): None

2. INSTRUCTOR DETAILS
Name: Dr. Tassadaq Hussain
Lecture Timings: TBD
Office Location: Faculty Offices and CAID, Namal University Mianwali
Office Telephone: +92-
Office Hours: Students can visit during working hours
E-mail: [email protected]

3. COURSE RELEVANT DETAILS

Course Description:
This introductory course will cover the basic principles and concepts involved in analyzing
and designing digital systems using different hardware technologies. The students will be
introduced to number systems, Boolean algebra, logic gates, minimization techniques, and
simulation and testing, logic synthesis. Design and analysis of combination al and sequential
circuits will be performed on custom ICs and programmable arrays.
Course Learning Outcomes (CLOs)
On successful completion of this course, the student will be able to:
Course
Learning CLO Statement Taxonomy Level
Outcome
 CLO-1 Explain fundamental concepts of number systems, logic gates, C2 (Cognitive)
and Boolean algebra used in the development of digital circuits.

CLO-2 Analyze combinational and sequential logic using gate-level and C4 (Cognitive)
register-transfer level (RTL) modeling through test cases.
CLO-3 Design and implement combinational and sequential digital logic C6 (Cognitive)
circuits for open hardware and programmable gate array
technologies.
Program Learning Outcomes (PLO’s):
PLO-1
Engineering Knowledge: An ability to gain and apply knowledge of mathematics, science,
engineering fundamentals and engineering specialization to solve complex engineering
problems.
PLO-2
Problem Analysis: An ability to identify, formulate, research literature, and analyze complex
engineering problems reaching substantiated conclusions using first principles of mathematics,
natural sciences, and engineering sciences.
PLO-3
Design/Development of Solutions: An ability to design solutions for complex engineering
problems and design systems, components, or processes that meet specified needs with
appropriate consideration for public health and safety, cultural, societal, and environmental
considerations.
MAPPING OF CLOs TO PROGRAM LEARNING OUTCOMES

CLOs/PLOs CLO:1 CLO:2 CLO:3

PLO:1 (Engineering Knowledge) 
PLO:2 (Problem Analysis) 
PLO:3 (Design/Development of Solutions) 

Week# Topics Covered in Class Reference in Book/ Course

Course Material Assessments
Assignment/Test/
Project/Lab
Report/Quiz
Week 1 Introduction to Digital Logics, importance and Digital Design (Ch. 1)
Applications
Fundamental Concepts and semiconductor
technologies, ASIC and FPGA
Week 2 Introduction Number system Digital Design (Ch. 1)
Binary numbers, Number Base Conversion,
Octal, and Hexadecimal Numbers
Arithmetic with Number Systems, Signed and
Unsigned Number Systems, and their
arithmetic, Binary Codes, Floating Number
Week 3 Boolean Algebra & Logic Gates Digital Design (Ch. 2) Quiz 1
Postulates and Theorems of Boolean Algebra,
Boolean Functions, Canonical and Standard
Forms, Digital Logic Gates,
Week 4 Introduction to Switch Level Design using
LogiSim, Verilog and Simulation using GTK
Wave.
Implementation, Universal Gate in Simulators
Week 5 Building and Analyzing Logic Gates using Gate Digital Design (Ch. 3) Assignment 1
Level Design Approach.
Modeling and Simulation Universal gate using
Opensource simulators
Week 6
Boolean Function Minimization
Karnaugh Maps
Simplifying Boolean expressions using K-
Maps
Reducing circuit complexity
Quine–McCluskey Method
Practical approach to minimizing Boolean
functions

Week 7 Combinational Logic Digital Design (Ch. 4) Quiz 2

Analysis and Design of Combinational Circuits,
Adders & its types, Subtractors, Multiplier,
Magnitude Comparator Decoders, and Encoders,
Multiplexers.
Week 8 Verilog description of Combinational Logic
Circuits
Binary Adder and Subtractor Circuits
Full and half adders, subtractors
Multiplexers, Dividers, and Shift Registers
Use in arithmetic operations

Week 9 - Mid Term Exam

Week 10 Sequential Logic Digital Design (Ch. 5) Quiz 3
Introduction to Sequential Circuits, Latches (SR
Latch, D Latch), Flip Flops (D Flip Flop, JK
Flip Flop, T Flip Flop), Verilog
descriptions of latches and flip-flops
Week 11 Sequential Logic Digital Design (Ch. 5) Assignment 2
Analysis of Sequential Systems, State Equation,
State Table, State Diagram.
FSM, Moore Machine, Mealy Machine.
Week 12 Registers and Memories Digital Design (Ch. 5)
Simple registers, Registers with Parallel Load,
Shift Registers/Serial to parallel Converters,
Universal Shift Register.
Memory Elements and Storage Devices
Storage devices and their applications
 13 RAM and ROM Quiz4
Basic memory design and application.

14 Counters and timers include various types like Digital Design (Ch. 6)
ripple, binary, BCD, synchronous, up-down, ring,
and Johnson counters, each serving different
counting and timing functions in digital circuits.
15 Open Hardware and Open Software Digital ) Quiz 4
Logic Technologies

16 CEP Project Evaluation

17 Advanced Topics and Revision

4. TEACHING METHODOLOGY
Lectures
Discussion
Tutorials

5. TEACHING MATERIAL
Text Books
1. Digital Design: With an Introduction to the Verilog HDL, by M. Morris Mano and
Michael D. Ciletti, 5th Edition, Pearson, 2013.
2. Logic and Computer Design Fundamentals, by M. Morris Mano, Charles R. Kime,
Tom Martin, 5th or 4th Edition, Prentice-Hall, 2015.

Reference Books
 1. Digital Design and Computer Architecture by D. M. Harris and S. L. Harris, 2nd
Edition, Morgan Kaufmann, 2013.
2. Digital Systems Principles and Applications” by Tocci and Widmer, 12th Edition,
Pearson, 2017.

6. ONLINE RESOURCES

7 COURSE ASSESSMENT AND EVALUATION

The student's performance will be assessed through a number of assessment instruments. The
table below displays the appropriate distribution of grade weights and their corresponding
linkage with the stated CLOs.
Assessments Instruments Grade Course
No Weight Learning
Outcomes
% 1 2 3
1 Continuous Assignment 1 2.5 ✔
2 Assessments (60%) Assignment 2 2.5 ✔
3 Quiz 1 2.5 ✔
4 Quiz 2 2.5 ✔
5 Quiz 3 2.5 ✔
6 Quiz 4 2.5 ✔
7 Midterm 30 ✔ ✔
8 CEP 15 ✔ ✔
9 Final Examination (40) 40 ✔ ✔

8. UNIVERSITY POLICIES
The students are required to fully understand and observe the following policies of the
university. Seventy five (75%) attendance is mandatory for the lectures/laboratory work
delivered in the course.
For further details, please refer to the university policies mentioned in the student handbook and
undergraduate academic regulations of Namal University Mianwali.

9. VERIFICATION
(i) I verify that the content of this document are correct and up-to-date.

_Dr. Tassadaq Hussain

Instructor’s Name and Signature Date
(ii) I have reviewed the course-outline and state that it complies with Namal Institute
policies and guidelines.

__Dr. Sami Ud Din_

Name and Signature of Head of Department Date