RECORD NOTEBOOK
DEGREE :[Link]
BRANCH :INFORMATION
TECHNOLOGYYEAR/SEM/SEC:II / III / A
NAME
REGISTER. NO
SUBJECT CODE BEC18IL1
SUBJECT NAME DIGITAL SYSTEMS LAB
REGULATION 2020
1
BONAFIDE CERTIFICATE
Register No :
Name of the Lab: Digital Systems
LabDepartment : IT
Certified that this is a bonafide record of work done by---------------of II Year IT
ASection in the Digital Systems laboratory during the year 2021-2022.
Signature of Lab-in-Charge Head of the Department
Submitted for the practical Examination held on
Internal Examiner External Examiner
2
TABLEOFCONTENTS
[Link] Date Name of the Experiment Page
No
6.10.2021
1 VERIFICATIONOFTRUTHTABLESOFLOGICGATES 4
8.10.2021
2 IMPLEMENTATION OF BOOLEAN FUNCTIONS 10
11.10.2021
3 DESIGN AND IMPLEMENTATION OF 13
HALFADDER AND FULL ADDER
11.10.2021
4 DESIGN AND IMPLEMENTATION OF 16
HALFSUBTRACTOR AND FULL
SUBTRACTOR
12.10.2021
5 MULTIPLEXER 18
12.10.2021
6 DEMULTIPLEXER 20
18.10.2021
7 ENCODER 22
18.10.2021
8 DECODER 25
21.10.2021
9 FLIP FLOPS 27
25.10.2021
10 REGISTERS 29
01.11.2021
11 CONSTRUCTION AND VERIFICATION 35
OFCOUNTERS
03.11.2021
12 ANALOG TO DIGITAL CONVERTER 37
3
EXP:NO:1: VERIFICATIONOFTRUTHTABLESOFLOGICGATES
AIM:To studyaboutlogicgatesandverifytheirtruthtables.
APPARATUSREQUIRED:
SLNo. COMPONENT SPECIFICATION QTY
1. ANDGATE IC7408 1
2. ORGATE IC7432 1
3. NOTGATE IC7404 1
4. NANDGATE2 I/P IC7400 1
5. NORGATE IC7402 1
6. X-ORGATE IC7486 1
7. NANDGATE3 I/P IC7410 1
8. ICTRAINERKIT - 1
9. PATCHCORD - 14
4
THEORY:
Circuitthattakesthelogicaldecisionandtheprocessarecalledlogicgates.
Eachgatehasoneormoreinput andonlyoneoutput.
OR, AND and NOT are basic gates. NAND, NOR and X-OR are
[Link] formthesegates.
ANDGATE:
TheANDgateperformsalogicalmultiplicationcommonlyknownasANDfunctio
n. The output is high when both the inputs are high. The output is lowlevelwhen
anyoneof the inputsislow.
ORGATE:
[Link]
[Link]
inputsarelow.
NOT GATE:
The NOT gate is called an inverter. The output is high when the
[Link].
NANDGATE:
TheNANDgateisacontractionofAND-
[Link] low and any one of the input is low .The
output is low level whenboth inputsarehigh.
NORGATE:
[Link]
[Link] or bothinputsarehigh.
5
X- ORGATE:
[Link]
putsarehigh.
PROCEDURE:
(i) Connectionsaregivenaspercircuitdiagram.
(ii) Logicalinputsaregivenaspercircuitdiagram.
(iii) Observetheoutputandverifythetruthtable.
ANDGATE:SYMBOL:PI
NDIAGRAM:
ORGATE:
6
NOTGATE:
SYMBOL: PINDIAGRAM:
X-OR GATE:
SYMBOL:PINDIAGRAM:
7
2- INPUTNANDGATE:
SYMBOL: PINDIAGRAM:
8
NORGATE:
RESULT:Thus the different kind so of logicgates are studied.
9
EXP: NO:2IMPLEMENTATION OFBOOLEANFUNCTIONS
AIM:ImplementationoftheGivenBooleanFunctionsusingLogicGatesinBothSopandPos
Forms.
Twoinput SOP: Y =A.B +A.𝐵̅
Twoinput POS:Y = (A+B)(A+𝐵̅ )
I.
II.
EQUIPMENTREQUIRED:PowerSupply,DigitalTrainer,IC’s(7404,7408,7432)Connectingleads.
THEORY
SOP FORM OF BOOLEN FUNCTION:The sum of product or SOP form is represented
byusingbasic logic gates like AND gate and OR gate. The SOP form implementation will have
theANDgate at its input side and as the output of the function is the sum of all product terms, it
hasan ORgate at its outputside. This is important to remember that we use NOTgate to represent
the inverse or complement of the variables.
POS FORM OF BOOLEN FUNCTION:
The product of sums or POS form can be represented by using basic logic gates like AND gate
and OR gates. The POS form implementation will have the OR gate at its input side and as the
output of the function is product of all sum terms, it has AND gate at its output side .In POS
form implementation ,we use NOT gate to represent the inverse or complement of the variables.
LogicdiagramforSOP Boolean function
AB
A
AB
7404
10
TruthTableforthis SOPexpression
𝐵̅
𝐵̅
A.
=A.B+A.𝐵̅
A B A.B Y
0 0 1 0 1 1
0 1 0 0 0 0
1 0 1 0 1 1
1 1 0 1 0 1
LogicDiagramFor POSForm
AB
Y=(A+B)(A+𝐵̅ )
A
𝐵
TruthTableFor POSExpression
𝐵̅ (A+𝐵̅ )
A B � A+B A+ Y=(A+B)
�
̅
0 0 1 0 1 0
0 1 0 1 0 0
1 0 1 1 1 1
1 1 0 1 1 1
11
PROCEDURE
SOPform
1. Place the Digital lab kit at one place.
2. Take the one ANDgate ICs i.e. ICno.7408,one NOTgate IC i.e. IC no.7404 and one ORgate
IC i.e. IC no.7432.
3. Place these 3 ICs in the bread board one by one.
4. Now, connect the AND gate with the inputs of A and B and other AND gate in the same IC is
given by the complement input of the A and B i.e. A’ and B’ by using NOT gate with the help of
connecting wires.
5. Give the output voltage Vcc and GROUND to all the ICs separately.
6. When whole configuration is read, gently on the switch and note there output of different values
of A and B i.e. either 0 or 1.
ForPOSform
Place the Digital lab kit at oneplace.
1. Take the1OR,1AND, 1NOTgates IC
2. Place these 3ICs in the breadboard
onebyone.3.
Now,connecttheORgateofInputAorB,BorCandlastoneisAorC’([Link].
Inputs areconnectedwith the help of connectingwires.
4. Whenwholecircuitiscomplete,ontheswitchandnotedowntheoutputwithdifferentvaluesofA,
BandC.
RESULT:-Hence, givenBooleanExpressionisimplementedbytheLogicGates.
1. Y =A.B+A.𝐵̅
2. Y = (A+B) (A+𝐵̅ )
12
EXP:NO:3DESIGNANDIMPLEMENTATIONOFHALFADDERAND FULLADDER
AIM:
Todesignandimplementthehalfadderandfulladdercircuitsusinglogicgatesandto
verifyits truth tables.
EQUIPMENTREQUIRED:
Digital TrainerkitIC7408–
ANDICIC7432–ORICIC7486–
EXORICIC7404–NOTIC
THEORY:
HalfAdder:
A combinational circuit that performs the addition of two bits is called half adder.
Ahalfadder circuit needs two binary inputs and binary outputs. The input variable
designatestheaugendsand the addendbits. Theoutput variablesproducethe sum andthecarry.
[Link] of
thesum.
ThesimplifiedBooleanfunctionsforthetwooutputscanbeobtaineddirectlyfrom
thetruth table.
S=X’Y+XY’C=XY
FullAdder:
A full adder is a combinational circuit that forms the arithmetic sum of three input
[Link] of three inputs and two outputs. The two outputs are designated by the symbols
Sforsumand C forcarry.
[Link]
13
variableCgivestheoutputcarry.
Whenallinputsare0,[Link]
outputhas acarryof 1if twoorthreeinputs are equal to 1.
ThesimplifiedBooleanfunctionsforthetwooutputscanbeobtaineddirectlyfromthetruth
table.
S=X’YC’+X’YZ’+XY’Z’+XYZC=XY+XZ+YZ
14
PROCEDURE:
1. Theconnectionsaregivenperthelogicdiagram.
2. Thesupplyvoltage andtheground areconnectedto theappropriate pins.
3. Theinputsaregiven [Link] the switchis ONinputis 1,otherwise 0
4. TheoutputobtainedfromLEDglows outputis1, else0
5. Forvariouscombinationsofinputtheoutputisverified.
RESULT: Thus an addercircuits using logic gates were implemented and
itstruthtablesareverified
15
EXP:NO:4:DESIGNANDIMPLEMENTATIONOFHALFSUBTRACTORANDFULLSUBTRACTOR
AIM:
Todesignandimplementthehalfsubtractorandfullsubtractorcircuitsusinglogicgates
and toverifyits truth tables.
EQUIPMENTREQUIRED:
Digital TrainerkitIC7408–
ANDICIC7432–ORICIC7486–
EXORICIC7404–NOTIC
THEORY:
HalfSubtractor:
Ahalfsubtractorisacombinationalcircuitthatsubtractstwobitsandproducestheirdifferences.
A half subtractor needs two binary inputs and two binary outputs. The
[Link]
differenceandborrow.
The simplified Boolean functions for the two outputs can be easily obtained
directlyfromthetruth table.
D=X’Y+XY’B=X’Y
FullSubtractor:
A full subtractor is a combinational circuit that performs a subtraction between
threebits,1 may have been borrowed by a lower significant bit. This circuit has three inputs and
[Link] three inputs a, b and c denote the minuend subtrahend and previous borrow. The
twooutputsDand B represent thedifferenceand output borrow.
16
ThesimplifiedBooleanfunctionsforthetwooutputscanbeobtaineddirectlyfromthetruth table.
D=X’Y’Z+X’YZ’+XY’Z’+XYZB=X’Y+X’Z+YZ
Truthtableofhalfadder
Truthtableforfull
INPUTS OUTPUTS
X Y Z D B
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
RESULT:ThusHalfsubtractorandFullsubtractorcircuitusinglogicgateswereconstructedandits
truthtables wereverified.
17
EXP:NO:5: MULTIPLEXER
AIM:
ToconstructtheMultiplexerusinglogicgatesandverifyitstruthtable
APPARATUSREQUIRED:
1. Digitaltrainerkit
2. IC7404–NOTIC
3. IC 7411-3 I/P AND GATE
THEORY:
Multiplexer
Multiplexer is a combinational circuit that selects binary information from one of many input
linesanddirects it to a single output line. A multiplexer is also called as data selector. Normally there are
2ninputlinesandn selection lines whosebit combinationsdeterminewhich input is selected.
In a 4 to 1 line multiplexer, each of four input lines I 0to I3is applied to one input of an
[Link] lines S1and S0are decoded to select a particular AND gate. The function table lists the input
tooutputpath for each possible bit combination of selection linesTo demonstrate the circuit operation consider
thecasewhen S1S0=10. The AND gate associated with input I2has two of its inputs equal to 1 and third
inputconnectedtoI2.TheotherthreeANDgateshaveatleastoneinputequalto0,whichmakestheiroutputequalto
0. TheOR gate have at least one output is now equal to the value of I 2, thus providing path from the
selectedinput tothe output.
PROCEDURE:
1) Supplyvoltageandground areconnectedto the appropriate pins.
2) TheinputandoutputareconnectedtoswitchesandLEDsrespectively.
3) Forvariousselectinputcombinations,theoutputis verified.
18
Circuitdiagramfor1x4Multiplexer
Truthtablefor1X4Multiplexer
RESULT :To constructthe Multiplexerusinglogicgates andverifyitstruth table
19
EXP:NO:6:DEMULTIPLEXER
AIM:
ToconstructDemultiplexer usinglogic gatesandverifyitstruthtable.
APPARATUSREQUIRED:
[Link]
2.IC7404–NOTIC
3.IC7408–ANDIC
THEORY:
DeMultiplexer
A demultiplexer is a combinational logic circuit that receives the information on a single input and
transmitsthesame information over one of 2n possible output lines. The bit combinations of the select lines
controltheselection of specific output line to be connected to the input at given instant.A 1-to-2 demultiplexer
consistsofone input line, two output lines and one select line. The signal on the select line helps to switch the
input tooneof the two outputs. There are only two possible ways to connect the input to output lines, thus only
oneselectsignal is enough to do the demultiplexing operation. When the select input is low, then the input will
bepassedto Y0 and if the select input is high then the input will be passed to Y1. Demultiplexers are also called
asdatadistributors, sincetheytransmit thesamedata which is received at theinput to different destinations.
PROCEDURE:
4) Supplyvoltageandgroundareconnected totheappropriate pins.
5) TheinputandoutputareconnectedtoswitchesandLEDsrespectively.
6)
Forvariousselectinputcombinations,[Link]
uitdiagram for1x4 Multiplexer
20
Logic DiagramforDemultiplexer TruthTablefor1X4Demultiplexer
RESULT :To constructthe Multiplexerusinglogicgates andverifyitstruth table
21
EXPNO:7ENCODER
AIM
: Todesignandimplementusing ENCODERlogicgatesandverifyitstruthtable
APPARATUSREQUIRED:
[Link]. COMPONENT SPECIFICATION QTY.
1. ORGATE IC7432 3
2. ICTRAINERKIT - 1
3. PATCHCORDS - 27
THEORY:
ENCODER:[Link]
[Link]
binarycode corresponding to the input value. In octal to binary encoder it has eight
inputs,one foreachoctaldigitand
[Link]
hasavalueofoneat anygiven timeotherwisethecircuit ismeaningless. It has an ambiguila that
when all inputs are zero the outputs are zero. Thezerooutputs canalsobe generatedwhen
D0=1.
22
LOGICDIAGRAMFORENCODER:
TRUTHTABLE:
INPUT OUTPUT
Y1 Y2 Y3 Y4 Y5 Y6 Y7 A B C
1 0 0 0 0 0 0 0 0 1
0 1 0 0 0 0 0 0 1 0
0 0 1 0 0 0 0 0 1 1
0 0 0 1 0 0 0 1 0 0
0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 1 1 1 1
23
PROCEDURE:
(i) Connectionsaregivenaspercircuitdiagram.
(ii) Logicalinputsaregiven aspercircuitdiagram.
(iii) Observetheoutputandverifythetruthtable.
RESULT: Thus the design and implementation of encoder using logic gates and its
verifieditstruth table.
24
EXPNO:8:DECODER
AIM
: TodesignandimplementDECODERusinglogicgatesandverifyitstruthtable
APPARATUSREQUIRED:
[Link]. COMPONENT SPECIFICATION QTY.
1. 3I/PNANDGATE IC7410 2
2. NOTGATE IC7404 1
3. ICTRAINERKIT - 1
4. PATCHCORDS - 27
THEORYDECODER:
Adecoderisamultipleinputmultipleoutputlogiccircuitwhichconvertscodedinputinto
[Link]
[Link]
mapping can be expressed in truth table. In the block diagram
ofdecodercircuittheencodedinformationispresentasninputproducing2npossibleoutputs.2noutputv
aluesarefrom0 throughout2n–1.
25
LOGICDIAGRAMFORDECODER
TRUTHTABLE:
INPUT OUTPUT
E A B D0 D1 D2 D3
1 0 0 1 1 1 1
0 0 0 0 1 1 1
0 0 1 1 0 1 1
0 1 0 1 1 0 1
0 1 1 1 1 1 0
PROCEDURE:
(i) Connectionsaregivenaspercircuitdiagram.
(ii) Logicalinputsaregivenaspercircuitdiagram.
(iii) Observetheoutputandverifythetruthtable.
RESULT:Thusthedesignandimplementationofencoderanddecoderusinglogicgates.
26
EXP:NO:9:FLIPFLOPS
Aim:‐Todesignandconstruct basicflip-flopsR-S,J-K,J-K Masterslaveflip-flopsusinggatesandverifytheirtruthtables
EQUIPMENTREQUIRED
1IC‟s-7404,7402, 7400
2Electroniccircuitdesigner3Connectingpatchchords
THEORY:
JK Flip Flop: A JK Flip Flop is a refinement of the RS Flip Flop in that the indeterminate state of the RS
[Link] inputs
J and K are equal to 1, the flip-flop switches to its complement state that is the flip-floptoggles itsoutput.
T Flip Flop: The T flip flop is a single input version of the JK flip-flop. The T flip-flop is obtained from
theJKflip-flop when both inputs are together. The designation T comes from the ability of the flip-flop to
toggleitsstate.
D Flip Flop: One way to eliminate the undesirable condition of the indeterminate state in the RS flip flop
istoensure that inputs S and R are never equal to 1 at the same time. This is done in D flip flop. The D
inputhasonlytwo inputsD and [Link] D=1and clk=1 outputgoesto 1and ifD=0and clk =1then outputgoesto 0.
PROCEDURE:
1. Connectthecircuitas showninlogic connectionsforJK, DandT FlipFlops.
2. Verifythe truth table of all the FlipFlops.
27
Logicdiagramandtruth tableofJK flip flop
Logicdiagramand truthtableofRS flip flop
CLK INPUT OUTPUT
State
Clock S’ R’ Q Q’
LOW x x 0 1
HIGH 0 0 0 1
HIGH 1 0 1 0
HIGH 0 1 0 1
HIGH 1 1 1 1
28
Logicdiagramandtruth tableofD flip flop
Clock OUTPUT
D Q Q’
X X 1 0
X X 0 1
X X 1 1
HIGH 0 0 1
HIGH 1 1 0
LogicDiagramand TruthTableof T FlipFlop
Clock INPUT OUTPUT
RESET T Q Q’
X LOW X 0 1
HIGH HIGH 0 NoChange
HIGH HIGH 1 Toggle
LOW HIGH X NoChange
RESULT:
ThusthecharacteristicsofRS,JK,DandTflipflopsusingIC’swerestudied.
29
EXP:NO:10:REGISTERS
AIM:
To construct and verify the truth table of the following shift registers for4 bit
using D Flip Flop
30
1.
SerialI
nSerial
Out
2.
SerialI
nParall
elOut
3.
Paralle
lInPara
llelOut
4.
Paralle
lInSeri
alOut.
EQUIPMENTREQUIRED:
DigitalTrainerkitIC7474
THEORY:
Shift registers area type of sequential logic circuit, mainly for storage of digital data. They are agroup
offlip-flops connected in a chain so that the output from one flip-flop the input of the nextflip-
[Link]-flopsaredrivenbyacommon
clock, and allaresetorresetsimultaneously.
SerialIn -SerialOutShiftRegisters:
Theregisterisfirstcleared,[Link] appliedsequentially to
the D input of the first flip-flop on the left (FF 0). During each clock pulse, onebit istransmittedfrom
left to right.
SerialIn-ParallelOutShiftRegisters:
Forthiskindofregister,databitsareenteredseriallyinthesamemannerasdiscussedinthelastsection.
Thedifferenceis thewayin which thedata bits aretaken
31
[Link],eachbitappearsonitsrespectiveoutputline,andallbits
areavailable simultaneously.
ParallelIn -SerialOutShiftRegisters:
The circuituses D flip-flops and NAND gates for entering data (iewriting) to the register .D 0,D1,D2
and D3 are the paralle linputs ,where D0 is the most significant bit and D3 is the least significant bit .To write
data
in ,[Link]
GH asSHIFTisactivehigh.
ParallelIn -ParallelOutShiftRegisters:
Forparallelin-
paralleloutshiftregisters,alldatabitsappearontheparalleloutputsimmediatelyfollowingthesimultaneouse
[Link]'saretheparallelinputsandtheQ'saretheparallel outputs. Once the register is
clocked, allthe data at the D inputs appear atthecorrespondingQoutputssimultaneously.
PROCEDURE:
1. Theconnectionsaregivenasperthe circuit diagram
2. Verifythetruth table.
PINDIAGRAM:
DualD Flip Flop
32
CIRCUITDIAGRAMS:
Serialin -SerialOutShiftRegisters
SerialIn-
33
ParallelIn -SerialOutShiftRegisters:
ParallelinParalleloutShiftregisters:
34
TRUTHTABLES:
Serialin -SerialOut
SerialInParallelOut
ParallelInserialOut
35
ParallelInparallelOut
RESULT:
Thusshiftregisters aredesignedandverifiedtheirtruthtables respectively
36
EXP:NO:11: CONSTRUCTIONANDVERIFICATIONOFCOUNTERS
AIM:
TostudyandimplementJohnsonringcounter andverifyitstruthtable.
EQUIPMENTREQUIRED:
Digital
Trainerkit7
4LS74IC
Connectingwires
THEORY:
A counter is used to count are peated set of values for avariable like clockpulse.
TheJohnsonRingCounteror“TwistedRingCounters”,is ano
Her
Shift register with feedback exactly the same as the standard RingCounter above, except that this
time the inverted output Q of the last flip-flop is now connected back to the input D of the first
flip-flop as shownbelow.
The main advantage of this type of ring counter is that it only needs half the number of flip-
flopscompared to the standard ring counter then its modulo number is halved. So a “n-
stage”Johnsoncounter will circulate a single data bit giving sequence of 2n different states and
cantherefore beconsideredasa “mod-2ncounter”.
PROCEDURE:
1. TheD flipflops are connected as shown in logic diagram.
2. Theclockpulse isapplied and theoutputis verified byreadingthe LEDoutput.
3. Verifythecorrespondingtruthtable.
37
LogicdiagramforJOHNSONRINGcounter
TruthtablesforJOHNSONRINGcounter
RESULT:
Thus JOHNSON RING counter was designed and implemented & its truth
tablewasverified.
38
EXP:NO:12ANALOGTODIGITALCONVERTER
AIM
TostudythecharacteristicsofAnalogtodigital converter.
PPARATUSREQUIRED:
[Link] APPARATUS RANGE QUANTITY
1. IC μA741 1
2. Resistor 10KΩ, 4nos
3. IC 7408 1
4. IC 7432 1
5. Multimeter - 1
6. RPS DUAL(0-30)V 1
7. ConnectingWires
THEORY:
InweightedresistortypeDAC,op-
ampisusedtoproduceaweightedsumofdigitalinputswhereweightsarepro
[Link]
equaltoratioof feed back resistance to input resistance towhichit
isconnected.
VOUT=-RF//R (D3+1/2D2+¼ D1+1/8D0)
TheR-2 Rladder type DAC uses resistor of only two values R and 2R.
The inputs to resistor network may be applied through digitally
connected switches or from output pins of a counter .The analogue
output will be maximum,when allinputs are of logichigh.
V=-Rf/R(1/2 D3+1/4D2+1/8D1+1/16D0)
In a3 input ADC, if the analog signal exceeds there ference
signal, comparator turn son. If all comparators are off, analog
inputwill be between 0 and V/[Link] C1 is high and C2 is lowinput
will bebetween V/4 andV/[Link] C1 andC2 are high and C3 islow
input willbebetween 3V/4 andV.
PROCEDURE:
1. Connect the circuit as shown in circuit diagram.
2. Forvarious inputs, measurethe outputs using multimeter
39
CIRCUITDIAGRAM:
[Link]: ANALOGI DIGITALOUTPUT
NPUT A B C
1) 0-1 0 0 0
2) 1-2 0 0 1
3) 2-3 0 1 0
4) 3-4 0 1 1
5) 4-5 1 0 0
Result:
Thus a AtoD was constructed using IC and its truth table was verified
40
