2/10/2025

FUNDAMENTAL OF ELECTRICAL AND

ELECTRONICS ENGINEERING
(EX 101)

Chapter 5: Transistor
Er. Chaitya Shova Shakya
Senior Lecturer
Kathford International College of Engineering & Management

Chapter Outline
5.1 Introduction
5.2 BJT configuration
5.3 BJT biasing
5.4 Large signal model
5.5 Small signal model - π and T model
5.6 Concept of differential amplifier using BJT
5.7 BJT switch and logic circuits
5.8 Field Effect Transistor
5.9 Junction Field Effect transistor
5.10 Construction and working principle of MOSFET
5.11 MOSFET as logic circuits
5.12 Construction and working principle of CMOS
5.13 Depletion type MOSFET
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5.1 Introduction
• Transistor is a three terminal semiconductor device that can produce amplification (gain) in a
circuit.
• In transistor, a voltage or current applied to two terminals controls the current flowing in the third
terminal.
• Used as an amplifier or a switch.
• Transistors are used in integrated circuits, optoelectronic devices, microprocessors etc.
• Advantages
– very long life, smaller in size, lower cost
– fast switching, low operating voltages for greater safety
• Types
– Bipolar junction transistor (BJT)
– Field effect transistor (FET).

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Bipolar junction transistor (BJT)

• Bipolar junction transistor (BJT) is a three terminal semiconductor device.
• BJT is made of three alternate layers of p and n type semiconductor forming two pn
junctions connected in series, back to back.
• Types: npn transistor and pnp transistor.

• Doping level and thickness of the regions are different - BJT is not a symmetric device.
• The terminals are called emitter (E), base (B), and collector (C).
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Modes of operation
• BJT has two pn junctions:
– emitter-base junction (EBJ)
– collector-base junction (CBJ)
• Depending on the bias condition (forward or reverse) of the junctions, the BJT can
operate in three modes.
Mode EBJ CBJ Remark
Cutoff Reverse Reverse Switching applications
Active Forward Reverse Amplifier circuits
Saturation Forward Forward Switching applications

• In BJT, current is conducted by both electrons and holes  bipolar junction

transistor.
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Schematic symbol of BJT

(a) npn transistor (b) pnp transistor

• In symbol, the arrow indicates the emitter terminal and always points to n-type material.
– In npn – arrow points out (NPN: Not Pointing iN)
– In pnp – arrow points in.
• The arrow also indicates the direction of conventional current flow in the emitter terminal.
• Terminal currents are defined in the direction as current flow in the active mode.

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Voltage polarities and current flow in npn transistor

• In BJT, terminal currents are defined in the
direction as current flow in the active mode.
VCC VCB  VC 
IB IC • The EBJ is forward biased by VBB supply and
VB 
VCE the CBJ is reverse-biased by VCC supply.

VBB VBE IE • Terminal currents are IB , IC , IE in which
  IB < IC < IE
VE
• In transistor, IE = IC + IB
• Terminal voltages are VB , VC , VE in which
VC >VB>VE
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5.2 BJT configuration

• In BJT circuit, two terminals of a transistor are used for input and output and
third terminal is common to both input and output.

• According to the common terminal used in the circuit connection, there are
three types of BJT circuit configuration.
– Common base configuration (CB)

– Common emitter configuration (CE)

– Common collector configuration (CC)

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Common-base configuration
• In CB configuration,
– Base is common terminal.
IE IC
– Emitter is input terminal.  
– Collector is output terminal. VBE VCB
– Input current is IE IB
 
– Input voltage is VE
– Output current is IC
– Output voltage is VC
• The current gain of CB configuration is known as common-base current gain (α).
• Large-signal or dc alpha  dc    IC I E
• Its value is less than but close to 1 (0.95 to 0.99).

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Common emitter configuration

• In CE configuration,
IC
– Emitter is common terminal.
IB 
– Base is input terminal.
– Collector is output terminal.  VCE
– Input current is IB VBE IE
– Input voltage is VB  
– Output current is IC
– Output voltage is VC
• The current gain of CE configuration is known as common-emitter current gain (β).
• Large-signal or dc beta dc    IC I B
• Its value ranges from 50 to over 400 (up to 1000) depending on the types of the
transistor used.

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Common collector configuration

• In CC configuration, IE
– Collector is common terminal IB 
– Base is input terminal
 VCE
– Emitter is output terminal.
VCB IC
– Input current is IB  
– Input voltage is VB
– Output current is IE
– Output voltage is VE

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Relationship between α and β

For BJT, we have

I E  I B  IC
Dividing both sides by IC ,

I E I B IC
 
IC IC IC
1 1
 1
 
 
 
1  1

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Characteristic curves of CE configuration

• Input characteristic curve • When VCE = 0, the CBJ has no effect
I B  f VBE  as VCE  constant on the performance of the transistor.
– The transistor is equivalent to a
forward biased diode.
I B  μA  VCE  1 V
VCE  10 V – the curve is simply the characteristic
VCE  20 V curve of the forward biased diode.
• As VCE is increased, the IB decreases
VBE for fixed value of VBE .
0.7 V

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• Output characteristic curve Four regions of operation:

• Cut off region: a region below the
I C  f VCE  for I B  constant curve IB = 0. It is a non-conducting
state of a transistor.
IC • Active region: a region where the
 mA  curves are almost horizontal. The
transistor acts as a current source. In
I B  40 μA this region, the collector current is βIB.
I B  30 μA
• Saturation region: a region left to
VCEsat (typical value is 0.2 V). In this
I B  20 μA region, the collector current is
I B  10 μA independent of the base current.
IB  0 • Breakdown region: a region of higher
VCE where IC increases rapidly.
0 VCE sat BVCEO VCE  V 
I CEO

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5.3 BJT biasing

• The purpose of dc biasing is to set the operating point that is independent of β
change and temperature variation.
* Operating point is the point on the output characteristics that gives VCE and IC
with no input signal; aka bias point or Q-point (Quiescent point).
• Types of biasing methods used in BJT circuits
– Fixed bias (Base bias)
– Emitter feedback bias (current feedback)
– Collector feedback bias (voltage feedback)
– Voltage divider bias (universal biasing method)
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Fixed bias
RC IC
RB I B 
VCE VCC
 
VBB VBE 
IE

VCC

RB RC IC IC
RB RC
IB 
VCC IB 
VCE
 VCE
 
VBE IE VBE 
 

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Emitter feedback bias

VCC

RB RC IC
IB 
 VCE
VBE  

RE IE

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Collector feedback bias

VCC

RC IC  I B  I E

IC
IB RB 
VCE

VBE 
 IE

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Voltage divider bias

• Aka universal biasing method or β-independent biasing method
VCC VCC VCC VCC

R1 IC R1 RC IC R1 R1
RC
IB  IB 
VCE VCE

   RTh
R2 VTh  VBB R2
R2 R2 RE IE  RB
RE IE 

R2 R1 R2
VBB  VCC RB  R1  R2 
• First thevenize the input circuit. R1  R2 R1  R2
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Voltage divider bias (contd..)

VCC
 R2 
VBB  VCC  
 R1  R2  RC IC
IB 


VCE
RB VBE 

 R1  R2
RE IE

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5.4 Large signal model of BJT

• When a transistor is operated in active mode, the EBJ behaves like a forward biased
diode and output is a controlled current source.
IC
IB IC IB IC
B C B C
 
IB  VBE  IB VBE g mVBE

VCE  
 IE IE
VBE IE
 E E

(a) CCCS form (b) VCCS form

• In this model, replace a forward-biased diode by its constant voltage drop model i.e.,
VBE = 0.7 V .

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5.5 Small signal model

re model:
• Replace a forward biased diode by its small signal model.
• Small signal model of a diode is a dynamic resistance or ac resistance.
rd = nVT / ID IB IC
B C

where, VT is thermal voltage VBE  IB

ID is dc diode current at Q point. IE
E
• Two variations of this model:
– Hybrid-π model
– T model.

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Hybrid-π model
• Hybrid-π model is used for CE configuration or when the emitter is grounded.
• The ac resistance between base and emitter, looking into the base is
r  v be ib  VT I B

ib ib ic ib ic
B C B C
  
vbe r  ib vbe r g m vbe
vbe  
vbe  g m  I C VT
r  ie ie
ib E r  VT I B   g m E

• Transconductance gm  ic vbe  IC VT

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T model
• T model is typically used for CB configuration or when the emitter is not grounded.
• The ac resistance between base and emitter, looking into the emitter is
re  vbe ie  VT I E

ie ic ie re ic ie re ic
E C E C
  vbe   vbe 
vbe  ie g m vbe
 g m  I C VT
v ib ib re  VT I E   g m ib
re  be B B
ie

vbe 1    vbe
• Relationship between rπ and re: r    1    re
ib ie
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BJT amplifier

RC iC vbe
iB 
vCE VCC
vbe    vce

vBE
VBE iE


• Transistor is biased in active mode and small

signal is applied at base terminal.
• The output is taken at collector terminal.
• The ac output voltage is amplified and is 180◦ out
of phase with respect to ac input voltage.
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Simulated BJT amplifier circuit

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5.6 Concept of differential amplifier using BJT

• A differential amplifier amplifies the difference signal between the two inputs and rejects
signal that are common to both inputs. VCC VCC
• It is widely used as the input stage of an OP amp.
• Construction of differential amplifier RC RC

– It has two matched transistors.  vod 

vo1 vo 2
– The values of collector resistors are equal.
– The emitters are shorted together and connected
vi1 Q1 Q2 vi 2
to a current source.
• It has two input terminals and two output terminals.
• Differential output voltage
I
vod  vo1  vo 2   Avi1    Avi 2   A  vi 2  vi1 
where, (vi2 - vi1) is differential input signal; A differential gain
VEE
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Operation of differential amplifier

a. Same signal is applied to both VCC VCC
inputs (common mode)
• Both transistors conduct equally. RC RC
• The outputs at the collector of both
 vod 
transistors are equal and inverted. iC1 vo1 vo 2
iC 2
• The differential output is zero .
Q1 Q2
vod  vo1  vo 2  A  vi 2  vi1  iE1 iE 2
vi1 vi 2
0
I
• The differential amplifier rejects
common mode signal.
VEE

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b. When differential signal is applied

• One transistor conducts more and another less by the amount proportional to
the difference input voltage.

• If vi1  vi 2 , vod  A  vi 2  vi1    Avid

– Output is amplified and out of phase with the input signal vi1.

– Terminal 1 is called an inverting terminal.

• If vi 2  vi1 , vod  A  vi 2  vi1   Avid

– Output is amplified and in phase with the input signal vi2.

– Terminal 2 is called a non inverting terminal.

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5.7 BJT switch and logic circuits

• Transistor switch is the basis for many digital circuits.
• When a transistor is used as a switch, it operates either in cutoff or saturation region.
VCC VCC VCC
iC
RC IC RC IC RC IC  0
VCC
IB RC C C
VCE  0 VCE  VCC
VI VCE
RB E E

VCC vCE
• When the input is high, the transistor operates in saturation region.
– VCE ideally drops to zero and IC is maximum saturated transistor acts as a closed switch.
• When the input is low, the transistor operates in cutoff region.
– The IC is zero and VCE equals the supply voltage. It acts as an open switch.
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Inverter circuit or NOT gate

• The BJT switch is actually an inverter circuit.

VCC
Truth table of NOT gate
VI RC IC VO
VI VO
5V IB VO 5V 0 1
VI VCE t
1 0
t RB

• When the input is low, the transistor is cut off. So, the output voltage equals to VCC (high).
• When the input is high, the transistor turns on. The output voltage ideally drops to zero (low)
because the emitter is connected to ground.

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NOR gate
VCC

RC
Truth table of NOR gate
VO V1 V2 VO
RB1 RB 2 0 0 1
V1 Q1 V2 Q2 0 1 0
1 0 0
1 1 0

• When both inputs are low, both Q1 & Q2 are cut off  output voltage equals to VCC
(high).
• When either input is high, the corresponding transistor turns on shorting output to
ground  output voltage ideally drops to zero (low).
• When both inputs are high, both transistors turn on shorting output to ground 
output voltage ideally drops to zero (low).
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NAND gate
VCC
RC
NAND gate
VO
RB1 V1 V2 VO
V1 Q1 0 0 1
RB 2 0 1 1
V2 Q2 1 0 1
1 1 0

• When both inputs are low, both transistors turn OFF. So, the output voltage equals
VCC (high).
• When either input is low, the corresponding transistor turns OFF. So, the output
voltage equals to VCC (high).
• When both inputs are high, both transistors turn on shorting output to ground. Hence,
the output voltage ideally drops to zero (low).
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5.8 Field Effect Transistor (FET)

• Field Effect Transistor (FET) is
– Voltage controlled device (BJT - Current controlled device)
– Unipolar device – conduction due to either electron (for n channel) or hole
(for p channel)
– High input impedance and low power consumption
– More temperature stable than BJT
– Smaller in construction - useful in integrated circuit (IC)
– Easy to manufacture compare to BJT - used in Very Large Scale Integrated
(VLSI) circuits

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Classification of FET
Transistor FET – Field effect transistor
MOSFET – Metal oxide semiconductor FET
IGFET - insulated gate FET
BJT FET

npn pnp JFET MOSFET or IGFET

(Junction)
Enhancement type Depletion type
(channel has to be created) (channel is already present)

n-channel p-channel n-channel p-channel

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5.9 Junction Field Effect transistor

Construction: • In n type silicon slab, p-type regions
are diffused on its two sides.
• These p type regions are connected
together to form a gate terminal.
• The n region acts as a channel.
• The opposite ends of n region forms
drain and source terminals.
• The pn junction formed between
channel and gate defines the operation
of the FET so it is called JFET.

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Operation of n-channel JFET

• For normal operation, gate channel
junction should be reverse biased and
drain should be at higher potential
than source.
With vGS = 0:
• When vDS is applied, iD flows from
drain to source through the channel.
• When vDS is small, vGS ≈ vGD. So, the
channel is uniform  iD rises linearly
 JFET acts as a resistance.

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• As vDS is increased, vGD is more negative

than vGS  gate channel junction is more
reverse bias  depletion width increase at
drain. Hence, the channel starts to taper at
drain side  iD starts to level off.

• When vDS = VP , the channel is pinched

off at drain side current iD saturates.

• This is a maximum drain current that JFET

can produce and is called IDSS (drain to
source current with gate shorted).

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• With vGS < 0, gate channel junction is

more reverse biased  depletion region
widen and channel becomes narrower 
iD decreases.
– More negative the vGS, the pinch off will
occur for smaller values of vDS and max
drain current will also be reduced.
• When vGS = VP , aka VGS OFF , the
depletion region touches each other  the
channel is pinched off  current iD
becomes zero.
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Symbol of n channel JFET Symbol of p channel JFET

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Drain characteristic curve

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Transconductance curve

IDSS = drain to source current with gate

shorted
VGS(off) = VP

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5.10 Construction of n-channel enhancement-type MOSFET

• In p type substrate, two heavily doped n-regions

are embedded which forms source and drain.
• A thin layer of silicon dioxide is grown on the
surface of the substrate covering the area
n n between the source and the drain regions.
• Metal is deposited on top of the oxide layer to
form a gate terminal. Metal contacts are also
made to source, drain, and substrate or body.
• MOSFET has four terminals.
• n-channel enhancement-type MOSFET • The device structure is symmetric.
• n-channel EMOSFET • In some MOSFETs, the body is internally
• enhancement-type NMOS transistor. connected to the source.

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Working principle of n-channel EMOSFET

• For normal operation,
– positive voltage vGS is applied at the
n gate terminal.
– the body is connected to a source
– drain is kept at higher potential than
vDS
source by vDS .
vGS
• When vGS = 0, the channel is not yet
n created  iD = 0
– EMOSFET is a normally off
MOSFET.

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Channel creation • When vGS > 0, the channel starts to build up.
The positive voltage on the gate will
– repel free holes in the channel region and
– attracts free electrons from the highly
iD doped source and drain regions into the
n channel region.
vDS • When vGS = Vt (threshold voltage; typically
iG  0 iD 1-3 V), a thin layer of electrons is
 small 
accumulated under the gate connecting the
vGS source and drain region. The induced n
iS  iD region acts as a conducting channel for the
n current flow hence named a channel or an
inversion layer.
• If vGS > Vt , the channel width and its
conductivity is enhanced.

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When vGS > Vt and vDS is applied  iD flows from drain to source through the channel.
• When vDS is small (around 0.1 or 0.2 V), the induced channel is uniform [⸪ vGD ≈ vGS] 
current iD rises linearly with vDS.
• As vDS is increased, vGD becomes smaller compared to VGS. So the channel starts to taper 
current iD starts to level off.
• When vGD = vGS – vDS =Vt , the channel is pinched off (channel depth decreases to zero) at
drain side.

iD iD

vGD = vGS – vDS
n n
vDS vDS
iG  0 iD iG  0 iD
 small 

vGS vGS
iS  iD iS  iD
n n

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• Increasing vDS beyond this value has no effect on the channel shape  current iD
saturates.
• The voltage at which saturation occurs is denoted by vDS sat = vGS – Vt
• The operation can be described graphically as follows.

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Characteristic curve of n-channel EMOSFET

• Drain characteristic curve • Transconductance curve

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Schematic symbol of the enhancement NMOS

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5.11 MOSFET as logic circuits

NOT gate VDD

RD Truth table of NOT gate

VO VI VO
VI 0 1
1 0

• When the input is at logic-0, the gate to source voltage vGS of NMOS is zero volt. The
NMOS is OFF and acts as an open circuit. Hence, the output is high.
• When input is at logic-1, the vGS of NMOS is VDD volts. The NMOS turns ON and acts as an
closed switch. Thus, the output is low.

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NOR gate VDD

Truth table of NOR gate
RD V1 V2 VO
VO 0 0 1
0 1 0
V1 V2 1 0 0
1 1 0

• When both inputs are low, both NMOSs turn off and act as an open switch. So, the output
voltage equals to VDD (high).
• When either inputs is high , the corresponding NMOS turns on shorting output to ground.
Hence, the output voltage ideally drops to zero (low).
• When both inputs are high , both NMOSs turns on shorting output to ground. Hence, the
output voltage becomes low.

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NAND gate
VDD
NAND gate
RD
V1 V2 VO
VO 0 0 1
V1 0 1 1
1 0 1
1 1 0
V2

• When both inputs are low, both NMOSs turn OFF. So, the output voltage equals to high .
• When either input is low, the corresponding NMOS turns OFF. So, the output voltage equals
to high.
• When both inputs are high, both NMOSs turn on shorting output to ground. Hence, the
output voltage ideally drops to zero (low).
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5.12 Construction of CMOS

• CMOS technology employs both PMOS and NMOS devices.
CMOS –
NMOS PMOS Complementary
S G D D G S MOS
Gate
oxide
SiO2 Thick SiO2 SiO2

n n p p
n well

p-type substrate

• Here, the substrate is p-type, so the NMOS transistor is created directly in the p-type
substrate and PMOS transistor is formed in n well (because PMOS needs an n-type body).
• The two devices are isolated from each other by a thick oxide region.
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Schematic symbol of the enhancement PMOS

• For normal operation of PMOS,

– negative voltage is applied at the gate terminal.
– body is connected to a source
– source is kept at higher potential than drain.

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CMOS logic inverter

VDD
• When input is low,

vSGP – the gate to source voltage of NMOS is
 zero and that of PMOS is -VDD volts.
QP
– The NMOS is OFF and PMOS turns ON.
iDP
– The output is high.
vI vO
iDN
QN • When input is high,

vGSN – the gate to source voltage of NMOS is
 VDD volts and that of PMOS is zero.
– The NMOS is ON and PMOS turns OFF.
Remember: – The output is low.
NMOS conducts when VGS is positive.
PMOS conducts when VGS is negative or VSG is positive.
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• In CMOS switch, PMOS and NMOS are connected like a complementary

switch: when one switch is closed other switch is open and vice versa.

• Properties of CMOS logic circuits

– Voltage swing is maximum possible  0 to VDD .
– Infinite input resistance
– Static power dissipation is zero.
– Low output resistance path  High output current.

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 2/10/2025

Chapter 3 complete!

ANY QUESTION?

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