VLSI Training Services
Setting standards in VLSI Design
Final Test
Time: 3 Hrs Total Marks: 100
Part – A
Marks: 40
Digital (12 Marks)
1. Design half adder circuit using 2-to-4 decoder and some basic gates. -- (5M)
2. Draw the waveform for the fout signal in the following circuit -- (7M)
Verilog (12 Marks)
1. Write an RTL code to design an 8-bit serial-in-parallel-out (SIPO) register, such that it
should act as the right shift register for the first 4 consecutive clock cycles and act as a
buffer for the next 4 consecutive clock cycles. Also, write test bench code for the same
and verify. -- (8M)
2. Draw the RTL schematic for the following snippets -- (4M)
a. always@(posedge clk)
begin
a <= b;
b <= c;
c <= d;
end
b. always@(posedge clk)
begin
a = b;
b = c;
c = d;
end
c. always@(posedge clk)
begin
a = b;
b <= c;
c <= d;
end
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VLSI Training Services
Setting standards in VLSI Design
Verification (16 Marks)
1. Write a constraint to randomly generate 10 real numbers between 1.356 to 2.683
--(5M)
2. Define Mailbox and explain how to create the bounded mailbox and built-in mailbox
methods. -- (6M)
3. Write an assertion for the following condition:
Once enable signal goes high, in the next clock cycle one pulse on signal "a" (whose
width is equal to one clock cycle) should be generated and from there it should be
generated for every ten clock cycles. -- (5M)
Part – B
Marks: 40
Digital (12 Marks)
1. Design a counter that will count the sequence 45,53,51,34 and repeat the same sequence
with 2 flip-flops and some logic gates. -- (7M)
2. Design half subtractor using half adders. -- (5M)
Verilog (12 Marks)
1. Predict the output for the following snippet. -- (5M)
module test();
integer a;
initial
begin
a = 2;
a <= 4;
#2 a = 6;
#2 a <= 8;
#2 a = #2 10;
a = #2 12;
#2 a <= #8 14;
#2 a<= 16;
end
initial
$monitor(“at time t = %t, a is %0d”, $time, a);
endmodule
2. Write Verilog RTL code to infer a 16x4 priority encoder using “case” construct.
-- (7M)
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VLSI Training Services
Setting standards in VLSI Design
Verification (16 Marks)
1. For the following snippet of code predict the coverage % and also write the covered
and uncovered bins. -- (4M)
module cg_test();
bit [4:0]a;
covergroup cg;
c1:coverpoint a {option.at_least = 2;
bins a1[10]={[0:$]};}
endgroup
cg c1;
initial
begin
c1 = new();
for(int i = 0;i < 16;i++)
begin
a = i;
c1.sample ();
end
a = 4'b1010;
c1.sample;
end
endmodule
2. Which macro and severity can be used for debug messages and how do you avoid
debug messages during regression? -- (2M)
3. Explain how communication between two components, Producer & consumer, can be
established using the TLM interface under the following scenarios. (Producer generates
the data item & consumer consumes the data item) -- (10M)
a. Producer as an initiator & consumer as the target.
b. Producer as the target & consumer as an initiator.
c. Both the consumer & producer as initiators.
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VLSI Training Services
Setting standards in VLSI Design
Part – C (Basic Electronics, CMOS, Networks, FPGA, STA)
Marks: 20
15. Find the value of current i4 in the following network:
-- (5M)
16. Given the data setup time of the flop is 6ns, the hold time of the flop is 2ns, and the
clock to Q delay is given as 10ns.
a. Calculate the minimum clock period required to handle the circuit by drawing
a digital logic circuit for function clock frequency divided by 2.
b. Also determine the status of hold time violation and give a proper reason. -- (5M)
17. What will be the voltage at node G in the following CMOS circuit? Assume the initial
voltage at every node is 0.75V. And supply voltage Vdd = 1.5V, Vss = 0V, Threshold
voltage Vth = 0.4V, and |Vtp| = 0.35V.
-- (5M)
18. Prove that the common emitter configuration output signal is 1800 out of phase with
input signal. -- (5M)
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