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Setting standards in VLSI Design
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Centre of
Final Test
TÉme: 3 Hrs Total Marks: 100
Part - A
Marks: 40
Digital(12 Marks)
four 2xl Multiplexers
circuit to the following operation using only
performi (4M)
1. Design a Control Input Operation
Half Adder
1 Half Subtractor
-(4M)
from 2^2x4 RAM chips.
2. Create 2^4 x4 RAM
to flights when
diagram for an airport trafYic controller which gives GRANT of runway
3. Draw astate information. 44M)
REQUEST for take-off from the terminals using the following
they
runway.
a. There are 3 terminals T1,
T2, and T3 sharing only one has to give a
REQUEST runway to take off, the controller
b. When the flight from any terminal
GRANT Of runway. priority
runway, then the terminal with the highest
Note: If more than one flight is requesting thefollows TI>T2>T3.
as
will get GRANT oftherunway. Priority is
Verilog(12 Marks)
the "case" construct. - (6M)
1. Write Verilog RTL code to infer a 16x4 priority encoder using
- (3M)
2. What type of Hardware will be synthesized for the following:
module hardware synth(input |7:0]a,
input (2:0] amt,
output reg [7:0] y);
always @*
case(am)
3'd0: y = a;
3'd1: y=(af0],a{7:1|};
3'42: y=(al1:0],a|7:2)};
3'43: y = (a[2:0),a[7:3);
3d4: y=(a[3:0), a[7:4};
3'45: y =(a[4:0],a[7:5|}:
3'd6: y =fa5:0),a{7:6}:
default : y =(a/6:0),a|7};:
endcase
endmodule
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MAVEN
SILICON
VLSI Training Services
Sctting standards in VLSI Design
in VIS
Centre of Itteente
mode output for the following: - (3M)
3. Display the hatch
module strne:
ininal
berin monitored = %"a:
Smonitor(Srime,"Value ofa
strobed= %d",a):
Sstrobe( Sime,"V'alue of a
:
=%d"a);
Stisplay Stime,"Value ofa displayed
el'bx;
end
endmodule
Verification (16 Marks)
driver with the required snippet of code -- (4M)
1. Explain the data flow between the sequence and
and correct the code:.
2. Find the bug in the below code
(4M)
class parent;
int var;
function new(input int var);
this. var=Var;
endfunction
endclass
class child extends parent;
int varl;
function new(input int varl);
this. varl=yarl;
endfunction
endclass
3. What is the difference between Srose & posedge? - (2M)
4. Write the assertion for 4-bit loadable up-down counter.(Inputs- load, up/down, reset-active high,
data in, output data_out) -- (6M)
MAVEN
SILIC0N
VLSI Training Services
Setting standards in VLSI Design
tentte of Ecellenco in VUSI
Part - B
Marks: 40
Digital(12 Marks) only one
numbers 75 and 98 and repeat the same sequence using
1. Design a counter to count the - (4M)
T-Flip-flop.
clock signal of frequency equal to felk/3 with 50% Duty Cycle.
2. Design acircuit to generate a (4M)
using aminimum number ofD flip Flops and a 4:1Mux
3. Designa synchronous sequential circuit using FSM. -(4M)
"101". Note: Design the circuit without
to Detect the sequence "010" and
Verilog (12 Marks)
-4M)
below is a good portable code &explain why?
4. Find out which of the code mentioned
b) always@(s or r)
a) always@s
begin begin
ifis) ifis)
q<=0; q<=l;
end else iflr)
q<=0;
end
alvays@r
begin
if)
end
32-bit number. - (8M)
2. Write an RTL code to find the number of l's and 0's in a given
Verification (16 Marks)
I. Complete the code given below - (4M)
class trans;
rand bil<7:0Ja{0:3/10:3/;
add constraints to meet the followingconditions
/sum of all the elements in a row should be equal to 50
/sum of all the elements in a column should be equal to 50
I sum of all the diagonal elements should be equal to 50
endclass
MAVER SILIC0N
VLSI Training Services
Setting standards in VLSI Design
tentre ot Ecellenco in VLSI
2. Draw the UVM TB architecture to verify aFIFO of depth 16 bytes and write the interface block &
transaction class definitions for the same -(12 M)
Part-C(Basic Electronics, CMOS, Networks, FPGA, STA)
Marks: 20
12. For the following specifications, check the circuit for any violations &fix them if any. - (5M)
Total net delay = 1.5ns
D Comb = 3ns,
D,
Tnet = 0.5ns Tbuffer = ]ns
Tcik-g =Sus
FF; Tsetup = 3ns
dk Thold =2ns
1Oal neeay =1Is
21. Design CMOS circuit for 3-input NAND gate.
- (5M)
22. Write any five Ideal Characteristics of an Op-Amp.
- (5M)
23. Explain the operation of the Bridge rectifier with relevant equations and
diagrams. - (SM)
