LT3790

60V Synchronous 4-Switch

Buck-Boost Controller

FEATURES DESCRIPTION
n 4-Switch Single Inductor Architecture Allows VIN The LT®3790 is a synchronous 4-switch buck-boost volt-
Above, Below or Equal to VOUT age/current regulator controller. The LT3790 can regulate
n Synchronous Switching: Up to 98.5% Efficiency output voltage, output current, or input current with input
n Wide VIN Range: 4.7V to 60V voltages above, below, or equal to the output voltage. The
n 2% Output Voltage Accuracy: 1.2V ≤ VOUT < 60V constant-frequency, current mode architecture allows its
n 6% Output Current Accuracy: 0V ≤ VOUT < 60V frequency to be adjusted or synchronized from 200kHz
n Input and Output Current Regulation with Current to 700kHz. No top FET refresh switching cycle is needed
Monitor Outputs in buck or boost operation. With 60V input, 60V output
n No Top FET Refresh in Buck or Boost capability and seamless transitions between operating
n VOUT Disconnected from VIN During Shutdown regions, the LT3790 is ideal for voltage regulator, bat-
n C/10 Charge Termination and Output Shorted Flags tery/super-capacitor charger applications in automotive,
n Capable of 100W or Greater per IC industrial, telecom, and even battery-powered systems.
n Easy Parallel Capability to Extend Output Power
The LT3790 provides input current monitor, output cur-
n 38-Lead TSSOP with Exposed Pad
rent monitor, and various status flags, such as C/10
charge termination and shorted output flag.
APPLICATIONS All registered trademarks and trademarks are the property of their respective owners.

n Automotive, Telecom, Industrial Systems

n High Power Battery-Powered System

TYPICAL APPLICATION
120W (24V 5A) Buck-Boost Voltage Regulator
VIN 0.003Ω
12V TO
58V 4.7µF
+ 47µF
VIN INTVCC 100V 80V
1µF 4.7µF
51Ω
BST2 +
470nF
IVINN 220µF
35V
Efficiency vs Load Current
IVINP 0.009Ω VOUT 100
BST1 0.1µF 24V
499k 499k 4.7µF 5A
TG1 50V 95
0.1µF
EN/UVLO ×2
SWI 73.2k 90
OVLO 10µH
BG1
EFFICIENCY (%)

56.2k 27.4k INTVCC 85

3.83k
LT3790 SNSP 80
100k 200k
SHORT 0.004Ω 75
C/10 SNSN
CCM 70
PGND
IVINMON VIN = 12V
BG2 65 VIN = 24V
ISMON
VIN = 54V
CLKOUT SW2 60
PWMOUT TG2 0 1 2 3 4 5
VREF ISP LOAD CURRENT (A)
0.1µF PWM ISN
3790 TA01b

100k CTRL SS SYNC V FB

C RT SGND 3790 TA01a

3.3k 147k
33nF 200kHz
33nF

Rev. B

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LT3790
ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION
(Note 1)
Supply Voltages TOP VIEW

Input Supply (VIN)......................................................60V CTRL 1 38 OVLO

SW1, SW2...................................................... –5V to 60V SS 2 37 FB

C/10, SHORT..............................................................15V PWM 3 36 VC

EN/UVLO, IVINP, IVINN, ISP, ISN...............................60V C/10 4 35 RT

5 34 SYNC
INTVCC, (BST1-SW1), (BST2-SW2)..............................6V SHORT
VREF 6 33 CLKOUT
CCM, SYNC, RT, CTRL, OVLO, PWM...........................6V
ISMON 7 32 CCM
IVINMON, ISMON, FB, SS, VC, VREF............................6V 8
IVINMON 31 PWMOUT
IVINP-IVINN, ISP-ISN, SNSP-SNSN........................±0.5V EN/UVLO 9 30 SGND
SNSP, SNSN............................................................±0.3V IVINP 10
39
29 TEST1
SGND
Operating Junction Temperature (Notes 2, 3) IVINN 11 28 SNSN
LT3790E/LT3790I............................... –40°C to 125°C VIN 12 27 SNSP
LT3790H............................................. –40°C to 150°C INTVCC 13 26 ISN
LT3790MP.......................................... –55°C to 150°C TG1 14 25 ISP
Storage Temperature Range................... –65°C to 150°C BST1 15 24 TG2

Lead Temperature (Soldering, 10 sec).................... 300°C SW1 16 23 NC

PGND 17 22 BST2
BG1 18 21 SW2
BG2 19 20 PGND

FE PACKAGE
38-LEAD PLASTIC TSSOP
θJA = 28°C/W
EXPOSED PAD (PIN 39) IS SGND, MUST BE SOLDERED TO PCB

ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LT3790EFE#PBF LT3790EFE#TRPBF LT3790FE 38-Lead Plastic TSSOP –40°C to 125°C
LT3790IFE#PBF LT3790IFE#TRPBF LT3790FE 38-Lead Plastic TSSOP –40°C to 125°C
LT3790HFE#PBF LT3790HFE#TRPBF LT3790FE 38-Lead Plastic TSSOP –40°C to 150°C
LT3790MPFE#PBF LT3790MPFE#TRPBF LT3790FE 38-Lead Plastic TSSOP –55°C to 150°C
Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.

ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = 12V, VEN/UVLO = 12V unless otherwise noted.
PARAMETER CONDITIONS MIN TYP MAX UNITS
Input
VIN Operating Voltage 4.7 60 V
VIN Shutdown IQ VEN/UVLO = 0V 0.1 1 µA
VIN Operating IQ (Not Switching) FB = 1.3V, RT = 59.0k 3.0 4 mA

Rev. B

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 LT3790
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = 12V, VEN/UVLO = 12V unless otherwise noted.
PARAMETER CONDITIONS MIN TYP MAX UNITS
Logic Inputs
EN/UVLO Falling Threshold l 1.16 1.2 1.24 V
EN/UVLO Rising Hysteresis 15 mV
EN/UVLO Input Low Voltage IVIN Drops Below 1µA 0.3 V
EN/UVLO Pin Bias Current Low VEN/UVLO = 1V 2 3 4 µA
EN/UVLO Pin Bias Current High VEN/UVLO = 1.6V 10 100 nA
CCM Threshold Voltage 0.3 1.5 V
CTRL Input Bias Current VCTRL = 1V 20 50 nA
CTRL Latch-Off Threshold Rising 10 50 95 mV
CTRL Latch-Off Hysteresis 13 mV
OVLO Rising Shutdown Voltage l 2.85 3 3.15 V
OVLO Falling Hysteresis 75 mV
Regulation
VREF Voltage l 1.96 2.00 2.04 V
VREF Line Regulation 4.7V < VIN < 60V 0.002 0.04 %/V
V(ISP-ISN) Threshold VCTRL = 2V, VISP = 12V/0.1V 58 60 62 mV
l 56 60 64 mV
VCTRL = 1V, VISP = 12V/0.1V 48 50 52 mV
l 46 50 54 mV
VCTRL = 600mV, VISP = 12V/0.1V 28 30 32 mV
l 26 30 34 mV
VCTRL = 100mV, VISP = 12V/0.1V 1 4.2 7.4 mV
l 0.2 4.2 8.2 mV
ISP Bias Current VISP = 12V, VISN = 11.9V 110 µA
ISN Bias Current VISP = 12V, VISN = 11.9V 20 µA
Output Current Sense Common Mode Range 0 60 V
Output Current Sense Amplifier gm 1650 µS
ISMON Monitor Voltage V(ISP-ISN) = 60mV l 1.14 1.2 1.26 V
Input Current Sense Threshold V(IVINP-IVINN) 3V ≤ VIVINP ≤ 60V l 46.5 50 54 mV
IVINP Bias Current VIVINP = VIVINN = 12V 90 µA
IVINN Bias Current VIVINP = VIVINN = 12V 20 µA
Input Current Sense Common Mode Range 3 60 V
Input Current Sense Amplifier gm 2.12 mS
IVINMON Monitor Voltage V(IVINP-IVINN) = 50mV l 0.96 1 1.04 V
FB Regulation Voltage 1.194 1.2 1.206 V
l 1.176 1.2 1.220 V
FB Line Regulation 4.7V < VIN < 60V 0.002 0.025 %/V
FB Amplifier gm 565 µS
FB Pin Input Bias Current FB in Regulation 100 200 nA
VC Standby Input Bias Current PWM = 0V –20 20 nA
VSENSE(MAX) (VSNSP-SNSN) Boost l 42 51 60 mV
Buck l –56 –47.5 –39 mV

Rev. B

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LT3790
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = 12V, VEN/UVLO = 12V unless otherwise noted.
PARAMETER CONDITIONS MIN TYP MAX UNITS
Fault
SS Pull-Up Current VSS = 0V 14 µA
SS Discharge Current 1.4 µA
C/10 Falling Threshold (V(ISP-ISN)) VFB = 1.2V 1 5 9 mV
SHORT Falling Threshold (VFB) 380 400 450 mV
C/10 Pin Output Impedance 1.1 2.0 kΩ
SHORT Pin Output Impedance 1.1 2.0 kΩ
SS Latch-Off Threshold 1.75 V
SS Reset Threshold 0.2 V
Oscillator
Switching Frequency RT = 147k 190 200 210 kHz
RT = 59.0k 380 400 420 kHz
RT = 29.1k 665 700 735 kHz
SYNC Frequency 200 700 kHz
SYNC Pin Resistance to GND 90 kΩ
SYNC Threshold Voltage 0.3 1.5 V
Internal VCC Regulator
INTVCC Regulation Voltage 4.8 5 5.2 V
Dropout (VIN – INTVCC) IINTVCC = –10mA, VIN = 5V 240 350 mV
INTVCC Undervoltage Lockout 3.1 3.5 3.9 V
INTVCC Current Limit VINTVCC = 4V 67 mA
PWM
PWM Threshold Voltage 0.3 1.5 V
PWM Pin Resistance to GND 90 kΩ
PWMOUT Pull-Up Resistance 10 20 Ω
PWMOUT Pull-Down Resistance 5 10 Ω
NMOS Drivers
TG1, TG2 Gate Driver On-Resistance VBST – VSW = 5V
Gate Pull-Up 2.6 Ω
Gate Pull-Down 1.7 Ω
BG1, BG2 Gate Driver On-Resistance VINTVCC = 5V
Gate Pull-Up 3 Ω
Gate Pull-Down 1.2 Ω
TG Off to BG On Delay CL = 3300pF 60 ns
BG Off to TG On Delay CL = 3300pF 60 ns
TG1, TG2, tOFF(MIN) RT = 59.0k 240 320 ns

Note 1: Stresses beyond those listed under Absolute Maximum Ratings operating junction temperature range. The LT3790MP is guaranteed to
may cause permanent damage to the device. Exposure to any Absolute meet performance specifications over the –55°C to 150°C operating
Maximum Rating condition for extended periods may affect device junction temperature range. High junction temperatures degrade operating
reliability and lifetime. lifetimes. Operating lifetime is derated for junction temperatures greater
Note 2: The LT3790E is guaranteed to meet performance from 0°C than 125°C.
to 125°C junction temperature. Specification over the -40°C to Note 3: The LT3790 includes overtemperature protection that is intended
125°C operating junction temperature range are assured by design, to protect the device during momentary overload conditions. Junction
characterization and correlation with statistical process controls. temperature will exceed the maximum operating junction temperature
The LT3790I is guaranteed to meet performance specifications over the when overtemperature protection is active. Continuous operation above
–40°C to 125°C operating junction temperature range. The LT3790H is the specified absolute maximum operating junction temperature may
guaranteed to meet performance specifications over the –40°C to 150°C impair device reliability.
Rev. B

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 LT3790
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted.

INTVCC Dropout Voltage INTVCC Current Limit

vs Current, Temperature INTVCC Voltage vs Temperature vs Temperature
2.5 5.20 90
TA = 150°C
TA = 25°C 5.15 80
2.0 TA = –50°C

INTVCC CURRENT LIMIT (mA)

70
5.10
60
VIN-VINTVCC (V)

1.5 5.05 VIN = 60V

INTVCC (V)
50
5.00
VIN = 12V 40
1.0
4.95
30
4.90 20
0.5
4.85 10

0 4.80 0
0 10 20 30 40 –50 –25 0 25 50 75 100 125 150 –50 –25 0 25 50 75 100 125 150
LDO CURRENT (mA) TEMPERATURE (°C) TEMPERATURE (°C)
3790 G01 3790 G02 3790 G03

INTVCC Load Regulation VREF Voltage vs Temperature VREF Load Regulation

6.00 2.04 2.20

5.75 2.03 2.15

5.50 2.02 2.10

5.25 2.01 2.05

INTVCC (V)

VREF (V)

5.00 2.00 VREF (V) 2.00

4.75 1.99 1.95

4.50 1.98 1.90

VIN = 60V
4.25 1.97 VIN = 12V 1.85
VIN = 4.7V
4.00 1.96 1.80
0 10 20 30 40 50 60 70 –50 –25 0 25 50 75 100 125 150 0 50 100 150 200 250 300 350 400
ILOAD (mA) TEMPERATURE (°C) IREF (µA)
3790 G04 3790 G05 3790 G06

V(ISP-ISN) Threshold
V(ISP-ISN) Threshold vs VCTRL V(ISP-ISN) Threshold vs VISP vs Temperature
70 70 70
VIN = 12V
68 68 VCTRL = 2V
60
66 66
50 64 64
V(ISP-ISN) (mV)
V(ISP-ISN) (mV)
V(ISP-ISN) (mV)

40 62 62
60 60
30
58 58

20 56 56
54 54 VISP = 60V
10 RISING 52 52 VISP = 12V
FALLING VISP = 0V
0 50 50
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0 10 20 30 40 50 60 –50 –25 0 25 50 75 100 125 150
VCTRL (V) VISP (V) TEMPERATURE (°C)
3790 G07 3790 G08 3790 G09

Rev. B

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LT3790
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted.

V(ISP-ISN) Threshold vs VFB ISMON Voltage vs Temperature ISMON Voltage vs V(ISP-ISN)

72 1.24 1.2
VIN = 12V
1.23 V(ISP-ISN) = 60mV
60 1.0
1.22
48 0.8
V(ISP-ISN) (mV)

1.21

VISMON (V)
VISMON (V)
36 1.20 0.6

1.19
24 0.4
1.18
12 0.2
1.17

0 1.16 0
1.17 1.18 1.19 1.20 1.21 1.22 1.23 –50 –25 0 25 50 75 100 125 150 0 10 20 30 40 50 60
VFB (V) TEMPERATURE (°C) V(ISP-ISN) (mV)
3790 G10 3790 G11 3790 G12

V(IVINP-IVINN) Threshold V(IVINP-IVINN) Threshold

vs Temperature vs VIVINP IVINMON Voltage vs Temperature
56 52.0 1.04
VIVINP = 12V
54 51.5 1.03 V(IVINP-VINN) = 50mV

51.0 1.02
52
V(IVINP-IVINN) (mV)

V(IVINP-IVINN) (mV)

VIVINP = 60V
50.5 1.01

VIVINMON (V)
50
VIVINP = 3V 50.0 1.00
48
49.5 0.99
46
49.0 0.98
44
48.5 0.97

42 48.0 0.96
–50 –25 0 25 50 75 100 125 150 0 10 20 30 40 50 60 –50 –25 0 25 50 75 100 125 150
TEMPERATURE (°C) VIVINP (V) TEMPERATURE (°C)
3790 G13 3790 G14 3790 G15

FB Regulation Voltage SHORT Threshold

V(IVINP-IVINN) Threshold vs VFB vs Temperature vs Temperature
60 1.24 0.500

1.23 0.475
50
1.22 0.450
V(IVINP-IVINSN) (mV)

40
FB VOLTAGE (V)

1.21 0.425 RISING

VFB (V)

30 1.20 0.400
FALLING
1.19 0.375
20
1.18 0.350
10 VIN = 60V
1.17 VIN = 12V 0.325
VIN = 4.7V
0 1.16 0.300
1.17 1.18 1.19 1.20 1.21 1.22 1.23 –50 –25 0 25 50 75 100 125 150 –50 –25 0 25 50 75 100 125 150
VFB (V) TEMPERATURE (°C) TEMPERATURE (°C)
3790 G16 3790 G17 3790 G18

Rev. B

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 LT3790
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted.

OVLO Threshold vs Temperature Soft-Start Current vs Temperature Supply Current vs Input Voltage
3.3 16 4.0

3.2 14 CHARGING 3.5

3.1 12 3.0
OVLO THRESHOLD (V)

RISING
3.0 10 2.5

ISS (µA)

IQ (mA)
2.9 FALLING 8 2.0

2.8 6 1.5

2.7 4 1.0
DISCHARGING TA = 150°C
2.6 2 0.5 TA = 25°C
TA = –50°C
2.5 0 0
–50 –25 0 25 50 75 100 125 150 –50 –25 0 25 50 75 100 125 150 0 10 20 30 40 50 60
TEMPERATURE (°C) TEMPERATURE (°C) VIN (V)
3790 G20 3790 G21 3790 G22

Oscillator Frequency
EN/UVLO Pin Current EN/UVLO Threshold Voltage vs Temperature
8 1.30 800
VEN/UVLO = 1V
1.28
7 700
RT = 29.1k

SWITCHING FREQUENCY (kHz)

1.26
EN/UVLO PIN CURRENT (µA)

6 600
EN/UVLO THRESHOLD (V)

1.24
5 1.22 500
RISING RT = 59.0k
4 1.20 400
1.18
3 FALLING 300
1.16 RT = 147k
2 200
1.14
1 1.12 100

0 1.10 0
–50 –25 0 25 50 75 100 125 150 –50 –25 0 25 50 75 100 125 150 –50 –25 0 25 50 75 100 125 150
TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C)
3790 G23 3790 G24 3790 G25

TG1, TG2 Minimum On-Time TG1, TG2 Minimum Off-Time V(BST1-SW1), V(BST2-SW2) UVLO
vs Temperature vs Temperature vs Temperature
100 350 3.9
TG2
90 300 3.8
TG1, TG2 MINIMUM OFF-TIME (ns)
TG1, TG2 MINIMUM ON-TIME (ns)

fSW = 200kHz
RISING
V(BST1-SW1), V(BST2-SW2) (V)

80 TG1 3.7
250
fSW = 400kHz
70 3.6
200
60 3.5
fSW = 700kHz
150
50 3.4
100 FALLING
40 3.3

30 50 3.2

20 0 3.1
–50 –25 0 25 50 75 100 125 150 –50 –25 0 25 50 75
100 125 150 –50 –25 0 25 50 75 100 125 150
TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C)
3790 G26 3790 G27 3790 G28

Rev. B

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LT3790
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted.

BG1, BG2 Driver On-Resistance TG1, TG2 Driver On-Resistance PWMOUT On-Resistance
vs Temperature vs Temperature vs Temperature
4.5 4.0 14

4.0 3.5 12
3.5 PULL-UP
BG1, BG2 RESISTANCE (Ω)

TG1, TG2 RESISTANCE (Ω)

PWMOUT RESISTANCE (Ω)

3.0 PULL-UP
10 PULL-UP
3.0
2.5
2.5 8
PULL-DOWN
2.0
2.0 6 PULL-DOWN
PULL-DOWN 1.5
1.5
4
1.0
1.0
0.5 2
0.5

0 0 0
–50 –25 0 25 50 75 100 125 150 –50 –25 0 25 50 75 100 125 150 –50 –25 0 25 50 75 100 125 150
TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C)
3790 G29 3790 G30 3790 G31

V(SNSP-SNSN) Buck Threshold V(SNSP-SNSN) Buck Threshold

VC Voltage vs Duty Cycle vs VC vs Temperature
1.6 60 60
V(SNSP-SNSN) = 0V
1.4 VC(MIN)
40 40

V(SNSP-SNSN) THRESHOLD (mV)

BG2
1.2
V(SNSP-SNSN) (mV)

20 20
1.0
BG1
VC (V)

0.8 0 0

0.6
–20 –20
0.4
–40 –40 VC(MAX)
0.2

0 –60 –60
0 20 40 60 80 100 0.6 0.8 1.0 1.2 1.4 1.6 1.8 –50 –25 0 25 50 75 100 125 150
DUTY CYCLE (%) VC (V) TEMPERATURE (°C)
3790 G32 3790 G33 3790 G34

V(SNSP-SNSN) Boost Threshold V(SNSP-SNSN) Boost Threshold

vs VC vs Temperature
60 60

VC(MAX)
40 40
V(SNSP-SNSN) THRESHOLD (mV)

20 20
V(SNSP-SNSN) (mV)

0 0

–20 –20

–40 –40

–60 –60 VC(MIN)

–80 –80
0.6 0.8 1.0 1.2 1.4 1.6 1.8 –50 –25 0 25 50 75 100 125 150
VC (V) TEMPERATURE (°C)
3790 G35 3790 G36

Rev. B

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 LT3790
PIN FUNCTIONS
CTRL (Pin 1): Output Current Sense Threshold Adjustment IVINMON (Pin 8): Monitor pin that produces a voltage
Pin. Regulating threshold V(ISP-ISN) is 1/20th of VCTRL. that is twenty times the voltage V(IVINP-IVINN). IVINMON
CTRL linear range is from 0V to 1.1V. For VCTRL > 1.3V, will equal 1V when V(IVINP-IVINN) = 50mV.
the current sense threshold is constant at the full-scale EN/UVLO (Pin 9): Enable Control Pin. Forcing an accurate
value of 60mV. For 1.1V < VCTRL < 1.3V, the dependence of 1.2V falling threshold with an externally programmable
the current sense threshold upon VCTRL transitions from hysteresis is generated by the external resistor divider
a linear function to a constant value, reaching 98% of full and a 3µA pull-down current. Above the 1.2V (typical)
scale by VCTRL = 1.2V. Connect CTRL to VREF for the 60mV threshold (but below 6V), EN/UVLO input bias current is
default threshold. Force less than 50mV (typical) to stop sub-µA. Below the falling threshold, a 3µA pull-down cur-
switching. Do not leave this pin open. rent is enabled so the user can define the hysteresis with
SS (Pin 2): Soft-start reduces the input power sources the external resistor selection. An undervoltage condition
surge current by gradually increasing the controller’s cur- resets soft-start. Tie to 0.3V, or less, to disable the device
rent limit. A minimum value of 22nF is recommended on and reduce VIN quiescent current below 1µA.
this pin. A 100k resistor must be placed between SS and IVINP (Pin 10): Positive Input for the Input Current Limit
VREF for the LT3790. and Monitor. Input bias current for this pin is typically
PWM (Pin 3): A signal low turns off switches, idles 90µA.
switching and disconnects the VC pin from all external IVINN (Pin 11): Negative Input for the Input Current Limit
loads. The PWMOUT pin follows the PWM pin. PWM has and Monitor. The input bias current for this pin is typically
an internal 90k pull-down resistor. If not used, connect 20µA.
to INTVCC.
VIN (Pin 12): Main Input Supply. Bypass this pin to PGND
C/10 (Pin 4): C/10 Charge Termination Pin. An open-drain with a capacitor.
pull-down on C/10 asserts if V(ISP-ISN) is less than 5mV
(typical). To function, the pin requires an external pull-up INTVCC (Pin 13): Internal 5V Regulator Output. The driver
resistor. and control circuits are powered from this voltage. Bypass
this pin to PGND with a minimum 4.7µF ceramic capacitor.
SHORT (Pin 5): Output Shorted Pin. An open-drain
pull-down on SHORT asserts if FB is less than 400mV TG1 (Pin 14): Top Gate Drive. Drives the top N-channel
(typical) and V(ISP-ISN) is larger than 5mV (typical). To MOSFET with a voltage equal to INTVCC superimposed on
function, the pin requires an external pull-up resistor. the switch node voltage SW1.
VREF (Pin 6): Voltage Reference Output Pin, Typically 2V. BST1 (Pin 15): Bootstrapped Driver Supply. The BST1 pin
This pin drives a resistor divider for the CTRL pin, either swings from a diode voltage below INTVCC up to a diode
for output current adjustment or for temperature limit/ voltage below VIN + INTVCC.
compensation of the output load. Can supply up to 200µA SW1 (Pin 16): Switch Node. SW1 pin swings from a diode
of current. voltage drop below ground up to VIN.
ISMON (Pin 7): Monitor pin that produces a voltage that PGND (Pins 17, 20): Power Ground. Connect these pins
is twenty times the voltage V(ISP-ISN). ISMON will equal closely to the source of the bottom N-channel MOSFET.
1.2V when V(ISP-ISN) = 60mV. For parallel applications,
tie master LT3790 ISMON pin to slave LT3790 CTRL pin. BG1 (Pin 18): Bottom Gate Drive. Drives the gate of the
bottom N-channel MOSFET between ground and INTVCC.

Rev. B

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LT3790
PIN FUNCTIONS
BG2 (Pin 19): Bottom Gate Drive. Drives the gate of the frequency forced continuous conduction mode and allows
bottom N-channel MOSFET between ground and INTVCC. the inductor current to flow negative. When the pin volt-
age is less than 0.3V, the part runs in discontinuous con-
SW2 (Pin 21): Switch Node. SW2 pin swings from a diode
duction mode and does not allow the inductor current to
voltage drop below ground up to VOUT.
flow backward. This pin is only meant to block inductor
BST2 (Pin 22): Bootstrapped Driver Supply. The BST2 pin reverse current, and should only be pulled low when the
swings from a diode voltage below INTVCC up to a diode output current is low. This pin must be either connected to
voltage below VOUT + INTVCC. INTVCC (pin 13) for continuous conduction mode across
NC (Pin 23): No Connect Pin. Leave this pin floating. all loads, or it must be connected to the C/10 (pin 4) with
a pull-up resistor to INTVCC for continuous conduction
TG2 (Pin 24): Top Gate Drive. Drives the top N-channel mode at heavy load and for discontinuous conduction
MOSFET with a voltage equal to INTVCC superimposed on mode at light load.
the switch node voltage SW2.
CLKOUT (Pin 33): Clock Output Pin. A 180° out-of-phase
ISP (Pin 25): Connection Point for the Positive Terminal clock is provided at the oscillator frequency to allow
of the Output Current Feedback Resistor. for paralleling two devices for extending output power
ISN (Pin 26): Connection Point for the Negative Terminal capability.
of the Output Current Feedback Resistor. SYNC (Pin 34): External Synchronization Input Pin. This
SNSP (Pin 27): The Positive Input to the Current Sense pin is internally terminated to GND with a 90k resistor.
Comparator. The VC pin voltage and controlled offsets The internal buck clock is synchronized to the rising edge
between the SNSP and SNSN pins, in conjunction with a of the SYNC signal while the internal boost clock is 180°
resistor, set the current trip threshold. phase shifted.
SNSN (Pin 28): The Negative Input to the Current Sense RT (Pin 35): Frequency Set Pin. Place a resistor to GND
Comparator. to set the internal frequency. The range of oscillation is
200kHz to 700kHz.
TEST1 (Pin 29): This pin is used for testing purposes only
and must be connected to SGND for the part to operate VC (Pin 36): Current Control Threshold and Error Amplifier
properly. Compensation Point. The current comparator threshold
increases with this control voltage. The voltage ranges
SGND (Pin 30, Exposed Pad Pin 39): Signal Ground.
from 0.7V to 1.9V.
All small-signal components and compensation should
connect to this ground, which should be connected to FB (Pin 37): Voltage Loop Feedback Pin. FB is intended
PGND at a single point. Solder the exposed pad directly for constant-voltage regulation. The internal transcon-
to the ground plane. ductance amplifier with output VC will regulate FB to 1.2V
(typical) through the DC/DC converter.
PWMOUT (Pin 31): Buffered Version of PWM Signal for
Driving Output Load Disconnect N-Channel MOSFET. The OVLO (Pin 38): Overvoltage Input Pin. This pin is used for
PWMOUT pin is driven from INTVCC. Use of a MOSFET OVLO, if OVLO > 3V then SS is pulled low, the part stops
with a gate cutoff voltage higher than 1V is recommended. switching and resets. Do not leave this pin open.
CCM (Pin 32): Continuous Conduction Mode Pin. When
the pin voltage is higher than 1.5V, the part runs in fixed

Rev. B

10 For more information www.analog.com

 LT3790
BLOCK DIAGRAM
25 26 10 11 12 6 13
ISP ISN IVINP IVINN VIN VREF INTVCC
+ – + –
A2 A1
SHDN_INT REGS
A = 20 A = 20 A = 20 A = 24

ISMON
7
ISMON_INT IVINMON_INT TSD BST1
+ 15
IVINMON A13 TG1
8 A3 14
SW1
EN/UVLO – 16
9 –
3µA A4 SHDN_INT SHDN_INT BUCK
LOGIC
1.2V + SS_RESET
SS LATCH INTVCC
PWM
A14 BG1
18
CCM PGND
32 17
A15 BG2
OSC 19
SLOPE_COMP_BUCK

INTVCC
RT
35
BOOST
SYNC LOGIC
34

CLKOUT SW2
33 + 21
A16 TG2
A7 24
SLOPE_COMP_BOOST BST2
– 22
SNSP
+ 27
A10
SNSN
SHORT + 0.4V – 28
5
A5
– IVINMON_INT
– FB FB
A11 – 37
VREF +
+ 0.2V
+ 0.1V A8 1.2V
C/10 14µA
4 A6
–
– ISMON_INT
+
CTRL
A12 + 1
SS RESET
R + – ISMON_INT
Q SS LATCH
S A9

– 1.75V

+ 3V
INTVCC
A18
PWM A17 1.4µA OVLO
3 – 38
SGND
PWMOUT 30, 39 SS VC
31 2 36 3790 BD

Rev. B

For more information www.analog.com 11

LT3790
OPERATION
The LT3790 is a current mode controller that provides slowly charged during start-up. This soft-start clamping
an output voltage above, equal to or below the input volt- prevents abrupt current from being drawn from the input
age. The LTC proprietary topology and control architecture power supply.
uses a current sensing resistor in buck or boost operation. The top MOSFET drivers are biased from floating boot-
The sensed inductor current is controlled by the voltage strap capacitors C1 and C2, which are normally recharged
on the VC pin, which is the output of the feedback amplifi- through an external diode when the top MOSFET is turned
ers A11 and A12. The VC pin is controlled by three inputs, off. A unique charge sharing technique eliminates top
one input from the output current loop, one input from the FET refresh switching cycle in buck or boost operation.
input current loop, and the third input from the feedback Schottky diodes across the synchronous switch M4 and
loop. Whichever feedback input is higher takes prece- synchronous switch M2 are not required, but they do
dence, forcing the converter into either a constant-current provide a lower drop during the dead time. The addition
or a constant-voltage mode. of the Schottky diode typically improves peak efficiency
The LT3790 is designed to transition cleanly between by 1% to 2% at 500kHz.
the two modes of operation. Current sense amplifier A1
Power Switch Control
senses the voltage between the IVINP and IVINN pins and
provides a pre-gain to amplifier A11. When the voltage Figure 1 shows a simplified diagram of how the four
between IVINP and IVINN reaches 50mV, the output of A1 power switches are connected to the inductor, VIN, VOUT
provides IVINMON_INT to the inverting input of A11 and and GND. Figure 2 shows the regions of operation for the
the converter is in constant-current mode. If the current LT3790 as a function of duty cycle D. The power switches
sense voltage exceeds 50mV, the output of A1 increases are properly controlled so the transfer between regions is
causing the output of A11 to decrease, thus reducing the continuous. When VIN approaches VOUT, the buck-boost
amount of current delivered to the output. In this manner region is reached.
the current sense voltage is regulated to 50mV. VIN VOUT

The output current amplifier works similar to the input TG1 M1 M4 TG2
current amplifier but with a 60mV voltage instead of L1
50mV. The output current sense level is also adjustable SW1 SW2

by the CTRL pin. Forcing CTRL to less than 1.2V forces BG1 M2 M3 BG2
ISMON_INT to the same level as CTRL, thus providing
current-level control. The output current amplifier pro- RSENSE
vides rail-to-rail operation. Similarly if the FB pin goes 3790 F01

above 1.2V the output of A11 decreases to reduce the

Figure 1. Simplified Diagram of the Output Switches
current level and regulate the output (constant-voltage
mode).
DMAX
The LT3790 provides monitoring pins IVINMON and BOOST
(BG2) M1 ON, M2 OFF
ISMON that are proportional to the voltage across the BOOST REGION PWM M3, M4 SWITCHES
DMIN
input and output current amplifiers respectively. BOOST
BUCK-BOOST REGION 4-SWITCH PWM
DMAX
The main control loop is shut down by pulling the EN/ BUCK
(TG1) M4 ON, M3 OFF
UVLO pin low. When the EN/UVLO pin is higher than 1.2V, BUCK REGION PWM M2, M1 SWITCHES
DMIN
an internal 14µA current source charges soft-start capac- BUCK 3790 F02

itor CSS at the SS pin. The VC voltage is then clamped a

Figure 2. Operating Regions vs Duty Cycle
diode voltage higher than the SS voltage while the CSS is

Rev. B

12 For more information www.analog.com

 LT3790
OPERATION
Buck Region (VIN > VOUT) The duty cycle of switch M3 decreases until the minimum
duty cycle of the converter in boost operation reaches
Switch M4 is always on and switch M3 is always off during
DMIN(BOOST,BG2), given by:
this mode. At the start of every cycle, synchronous switch
M2 is turned on first. Inductor current is sensed when DMIN(BOOST,BG2) = D(BUCK-BOOST)
synchronous switch M2 is turned on. After the sensed where D(BUCK-BOOST) is the duty cycle of the buck-boost
inductor current falls below the reference voltage, which switch range:
is proportional to VC, synchronous switch M2 is turned off
and switch M1 is turned on for the remainder of the cycle. D(BUCK-BOOST) = 8%
Switches M1 and M2 will alternate, behaving like a typical Figure 6 shows typical boost operation waveforms. If VIN
synchronous buck regulator. The duty cycle of switch M1 approaches VOUT, the buck-boost region is reached.
increases until the maximum duty cycle of the converter
in buck operation reaches DMAX(BUCK, TG1), given by: Low Current Operation
DMAX(BUCK,TG1) = 100% – D(BUCK-BOOST) The LT3790 is recommended to run in forced continuous
where D(BUCK-BOOST) is the duty cycle of the buck-boost conduction mode at heavy load by pulling the CCM pin
switch range: higher than 1.5V. In this mode the controller behaves as
a continuous, PWM current mode synchronous switching
D(BUCK-BOOST) = 8% regulator. In boost operation, switch M1 is always on,
Figure 3 shows typical buck operation waveforms. If VIN switch M3 and synchronous switch M4 are alternately
approaches VOUT, the buck-boost region is reached. turned on to maintain the output voltage independent of
the direction of inductor current. In buck operation, syn-
Buck-Boost Region (VIN ~ VOUT) chronous switch M4 is always on, switch M1 and syn-
When VIN is close to VOUT, the controller is in buck-boost chronous switch M2 are alternately turned on to maintain
operation. Figure 4 and Figure 5 show typical waveforms the output voltage independent of the direction of inductor
current. In the forced continuous mode, the output can
in this operation. Every cycle the controller turns on
source or sink current.
switches M2 and M4, then M1 and M4 are turned on
until 180° later when switches M1 and M3 turn on, and However, reverse inductor current from the output to the
then switches M1 and M4 are turned on for the remainder input is not desired for certain applications. For these
of the cycle. applications, the CCM pin must be connected to C/10 (pin
4) with a pull-up resistor to INTVCC (see front page Typical
Boost Region (VIN < VOUT) Application). Therefore, the CCM pin will be pulled lower
Switch M1 is always on and synchronous switch M2 is than 0.3V for discontinuous conduction mode by the C/10
always off in boost operation. Every cycle switch M3 is pin when the output current is low. In this mode, switch
turned on first. Inductor current is sensed when synchro- M4 turns off when the inductor current flows negative.
nous switch M3 is turned on. After the sensed inductor
current exceeds the reference voltage which is propor-
tional to VC, switch M3 turns off and synchronous switch
M4 is turned on for the remainder of the cycle. Switches
M3 and M4 alternate, behaving like a typical synchronous
boost regulator.

Rev. B

For more information www.analog.com 13

LT3790
OPERATION
M2 + M4 M2 + M4 M2 + M4
M1 + M4 M1 + M4 M1 + M4

3790 F03

Figure 3. Buck Operation (VIN > VOUT)

M1 + M4 M1 + M4 M1 + M4
M2 + M4 M2 + M4 M2 + M4
M1+ M3 M1+ M3 M1+ M3
M1 + M4 M1 + M4 M1 + M4

3790 F04

Figure 4. Buck-Boost Operation (VIN ≤ VOUT)

M1 + M4 M1 + M4 M1 + M4
M2 + M4 M2 + M4 M2 + M4
M1 + M3 M1 + M3 M1 + M3
M1 + M4 M1 + M4 M1 + M4

3790 F05

Figure 5. Buck-Boost Operation (VIN ≥ VOUT)

M1 + M3 M1 + M3 M1 + M3
M1 + M4 M1 + M4 M1 + M4

3790 F06

Figure 6. Boost Operation (VIN < VOUT)

Rev. B

14 For more information www.analog.com

 LT3790
APPLICATIONS INFORMATION
The Typical Application on the front page is a basic LT3790 200

application circuit. External component selection is driven 180

by the load requirement, and begins with the selection of 160

RSENSE and the inductor value. Next, the power MOSFETs 140

∆IL/ISENSE(MAX) (%)
BOOST ∆IL/
120
are selected. Finally, CIN and COUT are selected. This cir- ISENSE(MAX) LIMIT
100
cuit can operate up to an input voltage of 60V.
80
60 BUCK ∆IL/
Programming The Switching Frequency ISENSE(MAX) LIMIT
40
The RT frequency adjust pin allows the user to program 20
the switching frequency from 200kHz to 700kHz to opti- 0
50 55 60 65 70 75 80 85 90 95 100
mize efficiency/performance or external component size. BG1, BG2 DUTY CYCLE (%)
Higher frequency operation yields smaller component 3790 F07

size but increases switching losses and gate driving Figure 7. Maximum Peak-to-Peak Ripple vs Duty Cycle
current, and may not allow sufficiently high or low duty
cycle operation. Lower frequency operation gives better value has a direct effect on ripple current. The maximum
performance at the cost of larger external component inductor current ripple ΔIL can be seen in Figure 7. This is
size. For an appropriate RT resistor value see Table 1. the maximum ripple that will prevent subharmonic oscil-
An external resistor from the RT pin to GND is required; lation and also regulate with zero load. The ripple should
do not leave this pin open. be less than this to allow proper operation over all load
Table 1. Switching Frequency vs RT Value currents. For a given ripple the inductance terms in con-
fOSC (kHz) RT (kΩ)
tinuous mode are as follows:
200
300
147
84.5 LBUCK >
(
VOUT • VIN(MAX) – VOUT • 100 )
400 59.0
f •IOUT(MAX) • %Ripple • VIN(MAX)
500
600
45.3
35.7 LBOOST >
(
VIN(MIN)2 • VOUT – VIN(MIN) • 100 )
700 29.4
f •IOUT(MAX) • %Ripple • VOUT2

Frequency Synchronization where:

The LT3790 switching frequency can be synchronized to f is operating frequency

an external clock using the SYNC pin. Driving SYNC with a % ripple is allowable inductor current ripple
50% duty cycle waveform is always a good choice, other- VIN(MIN) is minimum input voltage
wise maintain the duty cycle between 10% and 90%. The VIN(MAX) is maximum input voltage
falling edge of CLKOUT corresponds to the rising edge of
VOUT is output voltage
SYNC thus allowing 2-phase paralleling converters. The
rising edge of CLKOUT turns on switch M3 and the falling IOUT(MAX) is maximum output load current
edge of CLKOUT turns on switch M2. For high efficiency, choose an inductor with low core
loss. Also, the inductor should have low DC resistance to
Inductor Selection reduce the I2R losses, and must be able to handle the peak
The operating frequency and inductor selection are inter- inductor current without saturating. To minimize radiated
related in that higher operating frequencies allow the use noise, use a shielded inductor.
of smaller inductor and capacitor values. The inductor
Rev. B

For more information www.analog.com 15

LT3790
APPLICATIONS INFORMATION
RSENSE Selection and Maximum Output Current The formula has a maximum at VIN = 2VOUT. Note that
RSENSE is chosen based on the required output current. The ripple current ratings from capacitor manufacturers are
current comparator threshold sets the peak of the induc- often based on only 2000 hours of life which makes it
tor current in boost operation and the maximum inductor advisable to derate the capacitor.
valley current in buck operation. In boost operation, the In boost operation, the discontinuous current shifts from
maximum average load current at VIN(MIN) is: the input to the output, so COUT must be capable of reduc-
⎛ 51mV ΔIL ⎞ VIN(MIN) ing the output voltage ripple. The effects of ESR (equiva-
IOUT(MAX _BOOST) = ⎜ – • lent series resistance) and the bulk capacitance must be
⎝ RSENSE 2 ⎟⎠ VOUT
considered when choosing the right capacitor for a given
output ripple voltage. The steady ripple due to charging
where ΔIL is peak-to-peak inductor ripple current. In buck
and discharging the bulk capacitance is given by:
operation, the maximum average load current is:
⎛ 47.5mV ΔIL ⎞
ΔVRIPPLE (BOOST _CAP ) =
(
IOUT • VOUT – VIN(MIN) )
IOUT(MAX _BUCK) = ⎜ +
⎝ RSENSE 2 ⎟⎠ COUT • VOUT • f
ΔIL
The maximum current sensing RSENSE value for the boost ΔVRIPPLE (BUCK _CAP ) ≈
8 • f • COUT
operation is:
2 • 51mV • VIN(MIN) where COUT is the output filter capacitor.
RSENSE(MAX) = The steady ripple due to the voltage drop across the ESR
2 •IOUT • VOUT + ΔIL(BOOST) • VIN(MIN)
is given by:
The maximum current sensing RSENSE value for the buck ΔVBOOST(ESR) = IOUT • ESR
operation is:
ΔVBUCK(ESR) = IOUT • ESR
2 • 47.5mV
RSENSE(MAX) = Multiple capacitors placed in parallel may be needed to
2 •IOUT – ΔIL(BUCK)
meet the ESR and RMS current handling requirements.
Output capacitors are also used for stability for the
The final RSENSE value should be lower than the calculated
RSENSE(MAX) in both the boost and buck operation. A 20% LT3790. A good starting point for output capacitors is
to 30% margin is usually recommended. seen in the Typical Applications circuits. Ceramic capaci-
tors have excellent low ESR characteristics but can have
CIN and COUT Selection a high voltage coefficient and are recommended for
applications less than 100W. Capacitors available with
In boost operation, input current is continuous. In buck
low ESR and high ripple current ratings, such as OS-CON
operation, input current is discontinuous. In buck opera-
and POSCAP may be needed for applications greater than
tion, the selection of input capacitor, CIN, is driven by the
100W.
need to filter the input square wave current. Use a low
ESR capacitor sized to handle the maximum RMS current.
For buck operation, the input RMS current is given by:
ΔIL2
IRMS = IOUT2 • D + •D
12

Rev. B

16 For more information www.analog.com

 LT3790
APPLICATIONS INFORMATION
Programming VIN UVLO and OVLO When the CTRL pin voltage is between 1.1V and 1.3V the
output current varies with VCTRL, but departs from the
The falling UVLO value can be accurately set by the resis-
equation above by an increasing amount as VCTRL volt-
tor divider R1 and R2. A small 3µA pull-down current is
active when the EN/UVLO is below the threshold. The age increases. Ultimately, when VCTRL > 1.3V the output
purpose of this current is to allow the user to program current no longer varies. The typical V(ISP-ISN) threshold
the rising hysteresis. The following equations should be vs VCTRL is listed in Table 2.
used to determine the resistor values: Table 2. V(ISP-ISN) Threshold vs CTRL
R1+ R2 VCTRL (V) V(ISP-ISN) (mV)
VIN(UVLO–) = 1.2 • 1.1 54.6
R2
1.15 57
R1+ R2
VIN(UVLO+ ) = 3µA • R1+ 1.215 • 1.2 58.8
R2
1.25 59.7
The rising OVLO value can be accurately set by the resis- 1.3 60
tor divider R3 and R4. The following equations should be
used to determine the resistor values: When VCTRL is higher than 1.3V, the output current is
R3 + R4 regulated to:
VIN(OVLO+ ) = 3 •
R4 60mV
IOUT =
R3 + R4 ROUT
VIN(OVLO–) = 2.925 •
R4
The CTRL pin should not be left open (tie to VREF if not
VIN
used). The CTRL pin can also be used in conjunction with
R1 R3
a thermistor to provide overtemperature protection for
LT3790
OVLO
the output load, or with a resistor divider to VIN to reduce
EN/UVLO output power and switching current when VIN is low. The
R2 R4 presence of a time varying differential voltage signal (rip-
3790 F08 ple) across ISP and ISN at the switching frequency is
Figure 8. Resistor Connection to Set VIN UVLO
expected. The amplitude of this signal is increased by
and OVLO Thresholds high output load current, low switching frequency and/
or a smaller value output filter capacitor. Some level of
Programming Output Current ripple signal is acceptable: the compensation capacitor
on the VC pin filters the signal so the average difference
The output current is programmed by placing an appro- between ISP and ISN is regulated to the user-programmed
priate value current sense resistor, ROUT, in series with value. Ripple voltage amplitude (peak-to-peak) in excess
the output load. The voltage drop across ROUT is (Kelvin) of 20mV should not cause mis-operation, but may lead
sensed by the ISP and ISN pins. The CTRL pin should to noticeable offset between the average value and the
be tied to a voltage higher than 1.2V to get the full-scale user-programmed value.
60mV (typical) threshold across the sense resistor. The
CTRL pin can also be used to adjust the output current, ISMON
although relative accuracy decreases with the decreasing
sense threshold. When the CTRL pin voltage is less than The ISMON pin provides a linear indication of the current
1.1V, the output current is: flowing through the output. The equation for VISMON is
V(ISP–ISN) • 20. This pin is suitable for driving an ADC
VCTRL
IOUT = input, however, the output impedance of this pin is 12.5kΩ
ROUT • 20 so care must be taken not to load this pin.
Rev. B

For more information www.analog.com 17

LT3790
APPLICATIONS INFORMATION
Programming Input Current Limit Dimming Control
The LT3790 has a standalone current sense amplifier. It There are two methods to control the current source for
can be used to limit the input current. The input current dimming using the LT3790. One method uses the CTRL
limit is calculated by the following equation: pin to adjust the current regulated in the output. A sec-
50mV ond method uses the PWM pin to modulate the current
IIN = source between zero and full current to achieve a precisely
RIN
programmed average current. To make PWM dimming
For loop stability a lowpass RC filter is needed. For more accurate, the switch demand current is stored on
most applications, a 50Ω resistor and 470nF capacitor the VC node during the quiescent phase when PWM is
is sufficient. low. This feature minimizes recovery time when the PWM
signal goes high. To further improve the recovery time a
Table 3.
RIN (mΩ) ILIMIT (A)
disconnect switch may be used in the output current path
20 2.5
to prevent the ISP node from discharging during the PWM
15 3.3 signal low phase. The minimum PWM on- or off-time is
12 4.2 affected by choice of operating frequency and external
10 5.0 component selection. The best overall combination of
6 8.3 PWM and analog dimming capabilities is available if the
5 10.0 minimum PWM pulse is at least six switching cycles and
4 12.5 the PWM pulse is synchronized to the SYNC signal.
3 16.7
2 25 SHORT Pin
The LT3790 provides an open-drain status pin,
IVINMON
SHORT, which pulls low when the FB pin is below
The IVINMON pin provides a linear indication of the cur- 400mV and V(ISP-ISN) is above 5mV. The only time the
rent flowing through the input. The equation for VIVINMON FB pin will be below 400mV is during start-up or if the
is V(IVINP-IVINN) • 20. This pin is suitable for driving an output is shorted. During start-up the LT3790 ignores
ADC input, however, the output impedance of this pin is the voltage on the FB pin until the soft-start capacitor
12.5kΩ so care must be taken not to load this pin. reaches 1.75V. To prevent false tripping after startup, a
large enough soft-start capacitor must be used to allow
Programming Output Voltage (Constant Voltage
the output to get up to approximately 40% to 50% of
Regulation)
the final value.
For a voltage regulator, the output voltage can be set by
selecting the values of R5 and R6 (see Figure 9) according C/10 Pin
to the following equation:
The LT3790 provides an open-drain status pin, C/10,
R5 + R6 which pulls low when the voltage across V(ISP-ISN) is less
VOUT = 1.2 •
R6 than 5mV. For battery charger applications with output
VOUT
current sense and limit, the C/10 provides a C/10 charge
LT3790 R5 termination flag.
FB
R6 Soft-Start
3790 F09
Soft-start reduces the input power sources’ surge cur-
Figure 9. Resistor Connection for Constant Output rents by gradually increasing the controller’s current limit
Voltage Regulation
Rev. B

18 For more information www.analog.com

 LT3790
APPLICATIONS INFORMATION
(proportional to an internally buffered clamped equivalent In order to select the power MOSFETs, the power dissi-
of VC). The soft-start interval is set by the soft-start capac- pated by the device must be known. For switch M1, the
itor selection according to the following equation maximum power dissipation happens in boost operation,
1.2V when it remains on all the time. Its maximum power dis-
tSS = •C sipation at maximum output current is given by:
14µA SS
2
⎛I •V ⎞
A 100k resistor must be placed between SS and VREF for PM1(BOOST) = ⎜ OUT OUT ⎟ • ρT • RDS(ON)
the LT3790. This 100k resistor also contributes the extra ⎝ VIN ⎠
SS charge current. Make sure CSS is large enough when
where ρT is a normalization factor (unity at 25°C)
there is loading during start-up.
accounting for the significant variation in on-resistance
Loop Compensation with temperature, typically 0.4%/°C as shown in Figure 10.
For a maximum junction temperature of 125°C, using a
The LT3790 uses an internal transconductance error value of ρT = 1.5 is reasonable.
amplifier whose VC output compensates the control loop.
The external inductor, output capacitor and the compen- Switch M2 operates in buck operation as the synchronous
sation resistor and capacitor determine the loop stability. rectifier. Its power dissipation at maximum output current
is given by:
The inductor and output capacitor are chosen based on
performance, size and cost. The compensation resis- VIN – VOUT
PM2(BUCK) = •IOUT2 • ρT • RDS(ON)
tor and capacitor at VC are set to optimize control loop VIN
response and stability. For typical applications, a 22nF Switch M3 operates in boost operation as the control
or higher compensation capacitor at VC is needed, and switch. Its power dissipation at maximum current is given
a series resistor should always be used to increase the by:
slew rate on the VC pin to maintain tighter regulation of
output current during fast transients on the input supply
PM3(BOOST) =
( VOUT – VIN ) • VOUT •I 2 • ρT • RDS(ON)
of the converter. OUT
VIN2
Power MOSFET Selections and Efficiency IOUT
+ k • VOUT3 • •C •f
Considerations VIN RSS
The LT3790 requires four external N-channel power where CRSS is usually specified by the MOSFET manufac-
MOSFETs, two for the top switches (switch M1 and M4, turers. The constant k, which accounts for the loss caused
shown in Figure 1) and two for the bottom switches by reverse-recovery current, is inversely proportional to
(switch M2 and M3 shown in Figure 1). Important param- the gate drive current and has an empirical value of 1.7.
eters for the power MOSFETs are the breakdown volt- For switch M4, the maximum power dissipation happens
age, VBR(DSS), threshold voltage, VGS(TH), on-resistance, in boost operation, when its duty cycle is higher than
RDS(ON), reverse transfer capacitance, CRSS, and maxi- 50%. Its maximum power dissipation at maximum output
mum current, IDS(MAX). current is given by:
The drive voltage is set by the 5V INTVCC supply. 2
Consequently, logic-level threshold MOSFETs must V ⎛I •V ⎞
PM4(BOOST) = IN • ⎜ OUT OUT ⎟ • ρT • RDS(ON)
be used in LT3790 applications. If the input voltage is VOUT ⎝ VIN ⎠
expected to drop below the 5V, then sub-logic threshold For the same output voltage and current, switch M1 has
MOSFETs should be considered. the highest power dissipation and switch M2 has the low-
est power dissipation unless a short occurs at the output.
Rev. B

For more information www.analog.com 19

LT3790
APPLICATIONS INFORMATION
From a known power dissipated in the power MOSFET, its The INTVCC pin regulator can supply a peak current of
junction temperature can be obtained using the following 67mA and must be bypassed to ground with a minimum
formula: of 4.7µF ceramic capacitor or low ESR electrolytic capac-
itor. An additional 0.1µF ceramic capacitor placed directly
TJ = TA + P • RTH(JA)
adjacent to the INTVCC and PGND IC pins is highly rec-
The RTH(JA) to be used in the equation normally includes ommended. Good bypassing is necessary to supply the
the RTH(JC) for the device plus the thermal resistance from high transient current required by MOSFET gate drivers.
the case to the ambient temperature (RTH(JC)). This value
Higher input voltage applications in which large MOSFETs
of TJ can then be compared to the original, assumed value
are being driven at high frequencies may cause the max-
used in the iterative calculation process.
imum junction temperature rating for the LT3790 to be
2.0 exceeded. The system supply current is normally domi-
nated by the gate charge current. Additional external load-
ρT NORMALIZED ON-RESISTANCE (Ω)

ing of the INTVCC also needs to be taken into account for

1.5
the power dissipation calculations. Power dissipation for
the IC in this case is VIN • IINTVCC, and overall efficiency
1.0 is lowered. The junction temperature can be estimated by
using the equations given
0.5
TJ = TA + (PD • θJA)
where θJA (in °C/W) is the package thermal impedance.
0
–50 0 50 100 150
For example, a typical application operating in continuous
JUNCTION TEMPERATURE (°C)
3790 F10 current operation might draw 24mA from a 24V supply:
Figure 10. Normalized RDS(ON) vs Temperature TJ = 70°C + 24mA • 24V • 28°C/W = 86°C
To prevent maximum junction temperature from being
Optional Schottky Diode (D3, D4) Selection exceeded, the input supply current must be checked
The Schottky diodes D3 and D4 shown in the Typical operating in continuous mode at maximum VIN.
Applications section conduct during the dead time
between the conduction of the power MOSFET switches. Top Gate (TG) MOSFET Driver Supply (C1, D1, C2, D2)
They are intended to prevent the body diode of synchro- The external bootstrap capacitors C1 and C2 connected
nous switches M2 and M4 from turning on and storing to the BST1 and BST2 pins supply the gate drive voltage
charge during the dead time. In particular, D4 significantly for the topside MOSFET switches M1 and M4. When the
reduces reverse-recovery current between switch M4 top MOSFET switch M1 turns on, the switch node SW1
turn-off and switch M3 turn-on, which improves converter rises to VIN and the BST1 pin rises to approximately VIN
efficiency and reduces switch M3 voltage stress. In order + INTVCC. When the bottom MOSFET switch M2 turns
for the diode to be effective, the inductance between it and on, the switch node SW1 drops low and the bootstrap
the synchronous switch must be as small as possible, capacitor C1 is charged through D1 from INTVCC. When
mandating that these components be placed adjacently. the bottom MOSFET switch M3 turns on, the switch node
SW2 drops low and the bootstrap capacitor C2, is charged
INTVCC Regulator through D2 from INTVCC. The bootstrap capacitors C1 and
An internal P-channel low dropout regulator produces 5V C2 need to store about 100 times the gate charge required
at the INTVCC pin from the VIN supply pin. INTVCC pow- by the top MOSFET switch M1 and M4. In most applica-
ers the drivers and internal circuitry within the LT3790. tions a 0.1µF to 0.47µF, X5R or X7R ceramic capacitor
is adequate.
Rev. B

20 For more information www.analog.com

 LT3790
APPLICATIONS INFORMATION
Efficiency Considerations PC Board Layout Checklist
The power efficiency of a switching regulator is equal to The basic PC board layout requires a dedicated ground
the output power divided by the input power times 100%. plane layer. Also, for high current, a multilayer board pro-
It is often useful to analyze individual losses to determine vides heat sinking for power components.
what is limiting the efficiency and which change would n The PGND ground plane layer should not have any
produce the most improvement. Although all dissipative traces and it should be as close as possible to the layer
elements in circuits produce losses, four main sources with power MOSFETs.
account for most of the losses in LT3790 circuits:
n Place CIN, switch M1, switch M2 and D1 in one com-
1. DC I2R losses. These arise from the resistances of the pact area. Place COUT, switch M3, switch M4 and D2
MOSFETs, sensing resistor, inductor and PC board in one compact area.
traces and cause the efficiency to drop at high output
currents.
n Use immediate vias to connect the components
(including the LT3790’s SGND and PGND pins) to the
2. Transition loss. This loss arises from the brief amount ground plane. Use several large vias for each power
of time switch M1 or switch M3 spends in the satu- component.
rated region during switch node transitions. It depends n Use planes for VIN and VOUT to maintain good voltage
upon the input voltage, load current, driver strength
filtering and to keep power losses low.
and MOSFET capacitance, among other factors. The
loss is significant at input voltages above 20V and can n Flood all unused areas on all layers with copper.
be estimated from: Flooding with copper will reduce the temperature rise
of power components. Connect the copper areas to any
Transition Loss ≈ 2.7 • VIN2 • IOUT • CRSS • f DC net (VIN or PGND).
where CRSS is the reverse-transfer capacitance. n Separate the signal and power grounds. All small-sig-
3. INTVCC current. This is the sum of the MOSFET driver nal components should return to the SGND pin at one
and control currents. point, which is then tied to the PGND pin close to the
sources of switch M2 and switch M3.
4. CIN and COUT loss. The input capacitor has the difficult
job of filtering the large RMS input current to the reg- n Place switch M2 and switch M3 as close to the con-
ulator in buck operation. The output capacitor has the troller as possible, keeping the PGND, BG and SW
difficult job of filtering the large RMS output current traces short.
in boost operation. Both CIN and COUT are required to n Keep the high dV/dT SW1, SW2, BST1, BST2, TG1 and
have low ESR to minimize the AC I2R loss and sufficient TG2 nodes away from sensitive small-signal nodes.
capacitance to prevent the RMS current from causing
additional upstream losses in fuses or batteries.
n The path formed by switch M1, switch M2, D1 and the
CIN capacitor should have short leads and PC trace
5. Other losses. Schottky diode D3 and D4 are responsi- lengths. The path formed by switch M3, switch M4, D2
ble for conduction losses during dead time and light and the COUT capacitor also should have short leads
load conduction periods. Inductor core loss occurs and PC trace lengths.
predominately at light loads. Switch M3 causes reverse n The output capacitor (–) terminals should be connected
recovery current loss in boost operation.
as close as possible to the (–) terminals of the input
When making adjustments to improve efficiency, the input capacitor.
current is the best indicator of changes in efficiency. If you n Connect the top driver bootstrap capacitor, C1, closely
make a change and the input current decreases, then the
to the BST1 and SW1 pins. Connect the top driver boot-
efficiency has increased. If there is no change in the input strap capacitor, C2, closely to the BST2 and SW2 pins.
current, then there is no change in efficiency.
Rev. B

For more information www.analog.com 21

LT3790
APPLICATIONS INFORMATION
n Connect the input capacitors, CIN, and output capac- Differences Between LT3790 and LT3791-1
itors, COUT, closely to the power MOSFETs. These The LT3790 is an improved version of the LT3791-1 and
capacitors carry the MOSFET AC current in boost and is recommended for use in new designs. Some exter-
buck operation. nal component values may change, but otherwise, the
n Route SNSN and SNSP leads together with minimum LT3790 is functionally equivalent to the LT3791-1. The
PC trace spacing. Avoid sense lines pass through noisy differences between the two products are:
areas, such as switch nodes. Ensure accurate current 1. The LT3790 has a 60mV (typical) full-scale V(ISP-ISN)
sensing with Kelvin connections at the SENSE resistor. current sense voltage, compared to 100mV (typical) for
n Connect the VC pin compensation network close to the the LT3791-1. This change allows lower power current
IC, between VC and the signal ground pins. The capac- sense resistors to be used for most applications.
itor helps to filter the effects of PCB noise and output 2. The LT3790 CTRL pin linear range is from 0V to 1.1V,
voltage ripple voltage from the compensation loop. and has a turn-off threshold of 50mV(typical), com-
n Connect the INTVCC bypass capacitor, CVCC, close to pared to a 200mV to 1.1V linear range and 175mV
the IC, between the INTVCC and the power ground pins. (typical) turn-off threshold for the LT3791-1. These
This capacitor carries the MOSFET drivers’ current changes make it easier to parallel two or more LT3790
peaks. An additional 0.1µF ceramic capacitor placed ICs for higher power levels.
immediately next to the INTVCC and PGND pins can 3. The LT3790 C/10 pin pulls low when the V(ISP-ISN)
help improve noise performance substantially. voltage is less than 1/10 full scale, compared to the
LT3791-1, where C/10 pulls low when both V(ISP-ISN)
is less than 1/10 full scale and VFB is greater than
1.15V(typical). Since the C/10 pin is used to allow DCM
mode for some applications, this change ensures that
negative current does not occur at light loads for a
broader range of applications.

Rev. B

22 For more information www.analog.com

 LT3790
TYPICAL APPLICATIONS
98% Efficient 60W (12V 5A) Voltage Regulator Runs Down to 3V VIN
RIN
VIN 0.003Ω
CIN
3V TO 55V VO 4.7µF
STARTS UP R7
D5 100V
ABOVE 5.5V 51Ω D6
×4
VIN INTVCC
CVCC + COUT2
C3 D1 D2 4.7µF 100µF
1µF VO ROUT
BST2 35V
IVINN 0.009Ω VOUT
C7 C2
BST1 0.1µF 12V
470nF COUT 5A
IVINP
C1 10µF
TG1 M1 D4 M4
0.1µF 25V
R1 R3 R5
866k 1M SWI ×3
L1, 6.8µH 73.2k
EN/UVLO BG1 M2 M3
D3
OVLO R6
R2 R4 INTVCC SNSP 8.06k
576k 57.6k RSENSE
R9 R10 LT3790 0.004Ω
100k 200k
SHORT SNSN
C/10 PGND
CCM
BG2
IVINMON
SW2
ISMON
TG2
CLKOUT
ISP
PWMOUT
ISN
VREF
C8 FB
3790 TA02a
0.1µF PWM
RFAULT D1, D2: NXP BAT46WJ
100k CTRL
D3: IRF 10BQ060
SS SYNC VC RT SGND D4: IRF 10BQ040
R8 D5, D6: DIODES INC. BAT46W
RC
CSS 84.5k L1: WURTH ELEKTRONIK WE-HCI 7443556680
5.1k
33nF 300kHz M1, M2: RENASAS RJK0651DPB 60VDS
CC M3, M4: VISHAY SiR424DP 40VDS
22nF COUT2: SUNCON 35HVT100M

Efficiency vs Load Current Maximum Output Current vs VIN

100 6
95
5
MAXIMUM OUTPUT CURRENT (A)

90
85
4
EFFICIENCY (%)

80
75 3
70
VIN = 3V 2
65
VIN = 6V
60 VIN = 12V 1
55 VIN = 28V
VIN = 48V
50 0
0 1 2 3 4 5 3 4 5 6 7 8 9 10 20 30 40 50 60
LOAD CURRENT (A) INPUT VOLTAGE (V)
3790 TA02b 3790 TA02c

Rev. B

For more information www.analog.com 23

LT3790
TYPICAL APPLICATIONS
98% Efficient 240W (24V 10A) Parallel Voltage Regulators
VIN 0.003Ω
12V TO
58V 4.7µF
+ C1 Transient Waveform
51Ω 100V 47µF
470nF 1µF
499k 499k 80V

INTVCC1
IVINP IVINN VIN INTVCC
4.7µF
EN/UVLO CCM D1 D2 10V
VOUT
OVLO 4.7µF 1V/DIV
BST2 50V
56.2k 27.4k ×2
0.1µF
C/10 0.009Ω VOUT IL2
BST1 24V 5A/DIV
INTVCC1 0.1µF 10A
TG1 M1 M4 COUT1
220µF IL1
200k SWI 5A/DIV
L1 51Ω 35V
SHORT SHORT BG1 M2 10µH M3 + ×2
VREF
0.47µF 3790 TA03a
0.1µF PWM LT3790 SNSP 1ms/DIV
CTRL 0.004Ω VIN = 36V
100k IOUT = 5A TO 10A
SNSN
SS PGND
33nF
BG2
IVINMON SW2
Startup Waveform
715k
CLKOUT TG2
ISMON ISP
SYNC 13.7k
ISN
VOUT
FB
VC RT SGND 5V/DIV
38.3k
3.3k 147k VSS
200kHz 1V/DIV
33nF
IL1
5A/DIV
0.003Ω
VIN IL2
4.7µF
+ C2 5A/DIV
51Ω 100V 47µF
470nF 1µF
499k 499k 80V
3790 TA03b
1ms/DIV
INTVCC2
IVINP IVINN VIN INTVCC VIN = 36V
4.7µF IOUT = 5A
EN/UVLO CCM D3 D4 10V
OVLO 4.7µF
BST2 50V
56.2k 27.4k ×2
0.1µF
C/10
BST1
0.009Ω Mismatch Current vs Load Current
INTVCC2 0.1µF
TG1 M5 M8 COUT2 0.5
200k 220µF
SWI 35V 0.4
L2 51Ω
SHORT SHORT BG1 M6 10µH M7 + ×2
VREF 0.3
0.22µF
0.1µF PWM LT3790 SNSP 0.2
0.004Ω 0.1
100k
∆I (A)

SNSN 0.0
SS PGND
33nF –0.1
BG2
CTRL SW2 –0.2
715k
IVINMON TG2
1nF –0.3
ISMON ISP
CLKOUT 140k –0.4
ISN
SYNC FB
VC RT SGND –0.5
38.3k 0 2 4 6 8 10
147k LOAD CURRENT (A)
D1–D4: NXP BAT46WJ
200kHz 3790 TA03c
1000pF 2.2k L1, L2: COILCRAFT SER2915L-103KL 10µH
M1, M2, M5, M6: RENESAS RJK0651DPB 60Vds
22nF M3, M4, M7, M8: RENESAS RJK0451DPB 40Vds
COUT1, COUT2: SUNCON 35HVT220M ×2
C1, C2: NIPPON CHEMICON EMZA800ADA470MJAOG

3790 TA03

Rev. B

24 For more information www.analog.com

 SLAVE × 2

VIN 0.003Ω 0.003Ω

12V TO VIN
58V 4.7µF
+ C1 4.7µF
+ C2
51Ω 100V 47µF 51Ω 100V 47µF
470nF 1µF 470nF 1µF
499k 499k 80V 499k 499k 80V

INTVCC1 INTVCC2
IVINP IVINN VIN INTVCC IVINP IVINN VIN INTVCC
4.7µF 4.7µF
EN/UVLO CCM D1 D2 EN/UVLO CCM D3 D4
10V 10V
OVLO 4.7µF OVLO 4.7µF
BST2 50V BST2 50V
56.2k 27.4k ×2 56.2k 27.4k ×2
0.1µF 0.1µF
C/10 0.009Ω C/10 0.009Ω
TYPICAL APPLICATIONS

VOUT
BST1 24V BST1
INTVCC1 0.1µF 15A INTVCC2 0.1µF
TG1 M1 M4 COUT1 TG1 M5 M8 COUT2
200k 220µF 200k 220µF
SWI SWI 35V
L1 51Ω 35V L2 51Ω
SHORT SHORT BG1 M2 10µH M3 + ×2 SHORT SHORT BG1 M6 10µH M7 + ×2
VREF VREF
0.47µF 0.22µF
0.1µF PWM LT3790 SNSP 0.1µF PWM LT3790 SNSP
CTRL 0.004Ω 0.004Ω
100k 100k
SNSN SNSN
SS PGND SS PGND
33nF 33nF
BG2 BG2
IVINMON SW2 715k CTRL SW2 715k
CLKOUT TG2 IVINMON TG2
1nF
ISMON ISP ISMON ISP
SYNC1 13.7k 140k
SYNC ISN CLKOUT ISN
FB SYNC FB
VC RT SGND VC RT SGND
38.3k 38.3k

For more information www.analog.com

3.3k 147k 147k
200kHz 1000pF 200kHz
33nF 2.2k

22nF
98% Efficient 360W (24V 15A) Parallel Voltage Regulators

INTVCC1 LTC6902
V+ OUT1
SYNC2
1µF DIV OUT2
SYNC3
MOD OUT3
332k
SET PH 3790 TA04
D1–D4: NXP BAT46WJ
GND L1, L2: COILCRAFT SER2915L-103KL 10µH
M1, M2, M5, M6: RENESAS RJK0651DPB 60Vds
M3, M4, M7, M8: RENESAS RJK0451DPB 40Vds
COUT1, COUT2: SUNCON 35HVT220M ×2
C1, C2: NIPPON CHEMICON EMZA800ADA470MJAOG

25
Rev. B
LT3790
LT3790
PACKAGE DESCRIPTION
FE Package
38-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1772 Rev C)
Exposed Pad Variation AA

4.75 REF 9.60 – 9.80*

(.378 – .386)
4.75 REF
(.187)
38 20

6.60 ±0.10
2.74 REF
4.50 REF
SEE NOTE 4 6.40
2.74
0.315 ±0.05 REF (.252)
(.108)
BSC
1.05 ±0.10

0.50 BSC
RECOMMENDED SOLDER PAD LAYOUT
1 19
1.20
4.30 – 4.50* (.047)
(.169 – .177) 0.25 MAX
REF
0° – 8°

0.50
0.09 – 0.20 0.50 – 0.75 (.0196) 0.05 – 0.15
(.0035 – .0079) (.020 – .030) BSC (.002 – .006)
0.17 – 0.27
FE38 (AA) TSSOP REV C 0910
(.0067 – .0106)
TYP
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS 4. RECOMMENDED MINIMUM PCB METAL SIZE
2. DIMENSIONS ARE IN MILLIMETERS FOR EXPOSED PAD ATTACHMENT
(INCHES) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
3. DRAWING NOT TO SCALE SHALL NOT EXCEED 0.150mm (.006") PER SIDE

Rev. B

26 For more information www.analog.com

 LT3790
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
A 12/15 Clarified Typical Application schematic. 1
Clarified Electrical V(ISP-ISN) Threshold parameters. 3
Clarified ISP/ISN Bias Current parameters. 3
Clarified Block Diagram. 11
Clarified ILED to IOUT in Equations. 17, 20
Clarified Loop Compensation paragraph. 10
B 01/22 Changed CTRL Latch-Off Threshold MIN/MAX spec. 3

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license For more by
is granted information www.analog.com
implication or otherwise under any patent or patent rights of Analog Devices. 27
LT3790
TYPICAL APPLICATION
2.4A Buck-Boost 36V SLA Battery Charger
PVIN
9V TO 58V
RIN CIN + CIN2
0.003Ω VIN INTVCC 4.7µF 100µF
1µF 4.7µF 100V 63V
D1 D2
×2
51Ω BST2
IVINN BST1 0.1µF
470nF COUT + COUT2
TG1 M1 0.1µF M4 4.7µF 220µF
499k IVINP
50V 50V
SWI
EN/UVLO L1 10µH ×2
OVLO BG1 M2 M3
57.6k
INTVCC
LT3790 SNSP
200k
30.9k SHORT RSENSE RBAT 2.4A
0.004Ω 0.025Ω CHARGE
PWMOUT
SNSN
PGND
+ 36V
SLA BATTERY
IVINMON BG2 AGM TYPE
ISMON 41V FLOAT
SW2 44V CHARGE
CHARGE CURRENT CONTROL CTRL TG2 AT 25°C
CLKOUT ISP
SGND 1µF 51Ω
ISN
VREF FB
0.1µF PWM C/10 1.00M
CCM INTVCC
100k
SS SYNC VC RT
20k 402k 30.1k
D1, D2: BAT46WJ 84.5k
22nF 2.2k
L1: COILCRAFT SER2915L-103K 300kHz M5
M1-M4: RENESAS RJK0651DPB
M5: NXP NX7002AK 22nF 3790 TA05
CIN2: NIPPON CHEMI-CON EMZA630ADA101MJA0G
COUT2: SUNCON 50HVT220M

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Rev. B

28
03/22
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