MECPC 103: DIGITAL VLSI CIRCUIT

Course Objectives:
1. To understand how a digital IC is designed under VLSI technology
2. Application of SRAM, DRAM & RRAM in industry

No. of
Unit Topic
Lecture
Issues of Digital IC Design: General overview of design
Unit I hierarchy, layers of abstraction, integration density and
7
Moore's law, VLSI design styles, VLSI hierarchy, Regularity,
Modularity and Locality, VLSI Design Flow.
Logic Design: switch logic, gate restoring logic,
Programmable Logic Array (PLAs), Finite State Machine
(FSM) as a PLA, personality matrix of a PLA, PLA folding,
pseudo-nmos logic, BiCMOS logic gates; Basic Circuit
Unit II
Concepts: sheet resistance and area capacitances of layers, 8
driving large capacitive loads, super-buffers, propagation
delay models of cascaded pass transistors, wiring
capacitances, switching delay in BiCMOS logic circuits;
Bipolar ECL.
Inverter : features of ECL gate, robustness and noise
immunity, logic design in ECL, single-ended and differential
ECL gates; Dynamic CMOS design : steady-state behavior of
dynamic gate circuits, noise considerations in dynamic
Unit III 9
design, charge sharing, cascading dynamic gates, domino
logic, np-CMOS logic, problems in single-phase clocking,
two-phase non-overlapping clocking scheme, different logic
families like CPL, DCVSL etc.
Sequential CMOS Logic Circuits: basic regenerative circuits,
digital phase-locked loop (DPLL); Low-power CMOS Logic
Circuits: low-power design through voltage scaling,
Unit IV estimation and optimization of switching activity, reduction
9
of switched capacitance, adiabatic logic circuits; Subsystem
Design: design of arithmetic building blocks like adders and
multipliers, barrel and logarithmic shifters, area-time
tradeoff, power consumption issues.
Semiconductor Memories : Dynamic Random Access
Memories (DRAM), Static RAM, non-volatile memories,
flash memories, low-power memory; Case Study (instructor
Unit V
may choose any suitable digital system; in the following, an 7
example is suggested) : A RISC Processor - Instruction Set,
Pipeline Architecture, Major Logic Blocks, Layout,
Functional Verification.

Course Learning Outcomes (CLO):

 After finishing of this course the students will be able to -
1. Solve problems occurs in different VLSI industry.
2. Solve application specific digital IC testing
3. Discuss the high density memory packaging.
4. Students will be substantially prepared to take up prospective research assignments.

Text Book:
1- Digital Integrated Circuits. Sung-Mo Kang, Yusuf Leblebici. Tata McGraw-Hill
2- - Digital Integrated Circuits VLSI-Rabaey - Digital Integrated Circuits.

MAPPING OF CLO WITH PO

Course
Learning Program Outcomes(PO)
Outcomes
(CLO): 1 2 3 4 5 6 7 8 9 10 11

1 3 2 2 2 2

2 3 3 2 2

3 2 3 1 2 2

4 3 2 2

MECPC 104: ADVANCE MICROPROCESSOR & MICROCONTROLLER

Course Objectives:
The course is design to meet with the objectives of:
1. To study the Architecture of microprocessor 8086
2. To study the programming of 8086 using C.
3. To study the architecture of INTEL 8051.
 No. of
Unit Topic
Lecture
8085 Microprocessor architecture – signals – Addressing
modes – Instruction classification Instruction set—Timing
diagram – ALP format – Programming 8085 – 8-bit and 16-
bit Operation including stack-subroutine.
Unit I 7
Introduction to 8086 microprocessor: Architecture of 8086
(Pin diagram, Functional block diagram, Register
organization Arithmetic operations, Logic Operations, Branch
operation.
Program structure of 8086, 8086 instruction, Assembler
Unit II Directives, string, procedures & macros, 8086 interrupts and 9
interrupt applications, Interfacing.
Microcomputer system peripherals, Introduction of 80386
microprocessors, scheduling, memory management, mode of
Unit III 7
operation, call gate, privilege levels, Interrupt and Exception
handling, Paging, introduction to Pentium Processors.
INTEL 8051 architecture, instruction set and programming,
Memory mapping, addressing modes, Registers, expanded
Unit IV modes. Interrupt handling timing and serial I/O. Design and 9
application of Micro-Controller in Data acquisition,
Embedded controllers, Process control etc.
Programming techniques in C: looping, counting and
indexing, Programmable peripheral interface, interfacing
Unit V 8
keyboard and seven segment display and other output devices,
8051 serial port programming.

Course Learning Outcomes (CLO):

1. Understanding basic principle of microprocessor.
2. Microprocessor programming and interfacing.
3. Understand efficiency in microprocessor-based system.
4. Write code or a compiler for a microprocessor which takes advantage of the
advanced architectural techniques.

Text and Reference Books:

1. Douglas V Hall “Microprocessors and interfacing” TMH Publication.

2. Muhammad Ali Mazidi “The 8051Microcontroller and Embedded System” TMH
Publication.

MAPPING OF CLO WITH PO

Course
Learning Program Outcomes(PO)
Outcomes
(CLO): 1 2 3 4 5 6 7 8 9 10 11

1 3 2 2 2 1

2 2 2 2

3 2 3 1 2 2 2

4 2 2 1 2
 MECPE 301: LOW POWER VLSI DESIGN

Course Objectives:
The course is designed to meet with the objectives of
1. To understand the basics of MOS in different regions of operation and to understand how
to apply proper bias voltages so as to operate as a switch or amplifier.
2. To understand the operations of CAD tools in the design and analysis of low power
CMOS circuits.

No. of
Unit Topic
Lecture
Introduction to VLSI design: MOS Physics, Structure and
Unit I operation of MOSFETs, MOSFET current- voltage
9
characteristics, MOSFET Modeling, MOSFET Scaling,
MOSFET Capacitances.
Low Power Design: Introduction, Needs of Low power VLSI
chips, dynamic power dissipation, short circuit power
Unit II
dissipation, leakage power dissipation. Review of power 8
dissipation in CMOS Circuits – static and dynamic power
dissipation Leakage sources.
MOSFET Scaling: constant field scaling, constant voltage
Unit III scaling, limitations on scaling of MOSFET, comparison
between constant field and constant voltage scaling, advantages 7
of scaling, disadvantages of scaling.
Low–Power CMOS Logic Circuits: Introduction, Low –
Power Design through voltage scaling, Variable threshold
CMOS Circuits, Multiple threshold CMOS circuits, Estimation
Unit IV and Optimization of switching activity, Reduction of Switched
9
Capacitance and Adiabatic Logic Circuits.
POWER ESTIMATION: Power Estimation techniques, logic
power estimation, Simulation power analysis, Probabilistic
power analysis.
SYNTHESIS AND SOFTWARE DESIGN FOR LOW
Unit V POWER: Synthesis for low power – Behavioral level 7
transform – software design for low power.

Course Learning Outcomes (CLO):

Upon Completion of the topics:
1. Students will be able to bias MOS transistors depending on requirements.
2. Knowledge about operations of low power CMOS circuits.

Text Books:
1. Kaushik Roy and S.C.Prasad, “Low power CMOS VLSI circuit design”, Wiley.
 2. Dimitrios Soudris, Chirstian Pignet, Costas Goutis, “Designing CMOS Circuits for Low
Power”, Kluwer.

Reference Books:
3. J.B. Kulo and J.H Lou, “Low voltage CMOS VLSI Circuits”, Wiley.
4. A.P .Chandrasekaran and R.W.Broadersen, “Low power digital CMOS design” Kluwer.

MAPPING OF CLO WITH PO

Course
Learning Program Outcomes(PO)
Outcomes
(CLO): 1 2 3 4 5 6 7 8 9 10 11

1 3 2 2 1 2

2 3 3 1 3 2 2

MECPE 401: FAULT TOLERANT DIGITAL DESIGN

Course Objectives:
The course is designed to meet the objectives of:
1. Acquire knowledge about fault tolerance in arithmetic circuits.
2. Learn about Fault diagnosis, Fault tolerance measurement.
No. of
Unit Topic Lectur
e
Unit Basic Concept of Reliability: Definition, Failure Rate, Relation between Mean time
I and Reliability, Maintainability, Availability, Series and Parallel System.
8
Faults in Digital Circuits: Failures and Faults, Modeling of Faults- (Stuck at Faults,
Bridging Faults, Stuck Open Faults), Temporary Faults.
Unit Test Generation: Fault Diagnosis of Digital Systems, Test Generation for
2 Combinational Logic Circuits (One Dimension Path Sensitization, Boolean
Difference, D- Algorithm, PODEM), Detection of Multiple Faults in Combinational 8
Logic Circuits, Test Generation for Sequential Logic Circuits, Random Testing,
Transition Count Testing, Signature Analysis.
Unit Fault Tolerant Design of Digital System: Concept of Fault Tolerance, Static
3 Redundancy, Dynamic Redundancy, Hybrid Redundancy, Self Purging Redundancy,
Shift out Modular Redundancy, 5MR Reconfiguration Scheme, Fault Tolerant 8
Design of Memory Systems using Error correcting codes, Time Redundancy,
Software Redundancy, Fail Soft Operation, Fault Tolerant chip for Design of VLSI
 Chips.

Unit Self Checking and Fail Safe Logic: Design of Totally Self Checking Checkers (Two
4 Rail Checkers, Self Checking checkers for m-out –of – n Codes, Self Checking for
8
Burger codes, Low cost residual code), Self Checking sequential Machine, Partially
Self Checking Circuits, Fail Safe Design.
Unit Design for Testability: Testability, Controllability and Observability, Design of
5 Testable Combinational Logic Circuits, Testable Design of Sequential Circuits, Scan
Path Techniques for Testable sequential circuits design, Level Sensitive Scan Design, 8
Random Access Scan Techniques, Built in Test, Design Testability into Logic
Boards.
3. Acquire knowledge on Software reliability models, and methods.

Course Learning Outcomes (CLO):

Upon Completion of the topics
1. To explain the concept of reliability & faults in digital circuit.
2. Understand the design, testing & fault tolerant design.

Text Books:
1. Fault Tolerant and Fault Testable Hardware Design by P. K. Lala , BS publication.
2. Digital circuits and logic design, Samuel C. Lee, by PHI.
3. Diraj K. Pradhan, “Fault Tolerant Computer System Design”, Prentice Hall.
Reference Books:
4. M. Abramovici, M.A. Breuer, A.D. Friedman, “Digital systems testing and testable
design”,
Jaico Publishing House.

MECPE 351: VLSI CAD LAB

1- Design the following circuits with given specifications*, completing the

Design flow mentioned below:
a. Draw the schematic and verify the following
i) DC Analysis
ii) AC Analysis
iii) Transient Analysis
b. Draw the Layout and verify the DRC, ERC
c. Check for LVS
 d. Extract RC and back annotate the same and verify the Design
i) AND, OR, NOR, NAND, NOT
ii) XOR, XNOR
2 Design an op-amp with given specification* using given differential amplifier Common
source and Common Drain amplifier in library** and completing the design flow mentioned
below:
a. Draw the schematic and verify the following
i) DC Analysis
ii) AC Analysis
iii) Transient Analysis
b. Draw the Layout and verify the DRC, ERC
c. Check for LVS
d. Extract RC and back annotate the same and verify the Design.
3 Design an comparator with given specification* using given differential amplifier
Common Source and Common Drain amplifier in library** and completing the design
Flow mentioned below:
a. Draw the schematic and verify the following
i) DC Analysis
ii) AC Analysis
iii) Transient Analysis
b. Draw the Layout and verify the DRC, ERC
c. Check for LVS
d. Extract RC and back annotate the same and verify the Design.
4 Design a 4 bit R-2R based DAC for the given specification and completing the design flow
mentioned using given op-amp in the library**.
a. Draw the schematic and verify the following
i) DC Analysis
ii) AC Analysis
iii) Transient Analysis
b. Draw the Layout and verify the DRC, ERC
c. Check for LVS
d. Extract RC and back annotate the same and verify the Design.
5 For the SAR based ADC mentioned in the figure below draw the mixed signal schematic and
verifies the functionality by completing ASIC Design FLOW.
Course Learning Outcomes (CLO):
At the end of this module, students are expected to be able to:
1. Comprehend the stability issues of the systems and should be able to design OpAmp
fully. Compensated against process, supply and temperature variations.
2. Design & analysis of comparator, DAC & verify their functionality.
3. Draw the layout of DRC, ERC & their verification.

MAPPING OF CLO WITH PO

Course
Learning Program Outcomes(PO)
 Outcomes
(CLO): 1 2 3 4 5 6 7 8 9 10 11

1 3 2 2 2 3 2

2 2 2 2 1 2

3 2 1 2 1 2 2

MECPS 152: ADVANCED MICROPROCESSOR & MICROCONTROLLER LAB

Experiments Based on Microprocessor (8086/8088)

Assembling and Executing the Program
1. Programs on Data Transfer Instructions.
2. Programs on Arithmetic and Logical Instructions.
3. Programs on Branch Instructions.
4. Programs on Subroutines.
5. Sorting of an Array.
6. Programs on Interrupts (Software and Hardware).
7. 8086 Programs using DOS and BIOS Interrupts.
Experiments Based on Interfacing & Microcontroller (8051)
8. DAC Interface of Waveform generations.
9. Stepper Motor Control.
10. Keyboard Interface / LCD Interface.
11. Data Transfer between two PCs using RS.232 C Serial Port.
12. Programs on Data Transfer Instructions using 8051 Microcontroller.
13. Programs on Arithmetic and Logical Instructions using 8051 Microcontroller.
14. Applications with Microcontroller 8051.

Course Learning Outcomes (CLO):

At the end of this module, students are expected to be able to:
1. To write a program & debugging related to 8086/8088 microprocessor.
2. How to control different function of stepper motor.
3. Transfer data between two PCs using different techniques.

MAPPING OF CLO WITH PO

Course
Learning Program Outcomes(PO)
Outcomes
(CLO): 1 2 3 4 5 6 7 8 9 10 11

1 2 2 2 2 1

2 2 2 1 2 2

3 2 1 2 2 2 2