Q1)Von Neumann architecture

1)Memory- Used to store programs and data for computer. Instructions are taken by processor,
decoded and executed. Similarly, data is also stored in memory, operation is performed on it and
results are stored in memory.

It consists of memory address register and memory data register which are used to get data to and
from memory.

2)Processing unit has arithmetic logic unit, that performs arithmetic and logical operations .Temp
refers to temporary storage by registers. Registers store the operands and the result of operations

3)Control unit controls the flow and execution of program. Consists of instruction register (contains
current instruction) and program counter(contains address of next instruction to be executed).

4)Input./output are devices used to accept input from user and display the result back to the
computer.e .g mouse, monitor etc.

Q2)8086 features

1)16 bit microprocessor

2)20 bit address bus that can access upto 2^20 memory locations(1mb), also has 16 bit databus

3)Supports upto 64k I/O ports

4)Can support upto 14, 16 bit registers

5) It has multiplexed address and data bus AD0- AD15 and A16 – A19.

6)Can operate in two modes, minimum and maximum

7) +5V power supply

8)Has a 440 pin dual in line package

9) It can prefetches up to 6 instruction bytes from memory and queues them in order to speed up
instruction execution

Q3)8086 architecture

8086 has two blocks BIU and EU.

- The BIU handles all transactions of data and addresses on the buses for EU.

- The BIU performs all bus operations such as instruction fetching, reading and writing operands for
memory and calculating the addresses of the memory operands. The instruction bytes are
transferred to the instruction queue.

- EU executes instructions from the instruction system byte queue

1) EU:

1)ALU- 16 bit unit that can perform a variety of arithmetic and logical operations like ad, subtract,
and,or,not etc.

2)Flag register is a 16 bit register with each bit corresponding to a flip flop. Each bit indicates some
condition produced by the execution of some instruction.
3) General purpose registers:

There are 4 general purpose 16 bit registers. AX,BX,CX,DX. They can be used as 16 bit registers or as
8 bit individual registers (AH, AL,BL,CH etc). They can also be used as 32 bit registers like AX can be
used with DX for a 32 bit operand.

AX: It is a 16 bit accumulator that can also be used as separate 8 bit registers of AH and AL. It stores
the operands and results of operations like multiplication,division. Addition and subtraction can be
used with any register but are more efficient with accumulator.

BX: base register. Used for indirect addressing

CX:Count register. Used for looping instructions, shift and rotate instructions. Also used with string
instructions.

DX: data register, used with AX for word sizrs mul and div operatons when operand is greater than
register. (32 bit). Also, holds port number for IN and OUT instructions.

4)Pointer and index registers:

-used to keep offset addresses.

- Used in various forms of memory addressing.

Stack pointer

-Used with SS to access the stack segment

BP: Base Pointer– Primarily used to access data on the stack– Can be used to access data in other
segments

SI: Source Index register and DI (destination index register)– is required for some string operations
2)BIU:

-6-byte Instruction Queue-

This queue permits pre-fetch of up to 6 bytes of instruction code. Whenever the queue of the BIU is
not full, it has room for at least two more bytes and at the same time the EU is not requesting it to
read or write operands from memory, the BIU is free to look ahead in the program by pre-fetching
the next sequential instruction. 17

-These pre-fetching instructions are held in its FIFO queue.

Segments-

-Code segment is used for storing the instructions.

– The stack segment is used as a stack and it is used to store the return addresses

- The data and extra segments are used for storing data byte
Q3) Organization vs architecture
Q4)

a)Register addressing

b)Immediate addressing
c)Direct addressing

d)Register indirect addressing

Q5)

FLynns classification of computers

SISD: SISD machines executes a single instruction on individual data values using a single processor.

- Traditional sequential architecture.

- Based on traditional Von Neumann uniprocessor architecture, instructions are executed
sequentially or serially, one step after the next.

- Until most recently, most computers are of SISD type.

- Parallelism can be achieved by Pipelining.

SIMD: -An SIMD machine executes a single instruction on multiple data values simultaneously
using many processors.

- Since there is only one instruction, each processor does not have to fetch and decode each
instruction. Instead, a single control unit does the fetch and decoding for all processors.

- SIMD architectures include array processors (ILLIAC-IV).

MISD:

-Multiple operations on same data.

-The result from one processing unit is input to next processing unit.

-It is not clear till now whether such machine exists or not.

MIMD:

-Multiple independent CPUs are there.

- It may execute multiple instructions simultaneously, contrary to SIMD machines.

- Multiple instruction streams operating on multiple data streams.

- Each processor must include its own control unit that will assign to the processor

parts of a task or a separate task.

-It may look like multiple SISD (MSISD).

Q6) InstructionCycle

A program that exists inside a computer's memory unit consists of a series of instructions. The
processor executes these instructions through a cycle for each instruction.

In a basic computer, each instruction cycle consists of the following phases:

Instruction fetch: fetch instruction from memory

Decode the instruction: what operation to be performed.

Read the effective address from memory Execute the instruction

Registers Involved In Each Instruction Cycle:

Memory address registers(MAR) : It is connected to System Bus address lines. It specifies the
address of a read or write operation in memory.

Memory Buffer Register(MBR) : It is connected to the data lines of the system bus. : It is connected
to the system bus Data Lines. It holds the memory value to be stored, or the last value read from the
memory.

Program Counter(PC) : Holds the address of the next instruction to be fetched.

Instruction Register(IR) : Holds the last instruction fetched.

Decode:

Execute:

Better version:

1) Fetch

• The Program Counter (PC) holds the address of the next instruction.

• This address is copied into the Memory Address Register (MAR).

• The Control Unit (CU) fetches the instruction from memory using the address in MAR.

• The fetched instruction is stored in the Memory Data Register (MDR).

• The instruction is then transferred to the Instruction Register (IR) for decoding.

• The PC is incremented (PC → PC + instruction length) to point to the next instruction.

2) Decode

• The Control Unit reads the instruction from IR.

• It identifies the opcode (operation to be performed) and the operands (data/addresses

needed for execution).

• Addressing modes (direct, indirect, register, etc.) determine how operands are accessed.

• Necessary registers and memory locations are prepared for execution.

3) Execute

• The ALU (Arithmetic Logic Unit) executes arithmetic/logical operations.

• Memory read/write operations are handled via MAR and MDR.

• Control flow changes (like JUMP, CALL, or RETURN) modify the PC to point to a different
instruction.

• The result is stored in a register or memory, depending on the instruction type.

Q7)Hub,repeater,switch,bridge,gateway

Networking Devices and Their Functions

1. Repeater

Regenerates weak signals to extend network coverage.

Operates only at the Physical Layer (Layer 1).

Does not amplify signals; instead, it cleans and retransmits them.

2. Hub

Connects multiple devices in a network (e.g., LAN).

Broadcasts data to all devices without filtering traffic.

Operates at the Physical Layer (Layer 1).

3. Bridge

Connects two or more network segments, filtering traffic based on MAC addresses.

Maintains a MAC address table to make forwarding decisions.

Helps reduce network congestion by segmenting traffic.

Operates at the Data Link Layer (Layer 2), though it interacts with the Physical Layer (Layer 1).

Types: Simple bridge, Multiport bridge.

4. Switch

Functions as a smart hub, forwarding data to specific devices instead of broadcasting.

Uses MAC addresses for filtering and forwarding.

Reduces network congestion compared to hubs.

Operates primarily at the Data Link Layer (Layer 2) but can also function at Layer 1 (Physical Layer).
Some advanced switches work at Layer 3 (Network Layer).

5. Router

Routes data between different networks using IP addresses.

Uses routing tables to determine the best path for data packets.

Operates at the Network Layer (Layer 3), but also interacts with the Physical (Layer 1) and Data Link
(Layer 2) layers.

6. Gateway

Converts data between different protocols (e.g., AppleTalk to TCP/IP).

Can operate at any layer of the OSI model, depending on the function (commonly at Layer 7 -
Application Layer for protocol conversion).

Q8)IP4 classful