19ECE313/VLSI Design

VI Semester
Department of ECE
Amrita School of Engineering,
Bengaluru
 7. Electronic Analysis of CMOS Logic Gates
Goal
• Understand how to perform electronic analysis of CMOS logic
gates. DC characteristics Noise margin
• Switching characteristics
• Power

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PMOS and NMOS Structure

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 Ideal Voltage Transfer Characteristic (VTC)

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 CMOS
Inverter VTC

CMOS Inverter
Voltage Transfer Characteristic (VTC)
VIL and VIH are the two points at which Slope is equal to (dvout/dvin) = -1

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 CMOS
Inverter
VTC

CMOS Inverter
Voltage Transfer
Characteristic
(VTC)

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 Finding Region
of Operation of
MOSFETs in
various regions
of VTC of
CMOS Inverter

Region Vin Vout NMOS PMOS

Operating Operating
Region Region
A < Vtn VDD
B VIL VOH ≈ VDD
(HIGH)
C VM VM
D VIH VOL ≈ GND
(LOW)
E VDD GND
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 For Region A on VTC
For NMOS For PMOS
VG = (<Vtn) VG = (<Vtn)
VS = 0 VS = VDD
VGS = VG –VS = (<Vtn) – 0 VSG = VS – VG = VDD –
= <Vtn (<Vtn) ≈ VDD
Therefore, VGS < Vtn Therefore, VSG > |Vtp|
Therefore, PMOS is ON
Therefore, NMOS is OFF To find the region of operation,
VSD = VS – VD = VDD – VDD
=0
VSG -|Vtp| = VS – VG - |Vtp| =
VDD – (<Vtn) -|Vtp|
=
+Ve value
Therefore, VSD < VSG - |Vtp|
So PMOS is in Linear Region of
Operation

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CMOS Inverter VTC Region of Operation for
MOSFETs
Region Vin Vout NMOS PMOS
Operating Operating
Region Region
A < Vtn VDD Cut Off Linear
B VIL VOH ≈ VDD Saturation Linear
(HIGH)

C VM VM Saturation Saturation

D VIH VOL ≈ GND Linear Saturation

(LOW)

E VDD GND Linear Cut off

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Calculation of Mid Point Voltage VM
• Switching threshold- Point on VTC where Vout = Vin is called midpoint voltage.
• At midpoint voltage Vin = Vout = VM
• Point is found in C region of VTC
• In this C region , both NMOS and PMOS are ON and found to be getting operated in Saturation
region of operation.

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Calculation of Mid Point Voltage VM
• In an Inverter
IDn = IDp
Solve equation for VM

The equation shows that VM is set by the nFET-to-pFET ratio

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Calculation of Mid Point Voltage VM
• If nFET and pFET are of same size then
(W/L)n = (W/L)p
COXn = COXp (always)

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Symmetrical Inverter
• A symmetrical inverter VTC is one that has equal “0” and “1” input voltage ranges.
• This can be achieved by choosing
1
VM = 2 VDD
We know IDn = IDp

1
After substituting VM = 2 VDD

Then

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Dependence of VM on Device Ratio

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 Solved Problem
Example 7.1 Consider a CMOS process with the following parameters-
k’n = 140 µA/V2, VTn = 0.70V, k’p = 60 µA/V2, VTp =- 0.7 V, VDD = 3.0V. Find-
(a) The relative sizes of nFET and pFET for symmetrical inverter.
(b) Midpoint voltage for the inverter with same aspect ratio.
Solution:

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 Assignment 1
1. A CMOS inverter is built in a process where k’n= 100 µA/V2, VTn= 0.70 V, k’p= 42 µA/V2, VTp= - 0.8 V, VDD = 3.3V. Find the midpoint
voltage if (W/L)n = 10 and (W/L)p = 14. (1.48 V)
2. Find the ratio (βn /βp) needed to obtain an inverter midpoint voltage of 1.3 V with a power supply of 3 V. Assume that V Tn= 0.60 V and VTp=
- 0.82 V. What would be the relative device sizes if k’n= 110 µA/V2 and the mobility values are related by µn = 2.2 µp ?
(1.58, (W/L)p = 1.39(W/L)n)

3. State whether the following statements are true or false for the VTC of CMOS inverter shown in figure. (Give proper explanations, prove the
statement if necessary).
a). The mid-point voltage(VM) depends on the threshold voltage of PMOS and NMOS transistors.
b). At VM both the transistors are in triode region.
c). Increasing the threshold voltage of NMOS would decrease the voltage noise margin ( VNML= VIL – VOL).
d). Increasing the size (W/L) of PMOS would move the midpoint voltage upwards.
e). For a symmetrical inverter, which has equal “0” and “1” input voltage ranges, VM = 0.5 VDD

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 CMOS Inverter Transient(Switching) Characteristics-

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CMOS Inverter Transient(Switching) Characteristics-
• The rise and fall time delays are due to the parasitic resistance and capacitances of the transistors.

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CMOS Inverter Transient(Switching) Characteristics-
• Load capacitance
• In a logic chain, every logic gate must drive another or set of logic gates which is known as fan-out
of the circuit.
• The fan-out gates act as a load to the driving circuit because of their input capacitance.

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CMOS Inverter Transient(Switching) Characteristics-

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CMOS Inverter Transient(Switching) Characteristics-

tf = ty - tx

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CMOS Inverter Transient(Switching) Characteristics-

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CMOS Inverter Transient(Switching) Characteristics-
• Maximum Signal Frequency
 This is the largest frequency that can be applied to the gate and still allow the output to settle to a definable
state.

• The Propagation Delay

 Reaction time delay from input to output

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CMOS Inverter-General Analysis

----Fast circuits consume more area than slow circuits ---

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CMOS Inverter-General Analysis
• Normal CMOS Inverter

• For Symmetrical Inverter

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 Solved Problems
Example 7.2. Find the output capacitance in the NOT gate shown in Figure.

Solution :

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 Solved Problems
Example 7.3. Consider an inverter circuit that has FET aspect ratio of (W/L)n = 6 and (W/L)p = 8 in a process where k’n= 150 µA/V2, VTn= 0.7V,
k’p = 62 µA/V2, VTp = - 0.85 V, VDD = 3.3 V. The total output capacitance is estimated to be Cout = 150 fF. Compute rise time, fall
time and maximum signal frequency.
Solution :

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 Assignment 2
1. An inverter uses FETs with βn = 2.1 mA/V2 and βp = 1.8 mA/V2. The threshold voltages are given as Vtn = 0.6 V and Vtp = - 0.7V and the
power supply has a value of VDD = 5 V. The parasitic FET capacitance at the output node is estimated as CFET = 74 fF.
(a) Find the midpoint voltage. (2.378 V)
(b) Find the values of Rn and Rp. (108.23 ohm, 129.2 ohm)
(a) Calculate the rise time and fall times at the output when C L = 0. (21.03ps, 17.62ps)
(b) Calculate the rise time and fall time when an external load of value C L = 115 fF is connected to the output. (53.72ps, 45ps)
(e) Plot rise time and fall time as functions of CL.
2. A CMOS inverter is designed with βp= 80 μA/V2, βn= 0.25 mA/V2, Vtn =|Vtp|= 0.5 V and VDD = 2.5 V. The total capacitance at the
output is 50fF.
(a) Using general expression for MOSFET resistance in saturation, what is the resistance for each transistor? (Rn= 2 Kohm, Rp= 6.25 Kohm)
(b) What is the rise time of this circuit? (685.5ps)
(c) What is the fall time of this circuit? (220ps)
(d) What is the high-to-low propagation delay for this inverter? (69.3ps)
(e) What is the low-to-high propagation delay for this inverter? (217ps)

3. Consider the NOT gate shown in figure of example 1 when an external load of CL = 80fF is connected to the output. The electrical channel
length is L = 0.8 μm.
(a) Find the input capacitance of the circuit. (32.4 fF) Hint :
(b) Find the values of Rn and Rp. (303.03 ohm, 387.6 ohm)
(c) Calculate rise and fall times for the inverter. (111.24ps, 87.04ps)

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CMOS Inverter- Power Dissipation
• The current IDD flowing from power supply to ground gives a dissipated power of-
P = VDDIDD
• The current is divided into DC and dynamic contributions so
P = PDC + Pdyn
DC Power PDC (Static power) –
• When the input voltage Vin stable at logic “0” or logic “1”.

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CMOS Inverter- Power Dissipation
Dynamic Power Dissipation Pdyn (Switching Power)-

• When the input is switching the power dissipated is called dynamic power dissipation.
• A complete cycle of input voltage effectively creates a path for the current to flow from the power supply to
the ground.
• During the first half cycle of input voltage-
 Stored electric charge on the capacitor
Qe = Cout VDD
• During the second half cycle same amount of charge is lost.
• The average power dissipated over a single cycle, of input voltage Vin, with a period T is-
Pav = VDDIDD = VDD (Qe/T)
Pdyn = Cout V2DD f where f = 1/T
Total power
P = VDDIDDQ + Cout V2DD f Power increases with Cout and frequency, and strongly with VDD
“A fast circuit dissipates more power than a slow circuit”
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Series/Parallel Equivalent Circuits-

 Inputs must be at the same value/voltage

Series transistors – increases effective length Parallel transistors – increases effective width

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DC Characteristics – NAND Gate
• NAND Analysis
 Both the pFETs are described by βp and both nFETs have same βn.

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DC Characteristics – NAND Gate
• Series/Parallel Equivalent Circuits-
 Inputs must be at the same value/voltage
Series transistors – increases effective length Parallel transistors – increases effective width

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DC Characteristics – NAND Gate
Midpoint voltage for simultaneous switching condition-

• Both nFET and pFET are in saturation region

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DC Characteristics – NAND Gate

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DC Characteristics – NOR Gate
• NOR Analysis
 Both the pFETs are described by βp and both nFETs have same βn.

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DC Characteristics – NOR Gate
Midpoint voltage for simultaneous switching condition-

• Both nFET and pFET are in saturation region

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 Assignment-3
1. A CMOS NAND2 is designed using identical nFETs with a value of βn = 2βp; the pFETs are the same size. The power supply
is chosen to be
VDD = 5 V and the device threshold voltages are given as VTn = 0.6 V and VTp = -0.7 V.
(a) Find the midpoint voltage VM for the case of simultaneous switching. (2.77 V)
(b) What would be the midpoint voltage for an inverter made with the same β specifications? (2.13 V)

2. A CMOS NOR2 gate is designed using nFETs with a value of βn. The pFETs are both described by βp = 2.2 βn. Find the value
of VM for the case of simultaneous switching if VDD = 3.3 V, VTn = 0.65 V and VTp = - 0.80 V. (1.47 V)

3. A NAND3 gate uses identical nFETs with an aspect ratio of 4. The nFET process transconductance is 120 µA/V2, and the
threshold voltage is 0.55 V. A power supply of 5 V is chosen for the circuit.
Find the value of the pFET βp needed to create a gate where the case of simultaneous switching gives a
midpoint voltage of VM = 2.4 V, Assume that VTp = -0.90 V and r = 2.4. (63.16 µA/V2)

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Gate Design for Transient Performance
• Why Logic Gate Sizing ?
High Speed Circuits are limited by the switching time of individual gates.
Aspect Ratios – Critical Design Parameters for both DC and transient switching
times.
Inverter is used as a reference and then attempt to design other gates that have
approximately the same switching times.

tr = 2.2 Rp Cout tf = 2.2 Rn Cout

tr α Rp tf α Rn

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Gate Design for Transient Performance
• Non Symmetrical Inverter
A non Symmetrical Inverter uses equal size of transistor. Where βn > βp
(W/L)n = (W/L)p
COXn = COXp (always)

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Gate Design for Transient Performance
• Symmetrical Inverter
Generally Symmetrical Inverter (Unit Size Inverter) is used as a sizing reference
in designing any logic function.
For Symmetrical Inverter

That requires, Vtn = |Vtp| and

Where K’ = µ Cox

R n = Rp tr = tf

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Gate Design for Transient Performance
• Identify Symmetrical and Non Symmetrical CMOS Inverter

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Gate Design for Transient Performance
• Symmetrical NAND2 Sizing
Consider parallel pFETS- Worst case

Series-connected nFETs-
where
Using the inverter as a reference, we set

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Gate Design for Transient Performance
• Symmetrical NOR2 Sizing
For parallel nFETs- worst case

For series connected pFETs-

R = Rp = 2RP

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Gate Design for Transient Performance
• Summary

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Gate Design for Transient Performance
• Sizing of 3-Input gates

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Gate Design for Transient Performance
• Answer-

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Gate Design for Transient Performance
• Sizing of Complex function
A CMOS logic gate that implements the function βP1 = 2 βp or βp
Selecting 2 βp leads to
simpler layout since
(a) Design the logic circuit. only a single size P+
(b) An inverter with βn = βp is used as sizing diffusion layer would
reference. Find the device sizes needed to be used.
equalize the nFET and pFET resistances.
Ans. βN = βN1 = 3 βn = 3βp
βP = 2βp
βP1 = 2βp or βp

(c) An inverter with βn = 1.5βp is used as sizing

reference. Find the device sizes needed to
equalize the nFET and pFET resistances.
Ans. βN = βN1 = 3 βn = 4.5βp
βP = 2βp
βP1 = 2βp or βp

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 Assignment-4
1. A CMOS logic gate that implements the function
𝐹 = 𝑥. 𝑦 + 𝑧 + 𝑥. 𝑤
(a) Design the logic circuit.
(b) An inverter with βn = βp is used as sizing reference. Find the device sizes needed to equalize the nFET
and pFET resistances.

2. A CMOS logic gate that implements the function

𝐹 = 𝑎 + 𝑏 . 𝑏 + 𝑐 .𝑑
(a) Design the logic circuit.
(b) An inverter with βn = 1.5 βp is used as sizing reference. Find the device sizes needed to equalize the
nFET and pFET resistances.

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Elmore Delay Calculation
• Consider a general RC tree network,
i) There are no resistor loops in this circuit
ii) All of the capacitors in an RC tree are
connected between a node and the ground
iii) There is one input node in the circuit. Also
notice that there is a unique resistive path,
from the input node to any other node in the circuit.
• Inspecting the general topology of this RC tree network, we can make the
following path definition:
 Let Pi denote the unique path from the input node to node i, i = 1,2,3,…..,N
 Let Pij = Pi Ⴖ Pj denote the portion of the path between the input and the node i, which is
common to the path between the input and node j.
 Assuming that the input signal is a step pulse at time t = 0, the Elmore delay at node i of this
RC tree is given by the following expression.

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Elmore Delay Calculation

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Elmore Delay Calculation

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Elmore Delay Calculation
• Example
• Elmore Delay at node 7 can be calculated as
• τD7 = R7(C7 + C8 ) + R6(C6 + C7 + C8) + R1(C1 + C2 + C3
• + C4 + C5 + C6 +C7 + C8)

• Elmore Delay at node 5 can be calculated as

τD5 = R5C5 + R4(C4 + C5) + R2(C2 + C3 + C4 + C5) + R1(C1
+ C2 + C3 + C4 + C5 + C6 +C7 + C8)

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Elmore Delay Calculation
• Example
Assume N = 8 and solve if R1 = R2 = ……= R8 = 1 K Ohm, and C1 = C2 = …..=
C8 = 2 pF. Find delay at node 8.

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