Scribd
Upload
23 views

2x4 Decoder

The document discusses the design and implementation of a 2:4 line decoder using both CMOS and Pseudo NMOS logic. It explains the functionality of the decoder, which translates binary inputs into unique outputs, and includes truth tables, schematics, and performance comparisons between the two logic types. The results indicate that while Pseudo NMOS logic offers higher speed, it also has increased power consumption compared to CMOS logic.

Uploaded by

Neha Divakar
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
23 views

2x4 Decoder

The document discusses the design and implementation of a 2:4 line decoder using both CMOS and Pseudo NMOS logic. It explains the functionality of the decoder, which translates binary inputs into unique outputs, and includes truth tables, schematics, and performance comparisons between the two logic types. The results indicate that while Pseudo NMOS logic offers higher speed, it also has increased power consumption compared to CMOS logic.

Uploaded by

Neha Divakar
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
You are on page 1/ 9

PROBLEM STATEMENT: Design and implementation of 2:4 line decoder

using CMOS logic and Pseudo NMOS logic

2:4 Decoder

The name “Decoder” means to translate or decode coded information from one
format into another, so a digital decoder transforms a set of digital input signals
into an equivalent decimal code at its output

A decoder is a combinational circuit that converts binary information from n


input lines to a maximum of m=2^n unique output lines.

The 2-to-4 line binary decoder depicted above consists of an array of four AND
gates. The 2 binary inputs labelled A and B are decoded into one of 4 outputs,
hence the description of 2-to-4 binary decoder. Each output represents one of
the minterms of the 2 input variables, (each output = a minterm).

Truth Table:
A B Q3 Q2 Q1 Q0
0 0 0 0 0 1
0 1 0 0 1 0
1 0 0 1 0 0
1 1 1 0 0 0

The binary inputs A and B determine which output line from Q0 to Q3 is


“HIGH” at logic level “1” while the remaining outputs are held “LOW” at logic
“0” so only one output can be active (HIGH) at any one time.

Therefore, whichever output line is “HIGH” identifies the binary code present at
the input, in other words it “decodes” the binary input.Some binary decoders
have an additional input pin labelled “Enable” that controls the outputs from the
device.

This extra input allows the decoders outputs to be turned “ON” or “OFF” as
required. Output is only generated when the Enable input has value 1;
otherwise, all outputs are 0. Only a small change in the implementation is
required: the Enable input is fed into the AND gates which produce the outputs.

If Enable is 0, all AND gates are supplied with one of the inputs as 0 and hence
no output is produced. When Enable is 1, the AND gates get one of the inputs as
1, and now the output depends upon the remaining inputs. Hence the output of
the decoder is dependent on whether the Enable is high or low.
2:4 line decoder using CMOS logic:

AND Schematic

NOT Schematic
2:4 Decoder Schematic

Test Circuit
Results:

2:4 line decoder using Pseudo logic


Pseudo-NMOS logic has the advantage of higher speed than static CMOS logic.
This is due to the fact that there is only one PMOS transistor contributing for
the output rise time. The overall speed improvement is substantial, at the cost of
a slight increase in power consumption.

AND Schematic (Pseudo logic)

OR Schematic (Pseudo logic)


2:4 Decoder Schematic (Pseudo logic)

Test Circuit (Pseudo logic)

Results (Pseudo logic)


Comparison And Conclusion:
CMOS Logic Pseudo NMOS
Logic
Rise time(p) Fall time(p) Rise time Fall time
A 1600 1600 1600 1600
B 800 800 799.9 799.9
D1 92.54 55.08 92.93 55.93
D2 92.45 53.39 92.77 55.81
D3 106.5 58.21 106.5 58.23
D4 123.4 70.63 123.4 70.66

Rise time: Rise time is the time taken for a signal to transition from a low
voltage level (usually 10% of its maximum value) to a high voltage level
(usually 90% of its maximum value).
Fall time: Fall time is the time taken for a signal to transition from a high
voltage level (usually 90% of its maximum value) to a low voltage level
(usually 10% of its maximum value).
In both CMOS and pseudo-NMOS logic, the rise and fall times are very close,
often differing by less than 0.5 ps. This demonstrates that both types of logic
can be designed to have similar transition times under controlled conditions.

CMOS Logic Pseudo NMOS


Logic
Power 0.6599uW 509.6uW
Power dissipation: Pseudo NMOS Logic dissipates more power when compared
to CMOS Logic.
No. of transistors: The number of transistors used in CMOS logic i.e. 28 are
greater than Pseudo NMOS logic i.e. 24.

You might also like