LPC47N217N

56-Pin Super I/O with

LPC Interface

PRODUCT FEATURES Data Brief

„ 3.3 Volt Operation (5V tolerant) „ Multi-Mode Parallel Port with ChiProtect™
„ Programmable Wakeup Event Interface (IO_PME# — Standard Mode IBM PC/XT®, PC/AT®, and PS/2™
Pin) Compatible Bidirectional Parallel Port
— Enhanced Parallel Port (EPP) Compatible - EPP 1.7
„ SMI Support (IO_SMI# Pin) and EPP 1.9 (IEEE 1284 Compliant)
„ GPIOs (13) — IEEE 1284 Compliant Enhanced Capabilities Port
„ Two IRQ Input Pins (ECP)
— ChiProtect Circuitry for Protection Against Damage Due
„ XNOR Chain to Printer Power-On
„ PC2001 — 192 Base I/O Address, 15 IRQ and 3 DMA Options
„ ACPI 2.0 Compliant „ LPC Bus Host Interface
„ 56-pin QFN Lead-free RoHS Compliant package — Multiplexed Command, Address and Data Bus
— 8-Bit I/O Transfers
„ Intelligent Auto Power Management
— 8-Bit DMA Transfers
„ Serial Port — 16-Bit Address Qualification
— One Full Function Serial Port — Serial IRQ Interface Compatible with Serialized IRQ
— High Speed 16C550A Compatible UART with Support for PCI Systems
Send/Receive 16-Byte FIFO — PCI CLKRUN# Support
— Supports 230k and 460k Baud — Power Management Event (IO_PME#) Interface Pin
— Programmable Baud Rate Generator
— Modem Control Circuitry
— Multiple Base I/O Address options and 15 IRQ Options

SMSC LPC47N217N 56QFN PRODUCT PREVIEW Revision 0.3 (09-16-09)

 56-Pin Super I/O with LPC Interface

ORDER NUMBER(S):
LPC47N217N-ABZJ for 56-pin QFN Lead-free ROHS Compliant package
LPC47N217N-ABZJ-TR for 56-pin QFN Lead-free ROHS Compliant package (tape and reel)

80 ARKAY DRIVE, HAUPPAUGE, NY 11788 (631) 435-6000, FAX (631) 273-3123

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Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information sufficient for
construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC
reserves the right to make changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications
before placing your product order. The provision of this information does not convey to the purchaser of the described semiconductor devices any licenses under any patent
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version of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors
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Revision 0.3 (09-16-09) 2 SMSC LPC47N217N 56QFN

PRODUCT PREVIEW
56-Pin Super I/O with LPC Interface

General Description

The SMSC LPC47N217N is a 3.3V PC 99, PC2001, and ACPI 2.0 compliant Super I/O Controller. The
LPC47N217N implements the LPC interface, a pin reduced ISA interface which provides the same or
better performance as the ISA/X-bus with a substantial savings in pins used. The part also includes
13 GPIO pins.

The LPC47N217N incorporates a 16C550A compatible UART and one Multi-Mode parallel port with
ChiProtect™ circuitry plus EPP and ECP support. The LPC47N217N is easy to use and offers lower
system cost and reduced board area.

The LPC47N217N offers a full 16-bit internally decoded address bus, a Serial IRQ interface with PCI
CLKRUN# support, relocatable configuration ports, and three DMA channel options.

The parallel port is compatible with IBM PC/AT architectures, as well as IEEE 1284 EPP and ECP. The
parallel port ChiProtect™ circuitry prevents damage caused by an attached powered printer when the
LPC47N217N is not powered.

The LPC47N217N features Software Configurable Logic (SCL) for ease of use. SCL allows
programmable system configuration of key functions such as the parallel port and UART.

The LPC47N217N supports the ISA Plug-and-Play Standard register set (Version 1.0a) and provides
the recommended functionality to support Windows operating systems, PC99, and PC2001. The I/O
Address, DMA Channel, and Hardware IRQ of each device in the LPC47N217N may be reprogrammed
through the internal configuration registers. There are multiple I/O address location options, a
Serialized IRQ interface, and three DMA channels.

SMSC LPC47N217N 56QFN 3 Revision 0.3 (09-16-09)

PRODUCT PREVIEW
 56-Pin Super I/O with LPC Interface

Block Diagram

PD[0:7],
IO_SMI#* IO_PME# MULTI-MODE BUSY, SLCT,
PARALLEL PE, nERROR, nACK
SMI PME WDT PORT
nSLCTIN, nALF
nINIT, nSTROBE

CONTROL, ADDRESS, DATA

GP10, GP11,
GP12*, GP13*,
GP14*,
GENERAL
GP23,
PURPOSE
GP4[1:7]
I/O

SER_IRQ SERIAL ACPI IRQIN1*, IRQIN2*

IRQ CONFIGURATION BLOCK
PCI_CLK
REGISTERS
LAD0
LAD1 TXD1, nRTS1, nDTR1
LAD2 16C550
LAD3 LPC BUS COMPATIBLE
LFRAME# INTERFACE SERIAL
PORT 1 nCTS1, RXD1,
LDRQ#
nDSR1, nDCD1, nRI1
PCI_RESET#
LPCPD#
CLKRUN#

CLOCK
GEN

V TR Vcc GND CLOCKI

* Denotes Multifunction Pins

Figure 1 LPC47N217N Block Diagram

Revision 0.3 (09-16-09) 4 SMSC LPC47N217N 56QFN

PRODUCT PREVIEW
56-Pin Super I/O with LPC Interface

Package Outline

REVISION HISTORY

REVISION DESCRIPTION DATE RELEASED BY

D D2
A INITIAL RELEASE 2/07/04 S.K.ILIEV

D1 e TERMINAL #1 B REMOVE "PRELIMINARY" NOTE 10/7/04 S.K.ILIEV

IDENTIFIER AREA 3
L(MAX) FROM 0.55 TO 0.50. ADDED D2/E2 VARIATIONS TABLE
(D/2 X E/2) C 7/2/05 S.K.ILIEV

3
TERMINAL #1
IDENTIFIER AREA
(D1/2 X E1/2)

E1 E E2
EXPOSED PAD 2

56X L

56X b 2
4X 45°X0.6 MAX (OPTIONAL)

TOP VIEW BOTTOM VIEW

A A2

A1

SIDE VIEW
D2 / E2 VARIATIONS

CATALOG PART

NOTES:
1. ALL DIMENSIONS ARE IN MILLIMETER.
2. POSITION TOLERANCE OF EACH TERMINAL AND EXPOSED PAD IS ± 0.05mm AT MAXIMUM MATERIAL
CONDITION. DIMENSIONS "b" APPLIES TO PLATED TERMINALS AND IT IS MEASURED BETWEEN 0.15 AND
0.30 mm FROM THE TERMINAL TIP.
3. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL BUT MUST BE LOCATED WITHIN THE AREA INDICATED.

UNLESS OTHERWISE SPECIFIED THIRD ANGLE PROJECTION

DIMENSIONS ARE IN MILLIMETERS
AND TOLERANCES ARE: 80 ARKAY DRIVE
HAUPPAUGE, NY 11788
DECIMAL ANGULAR USA
X.X ±0.1 ±1°
X.XX ±0.05
X.XXX ±0.025
TITLE

PACKAGE OUTLINE
DIM AND TOL PER ASME Y14.5M - 1994 NAME DATE

MATERIAL DRAWN
- S.K.ILIEV 2/06/04 56 TERMINAL QFN, 8x8mm BODY, 0.5mm PITCH
3-D VIEWS
FINISH CHECKED DWG NUMBER REV
- S.K.ILIEV 2/07/04 MO-56-QFN-8x8 C
APPROVED SCALE STD COMPLIANCE SHEET
PRINT WITH "SCALE TO FIT"
DO NOT SCALE DRAWING S.K.ILIEV 2/07/04 1:1 JEDEC: MO-220 1 OF 1

Figure 2 LPC47N217N 56-Pin QFN Package, 8x8mm Body, 0.5mm Pitch

SMSC LPC47N217N 56QFN 5 Revision 0.3 (09-16-09)

PRODUCT PREVIEW