SAL Engineering & Technical Institute

Computer Engineering Department

S eme s ter -6

Microprocessor and Interfacing (3160712)

Study Material
Academic Year: 2023-2024
1. Introduction to Microprocessor
Definition:
• “The microprocessor is a multipurpose, clock driven, register based, digital-integrated
circuit which accepts binary data as input, processes it according to instructions stored in
its memory, and provides results as output.”
• “Microprocessor is a computer Central Processing Unit (CPU) on a single chip that
contains millions of transistors connected by wires.”
Introduction:
• A microprocessor is designed to perform arithmetic and logic operations that make use
of small number-holding areas called registers.
• Typical microprocessor operations include adding, subtracting, comparing two numbers,
and fetching numbers from one area to another.

2. Components of Microprocessor
• Microprocessor is capable of performing various computing functions and making
decisions to change the sequence of program execution.
• The microprocessor can be divided into three segments as shown in the figure,
Arithmetic/logic unit (ALU), register array, and control unit.
• These three segment is responsible for all processing done in a computer

Array
(ALU)

Figure: Components of Microprocessor

Arithmetic and logic unit (ALU)

• It is the unit of microprocessor where various computing functions are performed on
the data.
• It performs arithmetic operations such as addition, subtraction, and logical operations
such as OR,AND, and Exclusive-OR.
• It is also known as the brain of the computer system.
 Register array
• It is the part of the register in microprocessor which consists of various registers
identified by letters such as B, C, D, E, H, and L.
• Registers are the small additional memory location which are used to store and transfer
data and programs that are currently being executed.

Control unit
• The control unit provides the necessary timing and control signals to all the operations
in the microcomputer.
• It controls and executes the flow of data between the microprocessor, memory and
peripherals.
• The control bus is bidirectional and assists the CPU in synchronizing control signals to
internal devices and external components.
• This signal permits the CPU to receive or transmit data from main memory.

3. System bus (data, address and control bus).

• This network of wires or electronic pathways is called the 'Bus'.
• A system bus is a single computer bus that connects the major components of a computer
system.
• It combines the functions of a data bus to carry information, an address bus to determine
where it should be sent, and a control bus to determine its operation.
• The technique was developed to reduce costs and improve modularity.

Figure: System Bus

 Address Bus
• It is a group of wires or lines that are used to transfer the addresses of Memory or I/O
devices.
• It is unidirectional.
• The width of the address bus corresponds to the maximum addressing capacity of the
bus, or the largest address within memory that the bus can work with.
• The addresses are transferred in binary format, with each line of the address bus carrying
a single binary digit.
• Therefore the maximum address capacity is equalto two to the power of the numberof
lines present (2^lines).
Data Bus
• It is used to transfer data within Microprocessor and Memory/Input or Output devices.
• It is bidirectional as Microprocessor requires to send or receive data.
• Each wire is used for the transfer of signals corresponding toa single bit of binary data.
• As such, a greater width allows greater amounts of data to be transferred at the same
time.
Control Bus
• Microprocessor uses control bus to process data, i.e. what to do
with the selected memory location.
• Some control signals are Read, Write and Opcode fetch etc.
• Various operations are performed by microprocessor with the help of control bus.
• This is a dedicated bus, because all timing signals are generated according tocontrol signal.

4. Microprocessor systems with bus organization

Figure: Microprocessor systems with bus organization

• To design any meaningful application microprocessor requires support of other auxiliary
devices.
• In most simplified form a microprocessor based system consist of a microprocessor, I/O
(input/output) devices andmemory.
• These components are interfaced (connected) with microprocessor over a common
communication path called system bus. Typical structure of a microprocessor based
system is shown in Figure.
• Here, microprocessor is master of the system and responsible for executing the program
and coordinating with connected peripherals as required.
• Memory is responsible for storing program as well as data. System generally consists of
two types of memories ROM (Read only and non-volatile) and RAM (Read/Write and
volatile).
• I/O devices are used to communicate with the environment. Keyboard can be example of
input devices and LED, LCD or monitor can be example of output device.
• Depending on the application level of sophistication varies in a microprocessor based
systems. For example: washing machine, computer.
1. Explain Classification of Memory
Ans.

Figure: Classification of Memory

ROM (Read OnlyMemory):
The first classification of memory is ROM. The data in this memory can only beread, no writing
is allowed. It is used to store permanent programs. It is a nonvolatile type of memory.

The classification of ROM memory is as follows:

1. Masked ROM: the program or data are permanently installed at the time of
manufacturing as per requirement. The data cannot be altered. The process of
permanent recording is expensive but economic for large quantities.

2. PROM (Programmable Read Only Memory): The basic function is same as that of
masked ROM. but in PROM, we have fuse links. Depending upon the bit pattern, the
fuse can be burnt or kept intact. This job is performed by PROM programmer.
To do this, it useshigh current pulse between two lines. Because ofhigh current, the
fuse will getburnt; effectively making two lines open. Once a PROM is programmed
we cannot change connections, only a facility provided over masked ROM is, the user
can load his program in it. The disadvantage is a chance of re-growing of the fuse and
changes the programmed data because of aging.
 3. EPROM (Erasable Programmable Read Only Memory): the EPROM is programmable
by the user. It uses MOS circuitry to store data. They store 1’s and 0’s in form of charge.
The information stored can be erased by exposing the memory to ultraviolet light
which erases the data stored in all memory locations. For ultraviolet light, a quartz
window is provided which is covered during normal operation. Upon erasing it can be
reprogrammed by using EPROM programmer. This type of memory is used in a project
developed andforexperiment use. The advantage is it canbe programmed erased and
reprogrammed. The disadvantage is all the data get erased even if you want to change
single data bit.

4. EEPROM: EEPROM stands for electrically erasable programmable read only memory.
This is similar to EPROM except that the erasing is done by electrical signals instead of
ultraviolet light. The main advantage is the memory location can be selectively erased
and reprogrammed. But the manufacturing process is complex and expensive so do
not commonly used.

R/W Memory (Read/Write Memory):

The RAM is also called as read/write memory. The RAM is a volatile type of memory. It
allows the programmer to read or write data. If theuser wants tocheck theexecution ofany
program, user feeds the program in RAM memory and executes it. The result of execution is
then checked by either reading memory location contents or by register contents.

Following is the classification of RAM memory.

It is available in two types:

1. SRAM(Static RAM): SRAM consists of the flip-flop; using either transistor or MOS.
for each bit we require one flip-flop. Bit status will remain as it is; unless and until
you perform next write operation or power supply is switched off.

Advantages of SRAM:
• Fast memory (less access time)
• Refreshing circuit is not required.
Disadvantages of SRAM:
• Low package density
• Costly
 2. DRAM (Dynamic RAM): In this type of memory a data is stored in form of charge in
capacitors. When data is 1, the capacitor will be charged and if data is 0, the
capacitor will not be charged. Because of capacitor leakage currents, the data will
notbeheldbythesecells.SotheDRAMsrequirerefreshingofmemorycells.Itisa
process in which same data is read and written after a fixed interval.

Advantages of DRAM:

• High package density

• Low cost
Disadvantages of DRAM:
• Required refreshing circuit to maintain or refresh charge on the capacitor, every
after few milliseconds.

Secondary Memory
• Magnetic Disk: The Magnetic Disk is Flat, circular platter with metallic coating that
is rotated beneath read/write heads. It isa Random access device; read/write head
can be moved to any location on the platter

• Floppy Disk:Thesearesmall removable disksthat areplastic coatedwithmagnetic

recording material. Floppy disks are typically 3.5″ in size (diameter) and can hold
1.44 MB of data. This portable storage device is a rewritable media and can be
reused a number of times. Floppy disks are commonly used to move files between
different computers. The main disadvantage of floppy disks is that they can be
damaged easily and, therefore, are not very reliable. The following figure shows
an example of the floppy disk. Figure 3 shows a picture of the floppy disk.

• Hard Disk: Another form of auxiliary storage is a hard disk. A hard disk consists of
oneormorerigidmetalplatescoatedwithametaloxidematerialthatallowsdata
tobemagnetically recorded on the surface of the platters. Thehard disk platters
spin at 5 a high rate of speed, typically 5400 to 7200 revolutions per minute
(RPM).Storage capacities of hard disks for personal computers range from 10 GB
to 120 GB (one billion bytes are called a gigabyte).

• Optical Disks: Optical Mass Storage Devices Store bit values as variations in light
reflection. They have higher area density & longer data life than magnetic storage.
They are also standardized and relatively inexpensive. Their Uses: read-only
storage with low performance requirements, applications with high capacity
requirements & where portability in a standardized format is needed.
 Types of Optical Disk
1. CD-ROM (read only)
2. CD-R: (record) to a CD
3. CD-RW: can write and erase CD to reuse it (re-writable)
4. DVD(Digital Video Disk)

2. Explain I/O devices and their Interfacing

Ans. Input /Output (I/O)
• MPU communicates with outside word through I/O device.
• There are 2 different methods by which MPU identifies and communicates With I/O
devices these methods are:
1- Direct I/O(Peripheral)
2- Memory-Mapped I/O
The methods differ in terms of the
• No. of address lines used in identifying an I/O device.
• Type of control lines used to enable the device.
• Instructions used for data transfer.

Direct I/O (Peripheral):-

• This method uses two instructions (IN & OUT) for data transfer.
• MPU uses 8 address lines to send the address of I/O device (can identify 256 input
devices & 256 output devices).
• The (I/P & O/P devices) can be differentiated by control signals I/O Read (IOR) and I/O
Write (IOW).
• The steps in communicating with an I/O device are similar to those in communicating
with memory and can be summarized as follows:
1- The MPU places an 8-bit device address on address bus then decoded.
2- The MPUsendsacontrol signal(IORor IOW)toenablethe I/Odevice.
3- Data are placed on the data bus for transfer.

Memory-Mapped I/O:-
• The MPU uses 16 address lines to identify an I/O device.
• This is similar to communicating with a memory location.
• Usethesamecontrol signals(MEMRorMEMW)andinstructionsasthoseofmemory.
• The MPU views these I/O devices as if they were memory locations.
• There are no special I/O instructions.
• It can identify 64k address shared between memory & I/O devices.
1. Write down main features of 8085 microprocessor.
• It is an 8 bit microprocessor.
• It is manufactured with N-MOS technology.
• It has 16-bit address bus and hence can address up to 216 = 65536 bytes (64KB) memory locations
through A0-A15
• The first 8 lines of address bus and 8 lines of data bus are multiplexed AD0 – AD7
• Data bus is a group of 8 lines D0 – D7
• It supports external interrupt request. .
• A 16 bit program counters (PC)
• A 16 bit stack pointer (SP)
• Six 8-bit general purpose register arranged in pairs: BC, DE, HL.
• It requires a signal +5V power supply and operates at 3.2 MHZ single phase clock.
• It is enclosed with 40 pins DIP (Dual in line package).

2. Explain 8085 microprocessorarchitecture.

Figure: 8085 microprocessor architecture.

• The architecture of microprocessor 8085 can be divided into seven parts as follows:

Register Unit:

General Purpose Data Register

• 8085 has six general purpose data registers to store 8-bit data.
• These registers are named as B, C, D, E, H and L as shown in fig. 1.
• The user can use these registers to store or copy a data temporarily during the execution of a program
by using data transfer instructions.
• These registers are of 8 bits but whenever the microprocessor has to handle 16-bit data, these registers
can be combined as register pairs – BC, DE and HL.
• There are two internal registers – W and X. These registers are only for internal operation like execution
of CALL and XCHG instructions and not available to the user.

Program Counter (PC)

• 16-bit register deals with sequencing the execution of instructions.
• This register is a memory pointer.
• Memory locations have 16-bit addresses which are why this is a 16-bit register.
• The microprocessor uses this register to sequence the execution of the instructions.
• The function of the program counter is to point to the memory address from which the next byte is to be
fetched.
• When a byte (machine code) is being fetched, the program counter is incremented by one to point to
the next memory location.

Stack Pointer (SP)

• SP is also a 16-bit register used as a memory pointer.
• It points to a memory location in R/W memory, called the stack.
• The beginning of the stack is defined by loading 16-bit address in the stack pointer.

MUX/DEMUX unit
• This unit is used to select a register out of all the available registers.
• This unit behaves as a MUX when data is going from the register to the internal data bus.
• It behaves as a DEMUX when data is coming to a register from the internal data bus of the
microprocessor.
• The register select will behave as the function selection lines of the MUX/DEMUX.

Address Buffer Register & Data/Address Buffer Register

• These registers hold the address/data, received from PC/internal data bus and then load the external
address and data buses.
• These registers actually behave as the buffer stage between the microprocessor and external system
buses.
Control Unit:
• The control unit generates signals within microprocessor to carry out the instruction, which has been
decoded.
• In reality it causes connections between blocks of the microprocessor to be opened or closed, so that
the data goes where it is required and the ALU operations occur.
• The control unit itself consists of three parts; the instruction registers (IR), instruction decoder and
machine cycle encoder and timing and control unit.

Instruction Register
• This register holds the machine code of the instruction.
• When microprocessor executes a program it reads the opcode from the memory, this opcode is stored in
the instruction register.

Instruction Decoder & Machine Cycle Encoder

• The IR sends the machine code to this unit.
• This unit, as its name suggests, decodes the opcode and finds out what is to be done in response of the
coming opcode and how many machine cycles are required to execute this instruction.

Timing & Control unit

• The control unit generates signals within microprocessor to carry out the instruction, which has been
decoded.
• In reality, it causes certain connections between blocks of the microprocessor to be opened or closed, so
that the data goes where it is required and the ALU operations occur.

Arithmetic & Logical Unit:

• The ALU performs the actual numerical and logical operation such as ‘add’, ‘subtract’, ‘AND’, ‘OR’, etc.
• ALU uses data from memory and from accumulator to perform the arithmetic operations and always
stores the result of the operation in accumulator.
• ALU consists of accumulator, flag register and temporary register.

Accumulator
• The accumulator is an 8-bit register that is a part of ALU.
• This register is used to store 8-bit data and perform arithmetical and logical operations.
• The result of an operation is stored in the accumulator.
• It is also identified as register A.

Flags register
• Flag register includes five flip-flops, which are set or reset after an operation according to the data
conditions of the result in the accumulator and other registers.
• They are called zero (Z), carry (CY), sign (S), parity (P) and auxiliary carry (AC) flags; their bit positions in
the flag register are shown in fig.
• The microprocessor uses these flags to set and test data conditions.

Interrupt Control
• The interrupt control unit has 5 interrupt inputs TRAP,RST 7.5, RST 6.5, RST 5.5 & INTR and one
acknowledge signal INTA.
• It controls the interrupt activity of 8085 microprocessor.

Serial IO control
• 8085 serial IO control provides two lines, SOD and SID for serial communication.
• The serial output data (SOD) line is used to send data serially and serial input data line (SID) is used to
receive data serially.

3. Explain Flags Registers in 8085

• Flag register includes five flip-flops, which are set or reset after an operation according to the data
conditions of the result in the accumulator and other registers.
• They are called zero (Z), carry (CY), sign (S), parity (P) and auxiliary carry (AC) flags; their bit positions in
the flag register are shown in fig.
• The microprocessor uses these flags to set and test data conditions.

Figure: Flags registers in 8085.

• The flags are stored in the 8-bit register so that the programmer can examine these flags by accessing
the register through an instruction.
• These flags have critical importance in the decision-making process of the microprocessor.
• The conditions (set or reset) of the flags are tested through the software instructions.
• For instance, JC (jump on carry) is implemented to change the sequence of a program when CY flag is
set.

Z (Zero) Flag:
• This flag indicates whether the result of mathematical or logical operation is zero or not.
• If the result of the current operation is zero, then this flag will be set, otherwise reset.

CY (Carry) Flag:
• This flag indicates, whether, during an addition or subtraction operation, carry or borrow is generated or
not, if generated then this flag bit will be set.

AC (Auxiliary Carry) Flag:

• It shows carry propagation from D3 position to D4 position.

1 0 0 0 1 1 0 0

0 0 1 0 1 0 1 1

1 0 1 1 0 1 1 1
 Figure: Auxiliary Carry.

• As shown in the fig., a carry is generated from D3 bit position and propagates to the D4 position. This
carry is called auxiliarycarry.

S (Sign) Flag:
• Sign flag indicates whether the result of a mathematical operation is negative or positive.
• If the result is positive, then this flag will reset and if the result is negative this flag will be set.
• This bit, in fact, is a replica of the D7 bit.

P (Parity) Flag:
• Parity is the number of 1’s in a number.
• If the number of 1’s in a number is even then that number is known as even parity number.
• If the number of 1’s in a number is odd then that number is known as an odd parity number.
• This flag indicates whether the current result is of even parity (set) or of odd parity (reset).
4. Explain 8085 pin diagram.

Figure: 8085 pin diagram.

• All signals can be classified into six groups:

1. Address Bus
2. Data Bus
3. Control & Status Signals
4. Power Supply & Frequency signals
5. Externally initiated signals
6. Serial I/O Ports
1) Address Bus (pin 12 to28)
• 16 signal lines are used as address bus.
• However these lines are split into two segments: A15 - A8 and AD7 - AD0
• A15 - A8 are unidirectional and are used to carry high-order address of 16-bit address.
• AD7 - AD0 are used for dual purpose.

2) Data Bus/ Multiplexed Address (pin 12 to 19)

• Signal lines AD7-AD0 are bidirectional and serve dual purpose.
• They are used as low-order address bus as well as data bus.
• The low order address bus can be separate from these signals by using a latch.

3) Control & Status Signals

• To identify natureof operation
• Two Control Signals
1) RD’ (Read-pin 32)
✓ This is a read control signal (active low)
✓ This signal indicates that the selected I/O or Memory device is to be read & data are available on
data bus.
2) WR’ (Write-pin 31)
✓ This is a write control signal (active low)
✓ This signal indicates that the selected I/O or Memory device is to be write.
• Three Status Signals
1) S1 (pin 33)
2) S0 (pin 29)
✓ S1 and S0 status signals can identify various operations, but they are rarely used in small systems.
S1 S0 Mode
0 0 HLT
0 1 WRITE
1 0 READ
1 1 OPCODE FETCH

3) IO/M’ (pin 34)

✓ This is a status signal used to differentiate I/O and memory operation
✓ When it is high, it indicates an I/O operation
✓ When it is low, it indicates a memory operation
✓ This signal is combined with RD’ and WR’ to generate I/O & memory control signals
• Toindicate beginning of operation
o One Special Signal called ALE (Address Latch Enable-Pin 30)
o This is positive going pulse generated every time the 8085 begins an operation (machine cycle)
o It indicates that the bits on AD7-AD0 are address bits
o This signal is used primarily to latch the low-address from multiplexed bus & generate a separate set
of address lines A7-A0.
4) Power Supply & FrequencySignal
• Vcc→Pin no. 40, +5V Supply
• Vss → Pin no.20, Ground Reference
• X1, X2 → Pin no.1 & 2, Crystal Oscillator is connected at these two pins. The frequency is internally
divided by two;
o Therefore, to operate a system at 3MHz, the crystal should have a frequency of 6MHz.
• CLK (OUT) → Clock output. Pin No.37: This signal can be used as the system clock for other devices.

5) Externally Initiated Signals including Interrupts

• INTR (Input) → Interrupt Request. It is used as general purpose interrupt
• INTA’ (Output) → Interrupt Acknowledge. It is used to acknowledge an interrupt.
• RST7.5, RST6.5, RST5.5 (Input) → Restart Interrupts.
o These are vector interrupts that transfer the program control to specific memory locations.
o They have higher priorities than INTR interrupt.
o Among these 3 interrupts, the priority order is RST7.5, RST6.5, RST5.5
• TRAP (Input) → This is a non maskable interrupt & has the highest priority.
• HOLD (Input) → This signal indicates that a peripheral such as DMA Controller is requesting the use of
address & data buses
• HLDA (Output) → Hold Acknowledge. This signal acknowledges the HOLD request
• READY (Input) → This signal is used to delay the microprocessor read or write cycles until as low-
responding peripheral is ready to send or accept data. When the signal goes low, the microprocessor
waits for an integral no. of clock cycles until it goes high.
• RESET IN’ (Input) → When the signal on this pin goes low, the Program Counter is set to zero, the buses
are tri-stated & microprocessor is reset.
• RESET OUT (Output) → This signal indicates that microprocessor is being reset. The signal can be used to
reset other devices.

6) Serial I/O Ports

• Two pins for serial transmission
1) SID (Serial Input Data-pin 5)
2) SOD (Serial Output Data-pin 4)
• In serial transmission, data bits are sent over a single line, one bit at a time.
5. Explain Instruction Cycle
• Instruction Cycle is defined as time required to complete execution of an instruction.
• 8085 instruction cycle consists of 1 to 6 Machine Cycles or 1 to 6 operations.

Figure: Instruction Cycle.

6. Explain Machine Cycle

• Machine Cycle is defined as time required by the microprocessor to complete operation of accessing
memory device or I/Odevice.
• This cycle may consist 3 to 6 T-states.
• The basic microprocessor operation such as reading a byte from I/O port or writing a byte to memory is
called as machine cycle.

Figure: Machine Cycle.

7. Explain T-States
• T-States are defined as one subdivision of operation performed in one clock period.
• These sub divisions are internal states synchronized with system clock & each T-state is precisely equal
to one clock period.
 Figure: T-States.

8. Compare Instruction Cycle, Machine Cycle and T-States

Figure: Comparison between Instruction Cycle, Machine Cycle and T-States.

• Instruction Cycle: Time required to complete execution of an instruction.

• Machine Cycle: Time required by the microprocessor to complete an operation.
• T-States: One subdivision of operation performed in one clock period.
9. Explain 8085 Programming Model

Figure: 8085 Programming Model.

Registers
• 6 general purpose registers to store 8-bit data B, C, D, E, H & L.
• Can be combined as register pairs – BC, DE, and HL to perform 16-bit operations.
• Used to store or copy data using data copy instructions.

Accumulator
• 8 - bit register, identified as A
• Part of ALU
• Used to store 8-bit data to perform arithmetic & logical operations.
• Result of operation is stored in it.

Flag Register
• ALU has 5 Flag Register that set/reset after an operation according to data conditions of the result in
accumulator & other registers.
• Helpful in decision making process of Microprocessor
• Conditions are tested through software instructions
• For e.g.
• JC (Jump on Carry) is implemented to change the sequence of program when CY is set.

Program Counter
• 16-bit registers used to hold memory addresses.
• Size is 16-bits because memory addresses are of 16-bits.
• Microprocessor uses PC register to sequence the execution of instructions.
• Its function is to point to memory address from which next byte is to be fetched.
• When a byte is being fetched, PC is incremented by 1 to point to next memory location.

Stack Pointer
• Used as memory pointer
• Points to the memory location in R/W memory, called Stack.
• Beginning of stack is defined by loading a 16-bit address in the stack pointer.

10. Explain Bus Organization of 8085

Figure: Bus Organization of 8085.

Address Bus
• Group of 16 lines generally identified as A0 to A15.
• It is unidirectional i.e. bits flow from microprocessor to peripheral devices.
• 16 address lines are capable of addressing 65536 memory locations.
• So, 8085 has 64K memory locations.

Data Bus
• Group of 8 lines identified as D0 to D7.
• They are bidirectional i.e. data flow in both directions between microprocessor, memory & peripheral.
• 8 data lines enable microprocessor to manipulate data ranging from 00H to FFH (28=256 numbers).
• Largest number appear on data bus is 1111 1111 => (255)10.
• As Data bus is of 8-bit, 8085 is known as 8-bit Microprocessor.

Control Bus
• It comprises of various single lines that carry synchronization, timing & control signals.
• These signals are used to identify a device type with which MPU intends to communicate.

11. Explain Demultiplexing AD0-AD7

Figure: Demultiplexing AD0-AD7.

• The higher-order bus remains on the bus for three clock periods. However, the low-order address is lost
after the first clock period.
• This address need to be latched and used for identifying the memory address. If the bus AD7-AD0 is used
to identify the memory location (2005H), the address will change to 204FH after the first clock period.
• Figure shows a schematic that uses a latch and the ALE signal to demultiplex the bus.
• The bus AD7-AD0 is connected as the input to the latch.
• The ALE signal is connected to the Enable pin of the latch, and the output control signal of the latch is
grounded.
• Figure shows that the ALE goes high during T1. And during T1 address of lower-order address bus is store
into the latch.
12. Explain Memory Interfacing
• When we are executing any instruction, we need the microprocessor to access the memory for reading
instruction codes and the data stored in the memory.
• For this, both the memory and the microprocessor requires some signals to read/write to/from registers.
• The interfacing circuit therefore should be designed in such a way that it matches the memory signal
requirements with the signals of the microprocessor.

Memory Read Cycle

Figure: Memory Read Cycle.

• It is used to fetch one byte from the memory.

• It requires 3 T-States.
• It can be used to fetch operand or data from the memory.
• During T1, A8-A15 contains higher byte of address. At the same time ALE is high. Therefore Lower byte
of address A0-A7 is selected from AD0-AD7.
• Since it is memory ready operation, IO/M (bar) goes low.
• During T2 ALE goes low, RD (bar) goes low. Address is removed from AD0-AD7 and data D0-D7 appears
on AD0-AD7.
• During T3, Data remains on AD0-AD7 till RD (bar) is at low signal.
Memory Write Cycle

Figure: Memory Write Cycle.

• It is used to send one byte into memory.

• It requires 3 T-States.
• During T1, ALE is high and contains lower address A0-A7 from AD0-AD7.
• A8-A15 contains higher byte of address.
• As it is memory operation, IO/M (bar) goes low.
• During T2, ALE goes low, WR (bar) goes low and Address is removed from AD0-AD7 and then data
appears on AD0-AD7.
• Data remains on AD0-AD7 till WR (bar) is low.
13. Explain how Control Signals Generated in 8085

Figure: Control Signals Generated in 8085.

• Figure shows that four different control signals are generated by combining the signals RD (bar), WR
(bar), and IO/M (bar).
• The signal IO/M (bar) goes low for the memory operation. This signal is ANDed with RD (bar) and WR
(bar) signals b using the 74LS32 quadruple two-input OR gates, as shown in figure 4.5.
• The OR gates are functionally connected as negative NAND gates. When both input signals go low, the
output of the gates go low and generate MEMR (bar) and MEMW (bar) control signals.
• When the IO/M (bar) signal goes high, it indicates the peripheral I/O operation.
• Figure shows that this signal is complemented using the Hex inverter 74LS04 and ANDed with the RD
(bar) and WR (bar) signals to generate IOR (bar) and IOW (bar) control signals.
1. 8085 instruction set.
Sr. Instruction Description Example
DATA TRANSFER INSTRUCTIONS
1. MOV Rd, Rs This instruction copies the contents of the source MOV B, C
MOV M,Rs register into the destination register; the contents of MOV B, M
MOV Rs, M the source register are not altered. If one of the
operands is a memory location, its location is
specified by the contents of the HL registers.
2. MVIRd, data The 8-bit data is stored in the destination register or MVI B, 57H
MVI M, data memory. If the operand is a memory location, its MVI M, 57H
location is specified by the contents of the HL
registers.
3. LDA16-bit address The contentsof amemorylocation, specifiedby a 16- LDA 2034H
bit address in the operand, are copied to the
accumulator. The contents of the source are not
altered.
4. LDAX B/D Reg. pair The contents of the designated register pair point to LDAX B
a memory location. This instruction copies the
contents of that memory location into the
accumulator. The contents of either the register pair
or the memory location are not altered.
5. LXI Reg.-pair, 16-bit data The instruction loads 16-bit data in the register pair LXI H, 2034H
designated in the operand. LXI H, XYZ
6. LHLD 16-bit address The instruction copies the contents of the memory LHLD 2040H
location pointed out by the 16-bit address into
registerLandcopiesthecontentsofthenextmemory
location into register H. The contents of source
memory locations are not altered.
7. STA 16-bit address The contents of the accumulator are copied into the STA 4350H
memory location specified by the operand. This is a
3-byte instruction, the second byte specifies the low-
order address and the third byte specifies the high-
order address.
8. STAXReg. pair The contents of the accumulator are copied into the STAX B
memory location specified by the contents of the
operand (register pair). The contents of the
accumulator are not altered.
Sr. Instruction Description Example
9. SHLD 16-bit address The contents of register L are stored intothe memory SHLD 2470H
location specified by the 16-bit address in the
operand and the contents of H register are stored
into the next memory location by incrementing the
operand. The contents of registers HL are not altered.
This is a 3-byte instruction, the second byte specifies
the low-order address and thethird byte specifies the
high-order address.
10. XCHG The contents of register H are exchanged with the XCHG
contents of register D, and the contents of register L
are exchanged with the contents of register E.
11. SPHL The instruction loads the contents of the H and L SPHL
registers into the stack pointer register, the contents
of the H register provide the high-order address and
the contents of the L register provide the low-order
address. Thecontents of the H andLregisters are not
altered.
12. XTHL The contents of the Lregister are exchanged withthe XTHL
stack location pointed out by the contents of the
stack pointer register. The contents of the H register
are exchanged with the next stack location (SP+1);
however, the contents of the stack pointer register
are not altered.
13. PUSH Reg. pair The contents of the register pair designated in the PUSH B
operand are copied onto the stack in the following PUSH A
sequence. The stack pointer register is decremented
and the contents of the high order register (B, D, H,
A) are copied into that location. The stack pointer
registeris decrementedagainandthecontents ofthe
low-order register (C, E, L, flags) are copied to that
location.
14. POP Reg. pair The contents of the memory location pointed out by POP H
the stack pointer register are copied to the low-order POP A
register (C, E, L, status flags) of the operand. The stack
pointer is incremented by 1 and the contents of that
memory location are copied to the high-order
register (B, D, H, A) of the operand. The stack pointer
register is again incremented by 1.
15. OUT 8-bit port address The contents of the accumulator are copied into the OUT F8H
I/O port specified by the operand.
16. IN 8CH
IN 8-bit port address The contents of the input port designated in the
operand are read and loaded into the accumulator.
ARITHMETIC INSTRUCTIONS
Sr. Instruction Description Example
17. ADD R The contentsof the operand (register ormemory) are ADDB
ADD M added to the contents of the accumulator and the ADD M
result is stored in the accumulator. If the operand is a
memory location, its location is specified by the
contents of the HL registers. All flags are modified to
reflect the result of the
addition.
18. ADCR The contents of the operand (register or memory) ADCB
ADC M and the Carry flag are added to the contents of the ADCM
accumulator and the result is stored in the
accumulator. If the operand is a memory location, its
location is specified by the contents of the HL
registers. All flags are modified to reflect the result of
the addition.
19. ADI 8-bit data The 8-bit data (operand) is added to the contents of ADI 45H
the accumulator and the result is stored in the
accumulator. All flags are modified to reflect the
result of the addition.
20. ACI 8-bit data The8-bit data(operand) andtheCarryflagareadded ACI 45H
to the contents of the accumulator and the result is
stored in the accumulator. All flags are modified to
reflect the result of the addition.
21. DADReg. pair The 16-bit contents of the specified register pair are DAD H
added to the contents of the HL register and the sum
isstoredintheHLregister.Thecontentsofthesource
register pair are not altered. If the result is larger than
16 bits, the CY flag is set. No other flags are affected.
22. SUB R The contentsof theoperand (register ormemory) are SUBB
SUB M subtractedfromthecontents of theaccumulator, and SUB M
the result is stored in the accumulator. If the operand
is a memory location, its location is specified by the
contents of the HL registers. All flags are modified to
reflect the result of the subtraction.
23. SBB R The contents of the operand (register or memory) SBB B
SBB M and the Borrow flag are subtracted from the contents SBB M
of the accumulator and the result is placed in the
accumulator. If the operand is a memory location, its
location is specified by the contents of the HL
registers. All flags are modified to reflect the result of
the subtraction.
Sr. Instruction Description Example
24. SUI 8-bit data The 8-bit data (operand) is subtracted from the SUI 45H
contents of the accumulator and the result is stored
in the accumulator. All flags are modified to reflect
the result of the subtraction.
25. SBI 8-bit data The 8-bit data (operand) and the Borrow flag are SBI 45H
subtracted from the contents of the accumulator and
the result is stored in the accumulator. All flags are
modified to reflect the result of the subtraction.
26. INR R The contents of the designated register or memory INR B
INRM are incremented by 1 and the result is stored in the INR M
same place. If the operand is a memory location, its
location is specified by the contents of the HL
registers.
27. INXR The contents of the designated register pair are INX H
incremented by 1 and the result is stored in the same
place.
28. DCR R The contents of the designated register or memory DCR B
DCR M are decremented by 1 and the result is stored in the DCR M
same place. If the operand is a memory location, its
location is specified by the contents of the HL
registers.
29. DCXR The contents of the designated register pair are DCX H
decremented by 1 and the result is stored in the same
place.
30. DAA The contents of the accumulator are changed from a DAA
binary value to two 4-bit binary coded decimal (BCD)
digits. This is the only instruction that uses the
auxiliary flag to perform the binary to BCD
conversion, and the conversion procedure is
described below. S, Z, AC, P, CY flags are altered to
reflect the results of the operation.

If the value of the low-order 4-bits in the accumulator

is greater than 9 or if AC flag is set, the instruction
adds 6 to the low-order four bits.

If the value of the high-order 4-bits in the

accumulator is greater than 9 or if the Carryflag is set,
the instruction adds 6 to the high-order four bits.
Sr. Instruction Description Example
BRANCHING INSTRUCTIONS
31. JMP16-bit address The program sequence is transferred to the memory JMP 2034H
location specified by the 16-bit address given in the JMP XYZ
operand.

Jump conditionally The program sequence is transferred to the memory location

specified
by the 16-bit address given in the operand based on the
specified flag of the PSW as described below.
32. JC 16-bit address Jump on Carry, Flag Status: CY=1 JC 2050H
33. JNC 16-bit address Jump on no Carry, Flag Status: CY=0 JNC 2050H
34. JP16-bitaddress Jump on positive, Flag Status: S=0 JP 2050H
35. JM 16-bit address Jump on minus, Flag Status: S=1 JM 2050H
36. JZ16-bitaddress Jump on zero, Flag Status: Z=1 JZ 2050H
37. JNZ 16-bit address Jumponnozero,Flag Status: Z=0 JNZ 2050H
38. JPE 16-bit address Jumponparityeven, FlagStatus: P=1 JPE 2050H
39. JPO 16-bit address Jumponparityodd, Flag Status: P=0 JPO 2050H

40. CALL 16-bit address The program sequence is transferred to the memory CALL 2034H
location specified by the 16-bit address given in the CALL XYZ
operand. Before the transfer, the address of the next
instruction after CALL (the contents of the program
counter) is pushed onto the stack.

Call conditionally The program sequence is transferred to the memory location

specified
by the 16-bit address given in the operand based on the specified
flag of the PSW as described below. Before the transfer, the
address of the next instruction after the call (the contents of the
program counter) is pushed onto the stack.
41. CC 16-bit address Callon Carry, Flag Status: CY=1 CC 2050H
42. CNC 16-bit address Call on no Carry, Flag Status: CY=0 CNC 2050H
43. CP 16-bit address Call on positive, Flag Status: S=0 CP 2050H
44. CM 16-bit address Call on minus, Flag Status: S=1 CM 2050H
45. CZ16-bitaddress Call on zero, Flag Status: Z=1 CZ 2050H
46. CNZ 16-bit address Callonnozero, FlagStatus: Z=0 CNZ 2050H
47. CPE 16-bit address Callonparityeven, FlagStatus:P=1 CPE 2050H
48. CPO 16-bit address Call on parity odd, Flag Status: P=0 CPO 2050H
Sr. Instruction Description Example
49. RET The program sequence is transferred from the RET
subroutine to the calling program. The two bytes
from the top of the stack are copied into the program
counter, and program execution begins at the new
address.

Return from The program sequence is transferred from the subroutine to the
subroutine calling program based on the specified flag of the PSW as
conditionally described below. The two bytes from the top of the stack are
copied into the program counter, and program execution begins
at the new address.
50. RC Return on Carry, Flag Status: CY=1 RC
51. RNC Return on no Carry, Flag Status: CY=0 RNC
52. RP Return on positive, Flag Status: S=0 RP
53. RM Return on minus, Flag Status: S=1 RM
54. RZ Return on zero, Flag Status: Z=1 RZ
55. RNZ Return on no zero, Flag Status: Z=0 RNZ
56. RPE Return on parity even, Flag Status: P=1 RPE
57. RPO Return on parity odd, Flag Status: P=0 RPO

58. PCHL The contents of registers H and L are copied into the PCHL
program counter. The contents of Hare placed asthe
high-order byte and the contents of L as the low-
order byte.
59. RST 0-7 The RST instruction is equivalent to a 1-byte call RST 3
instruction to one of eight memory locations
depending upon the number. The instructions are
generally used in conjunction with interrupts and
inserted using external hardware. However
these can be used as software instructions in a
program to transfer program execution to one of the
eight locations. The addresses are:
Instruction Restart Address
RST 0 0000H
RST 1 0008H
RST 2 0010H
RST 3 0018H
RST 4 0020H
RST 5 0028H
RST 6 0030H
RST 7 0038H
Sr. Instruction Description Example
The 8085 has four additional interrupts and these interrupts generate RST instructions internally
and thus do not require any external hardware.
60. TRAP It restart from address 0024H TRAP
61. RST 5.5 It restart from address 002CH RST 5.5
62. RST 6.5 It restart from address 0034H RST 6.5
63. RST 7.5 It restart from address 003CH RST 7.5
LOGICAL INSTRUCTIONS
64. CMP R The contentsof theoperand (register ormemory) are CMP B
CMP M comparedwiththe contents of the accumulator. Both CMP M
contentsarepreserved.Theresult ofthecomparison
is shown by setting the flags of the PSW as follows:
if (A) < (reg/mem): carry flag is set
if (A) = (reg/mem): zero flag is set
if (A) > (reg/mem): carry and zero flags are reset
65. CPI 8-bit data The second byte (8-bit data) is compared with the CPI 89H
contents of the accumulator. The values being
compared remain unchanged. The result of the
comparison is shown by setting the flags of the PSW
as follows:
if (A) < data: carry flag is set
if (A) = data: zero flag is set
if (A) > data: carry and zero flags are reset
66. ANA R Thecontentsof theaccumulator are logically ANDed ANA B
ANA M with the contents of the operand (register or ANA M
memory), and theresult is placed in the accumulator.
If the operand is a memory location, its address is
specified by the contents of HL registers. S, Z, P are
modified to reflect the result of the operation. CY is
reset. AC is set.
67. ANI 8-bit data The contentsof theaccumulator arelogically ANDed ANI 86H
with the 8-bit data (operand) and the result is placed
in the accumulator. S, Z, P are modified to reflect the
result of the operation. CY is reset. AC is set.
68. XRA R The contents of the accumulator are Exclusive ORed XRA B
XRAM with the contents of the operand (register or XRA M
memory), and the result is placed in the accumulator.
If the operand is a memory location, its address is
specified by the contents of HL registers. S, Z, P are
modified to reflect the result of the operation. CY and
AC are reset.
Sr. Instruction Description Example
69. XRI 8-bit data The contents of the accumulator are Exclusive ORed XRI 86H
with the 8-bit data (operand) and the result is placed
in the accumulator. S, Z, P are modified to reflect the
result of the operation. CY and AC are reset.
70. ORAR The contents of the accumulator are logically ORed ORA B
ORA M with the contents of the operand (register or ORA M
memory), andthe result is placed in the accumulator.
If the operand is a memory location, its address is
specified by the contents of HL registers. S, Z, P are
modified to reflectthe result of the operation. CY and
AC are reset.
71. ORI 8-bit data The contents of the accumulator are logically ORed ORI 86H
with the 8-bit data (operand) and the result is placed
in the accumulator. S, Z, P are modified to reflect the
result of the operation. CY and AC are reset.
72. RLC Each binary bit of the accumulator is rotated left by RLC
one position. Bit D7 is placed in the position of D0 as
well as in the Carry flag. CY is modified according to
bit D7. S, Z, P, AC are not affected.
73. RRC Each binary bit of the accumulator is rotated right by RRC
one position. Bit D0 is placed in the position of D7 as
well as in the Carry flag. CY is modified according to
bit D0. S, Z, P, AC are not affected.
74. RAL Each binary bit of the accumulator is rotated left by RAL
one position through the Carry flag. Bit D7 is placed
in the Carry flag, and the Carry flag is placed in the
least significant position D0. CY is modified according
to bit D7. S, Z, P, AC are not affected.
75. RAR Each binary bit of the accumulator is rotated right by RAR
one position through the Carry flag. Bit D0 is placed
in the Carry flag, and the Carry flag is placed in the
most significant position D7. CY is modified according
to bit D0. S, Z, P, AC are not affected.
76. CMA The contents of the accumulator are complemented. CMA
No flags areaffected.
77. CMC The Carry flag is complemented. No other flags are CMC
affected.
78. STC The Carry flag is set to 1. No other flags are affected. STC
CONTROL INSTRUCTIONS
79. NOP No operation is performed. The instruction is fetched NOP
and decoded. However no operation is executed.
Sr. Instruction Description Example
80. HLT The CPU finishes executing the current instruction HLT
and halts any further execution. An interrupt or reset
is necessary to exit from the halt state.
81. DI The interrupt enable flip-flop is reset and all the DI
interrupts except the TRAP are disabled. No flags are
affected.
82. EI The interrupt enable flip-flop is set and all interrupts EI
are enabled. No flags are affected. After a system
reset or the acknowledgement of an interrupt, the
interrupt enable flip-flop is reset, thus disabling the
interrupts. This instruction is necessary to re enable
the interrupts (exceptTRAP).
83. RIM This is a multipurpose instruction used to read the RIM
status of interrupts 7.5, 6.5, 5.5 and read serial data
input bit. The instruction loads eight bits in the
accumulator with the following interpretations.
D7 D6 D4 D3 D2 D1 D0
SID I7 I6 I5 IE 7.5 6.5 5.5

Serial Input InteSeri

Data bit Interrupts Interrupt
al
masked
pending if Output
if bit=1

84. SIM This is a multipurpose instruction and used to SIM

implementthe8085interrupts 7.5,6.5,5.5,andserial
data output. The instruction interprets the
accumulator contents asfollows.
2. Explain Addressing mode in 8085

1) Immediate Addressing Mode

• In this mode 8/16 bit data is specified in instruction itself as one of its operand.
• Example
MVI B 20H ; 20H is copied into register B.
LXI D 1000H ; 1000H is stored into DE register pair.

2) Direct Addressing Mode

• In this mode 8/16 bit address is directly specified in instruction itself as one of its operand.
• Example
LDA 2000H ; 2000H is memory address.
IN 08H ; 08H is port address.
OUT 10H ; 10H is port address.

3) Register Addressing Mode

• In this mode specifies register or register pair that contains data.
• Example
MOV A B ; A  B.
ADD B ; A=A+B.

4) Indirect Addressing Mode

• In this mode 16 bit memory address is indirectly provided with the instruction using a register pair.
• Example
LDAX D; AM[DE].
STAXD; M[DE]  A.

5) Implicit Addressing Mode

• This mode doesn’t require any operand, data is specified by the Opcode itself.
• Example
CMA
1. Write an ALP to load register B with data 14H, register C with FFH, register
D with 29H and register E with 67H.
MVI B, 14H

MVI C, FFH

MVI D, 29H

MVI E, 67H

HLT

2. Write an ALP to transfer data from register B to C.

MVI B, 55H

MOV C, B

HLT

3. Write an ALP tostoredataofregister B into memory location 2050H.

MVI B, 67H

MOV A, B

STA 2050H ; Store data of Accumulator at memory location 2050H

HLT

4. write an ALP which directly store data 56H into memory location 2050H.
LXI H, 2050H

MVI M, 56H

HLT

5. Write an 8085 assembly language program for exchanging two 8-bit

numbers stored in memory locations 2050h and 2051h.
LDA 2050H

MOV B, A

LDA 2051H

STA 2050H

MOV A, B

STA 2051H

HLT

6. Write an ALP to interchange 16-bit datastored in register BC and DE.

WITHOUT XCHG INSTRUCTION
MOV H, B
 MOV L, C

MOV B, D

MOV C, E

MOV D, H

MOV E, L

HLT

WITH XCHG INSTRUCTION

MOV H, B

MOV L, C

XCHG ; The contents of register H are exchanged with the contents of register D, and the

; contents of register L are exchanged with the contents of register E.

MOV B, H

MOV C, L

HLT

7. Write the set of 8085 assembly language instructions to store the contents of
B and C registers on the stack.
MVI B, 50H

MVI C, 60H

PUSH B

PUSH C

HLT

8. Write an ALP to delete (Make 00H) the data byte stored at memory
location from address stores in register DE.
MVI A, 00H

STAX D

HLT

9. Write an 8085 assembly language program to add two 8-bit numbers stored
in memory locations 2050h and 2051h. Storeresult in location 2052h.
LXI H 2050H

MOV A M

INX H

ADD M
 INX H

MOV M A

HLT

10. Subtract 8 bit data stored at memory location 2050H from data stored at
memory location 2051H and store result at 2052H.
LXI H2050H

MOV A M

INX H

SUB M ; A = A - M

INX H

MOV M A

HLT

11. Write an 8085 assembly language program to add two 16-bit numbers
stored in memory.
LHLD 2050H

XCHG ; The contents of register H are exchanged with the contents of register D, and the

; contents of register L are exchanged with the contents of register E.

LHLD 2052H

MOV A E

ADD L

MOV L A

MOV A D

ADC H

MOV H A

SHLD 2054H ; Store Value of L Register at 2054 and value of H register at 2055.

HLT

12. Write an 8085 assembly languageprogramtofindthenumberof1’sbinary

representation of given 8-bit number.
MVI B 00H

MVI C 08H

MOV A D
 BACK: RAR; Rotate Accumulator Rightthroughcarryflag.

JNC SKIP

INR B

SKIP: DCRC; Incrementof Bwill skip.

JNZ BACK

HLT

13. Implement the Boolean equation D= (B+C) ∙ E, where B, C, D and E

represents data in various registers of 8085.
MOV A B

ORA C

ANA E

MOV D A

HLT

14. Write an 8085 assembly language program to add two decimal numbers
using DAA instruction.
LXI H 2050H

MOV A M

INX H

MOV B M

MVI C 00H

ADD B

DAA ; Decimal adjustment of accumulator.

JNC SKIP

INR C

SKIP: INX H ; Increment of C will skip.

MOV M A

INX H

MOV M C

HLT
15. Write an 8085 assembly language programtofind the minimum from two
8-bit numbers.
LDA 2050H

MOV B A

LDA 2051H

CMP B

JNC SMALL

STA 2052H

HLT

SMALL: MOV A B

STA 2052H

HLT

16. Write an 8085 program to copy block of five numbers starting from
location 2001h to locations starting from 3001h.
LXI D 3100H

MVI C 05H

LXI H 2100

LOOP: MOVAM

STAX D

INX D

INX H

DCR C

JNZ LOOP
1. Draw and explain the block diagram of the programmable peripheral
interface (8255A).
Ans.

Figure: 8255A Architecture

Read Write Control Logic
RD (READ) This is an active low signal that enables Read operation. When signal is
low MPU reads data from selected I/O port of 8255A

WR (WRITE) This is an active low signal that enables Write operation. When signal
is low MPU writes data into selected I/O port or control register

RESET This is an active high signal, used to reset the device. That means clear
control registers

CS This is Active Low signal.

When it is low, then data is transfer from 8085
CS signal is the master Chip Select.
A0 and A1 specify one of the I/O ports or control register
Data Bus Buffer
• Thisthree-state bi-directional 8-bitbuffer is usedto interface the 8255tothe system
data bus.
• Data is transmitted or received by the buffer upon execution of input or output
instructions by the CPU.
• Control words andstatus information are also transferred through the databus buffer.

Group A and Group B Controls

• The functional configuration of each port is programmed by the systems software. In
essence, the CPU "outputs" a control word to the 8255.
• The control word contains information such as"mode","bitset", "bit reset", etc., that
initializes the functional configuration of the 8255.
• Each of the Control blocks (Group A and Group B) accepts "commands" from the
Read/Write Control logic, receives "control words" from the internal data bus and
issues the proper commands to its associated ports.

Ports A, B, and C
• The 8255 contains three 8-bit ports (A, B, and C).
• All can be configured to a wide variety of functional characteristics by the system
software but each has its own special features or "personality" to further enhance the
power and flexibility of the 8255.
• Port A One 8-bit data output latch/buffer and one 8-bit data input latch.
• Both "pull-up" and "pull-down" bus-hold devices are present on Port A.
• Port B One 8-bit data input/output latch/buffer and one 8-bit data input buffer.
• Port C One 8-bit data output latch/buffer and one 8-bitdata input buffer (no latch for
input). This port can be divided into two 4-bit ports under the mode control.
• Each 4-bit port contains a 4-bit latch and it can be used for the control signal output
and status signal inputs in conjunction with ports A and B.
 2. Explain 8255A I/O Operating Modes
Ans. 8255A has three different I/O operating modes:
1. Mode0
2. Mode1
3. Mode2
Mode 0
• Simple I/O for port A,B and C
• In this mode, Port A and B is used as two 8-bit ports and Port C as two 4-bit ports.
• Each portcan be programmed in either inputmode oroutputmode where outputs
are latched and inputs are not latched.
• Ports do not have handshake or interrupt capability.

Mode 1: Input or Output with Handshake

• Handshake signal are exchanged between MPUandperipheral prior todata transfer.
• In this mode, Port A and B is used as 8-bit I/O ports.
• Mode1 is ahandshakeMode whereby ports Aand/or Buse bitsfrom port Cas
handshake signals.
• In the handshake mode, two types of I/O data transfer can be implemented: status
check and interrupt.
• Port A uses upper 3 signals of Port C: PC3, PC4, PC5
• Port B useslower 3 signals of Port C: PC0, PC1, PC2
• PC6 and PC7 are general purpose I/O pins

Figure: Mode1 Input Handshake

STB(StrobeInput):
• This active low signal is generated by a peripheral device to indicate that, it has
transmitted a byte of data. The 8255A, in response to STB, generates IBF and INTR.
 IBF (Input Buffer Full)
This signal is acknowledged by 8255A to indicate that the input latch has received the
data byte. It will get reset when the MPU reads the data.

INTR(Interrupt Request)
This is an output signal that may be used to interrupt the MPU. This signal is generated
if STB, IBF and INTE (internal flip-flop) are all at logic 1. It will get reset by the falling
edge of RD

INTE(Interrupt Enable)
• This signal is an internal flip-flop, used to enable or disable the generation of INTR
signal.
• The interrupt enable signal is neither an input nor an output; it is an internal bit
programmed via the PC4 (port A) or PC2 (port B) bits.

Mode 2
• In this mode, Port A can be configured as the bidirectional port and Port B either in
Mode 0 or Mode 1.
• Port A uses five signals from Port C as handshake signals for data transfer.
• The remaining three signals from Port C can be used either as simple I/O or as
handshake for port B.

3. Explain BSR Mode of the programmable peripheral interface (8255A)

with necessary diagrams.

Ans. • These are two basic modes of operation of 8255.

I/O mode and Bit Set-Reset mode (BSR).
• In I/O mode, the 8255 ports work as programmable I/O ports, while in BSR mode only
port C (PC0-PC7) can be used to set or reset its individual port bits.
• UndertheI/Omodeofoperation,furthertherearethreemodesofoperationof8255,
so as to support different types of applications, mode 0, mode 1 and mode 2.

8255A: BSR(Bit Set/Reset) Mode

• In this mode any of the 8-bits of port C can be set or reset depending on D0 of the
control word.
• The bit to be set or reset is selected by bit select flags D3, D2 and D1 of the CWR (Control
Word Register).
• BSR Control Word affects one bit at a time
• It does not affect the I/O mode
 Figure: BSR Mode Control Word

4. Explain 8255A Control Word and Control Register with necessary

diagram.
Ans. Control Register

Figure: Control Register 8255A

Control Word: Content of Control register is known as Control Word.

• Control word specify an I/O function for each port this register can be.
 Figure:8255A Control Word

• Accessed to write a control word when A0 and A1 are at logic1, the register is not
accessible for a read operation.
• Bit D7 of the control register either specifies the I/O function or the bit Set/Reset
function, as classified in figure 1.
• If bit D7=0, bits D6-D0 determine I/O function in various mode, as shown in figure 4.
• If bit D7=0 port C operates in the bit Set/Reset (BSR) mode.
• The BSR control word does not affect the function of port A and B.

5. What is the need of the programmable interrupt controller (8259A)?

Draw and explain the block diagram of 8259A.
Ans. • The Intel 8259 is a Programmable Interrupt Controller (PIC) designed for use with the
8085 and 8086 microprocessors.
• The 8259 can beused for applications thatusemore than five numbers ofinterrupts
from multiple sources.

The main features of 8259 are listed below

• Manage eight levels of interrupts.
• Eight interrupts are spaced at the interval of four or eight locations.
• Resolve eight levels of priority in fully nested mode, automatic rotation mode or
specific rotation mode.
• Mask each interrupt individually.
• Read the status of pending interrupt, in-service interrupt, and masked interrupt.
• Accept either the level triggered or edge triggered interrupt
 8259 Internal BlockDiagram

Read/Write Logic
• It is typical R/W logic.
• WhenaddresslineA0isatlogic0,thecontrollerisselectedtowriteacommandword
or read status.
• The Chip Select logic and A0 determine the port address of controller.

Control Logic
• It has two pins: INT as output and INTA as input.
• The INT is connected to INTR pin of MPU

Interrupt Registers and Priority Resolver

1. Interrupt Request Register (IRR)
2. Interrupt In-Service Register (ISR)
3. Priority Resolver
4. Interrupt Mask Register (IMR)

Interrupt Request Register (IRR) and Interrupt In-Service Register (ISR)

• Interrupt input lines are handled by two registers in cascade – IRR and ISR
• IRR is used to store all interrupt which are requesting service.
• ISR is used to store all interrupts which are being serviced.
 Priority Resolver
• This logic block determines the priorities of the bit set in IRR.
• IR0 is having highest priority, IR7 is having lowest priority
Interrupt Mask Register
• It stores bits which mask the interrupt lines to be masked
• IMR operates on the IRR.
• Masking of high priority input will not affect the interrupt request lines.

Cascade Buffer /Comparator

This block is used to expand the number of interrupt levels by cascading two or more
8259As.

6. State the difference between the vectored and non-vectored

interrupts. Explain vectored interrupts of the 8085 microprocessor.

Ans. Difference between the vectored and non-vectored interrupts

VECTORED INTERRUPT
• In vectored interrupts, the processor automatically branches to the specific address
in response to an interrupt.
• In vectored interrupts, the manufacturer fixes the address of the ISR to which the
program control is to be transferred.
• The TRAP, RST 7.5, RST 6.5 and RST 5.5 are vectored interrupts.
• TRAP is the only non-maskable interrupt in the 8085.

NON-VECTORED INTERRUPT
• In non-vectored interrupts the interrupted device should give the address of the
interrupt service routine (ISR).
• The INTR is a non-vectored interrupt.
• Hence when a device interrupts through INTR, it has to supply the address of ISR
after receiving interrupt acknowledge signal.
Interrupt Maskable Vectored
INTR Yes No
RST 5.5 Yes Yes
RST 6.5 Yes Yes
RST 7.5 Yes Yes
TRAP No Yes
Explain vectored interrupts of the 8085 microprocessor
The vector addresses of 8085 interrupts are given below:

Software Interrupt Hardware Interrupt

RST 0 0000H RST 7.5 003CH
RST 1 0008H RST 6.5 0034H
RST 2 0010H RST 5.5 002CH
RST 3 0018H TRAP 0024H
RST 4 0020H
RST 5 0028H
RST 6 0030H
RST 7 0038H

Software Interrupt
• The software interrupts of 8085 are RST 0, RST 1, RST 2, RST 3, RST 4, RST 5, RST 6
and RST 7.
• The software interrupts cannot be masked and they cannot be disabled.

Hardware Interrupt
• The vectored hardware interrupts of 8085 are TRAP, RST 7.5, RST 6.5, RST 5.5.
• An external device, initiates the hardware interrupts of 8O85 by placing an appropriate
signal at the interrupt pin of the processor.
• The processor keeps on checking the interrupt pins at the second T -state of last
machine cycle of every instruction.
• If the processor finds a valid interrupt signal and if the interrupt is unmasked and
enabled, then the processor accepts the interrupt.
• The acceptance of the interrupt is acknowledged by sending an INTA signal to the
interrupted device.
• The processor saves the content of PC (program Counter) in stack and then loads the
vector address of the interrupt in PC. (If the interrupt is non-vectored, then the
interrupting devicehas to supplytheaddress of ISRwhen it receives INTA signal).
• It starts executing ISR in this address.
• At the end of ISR, a return instruction, RET will be placed.
• When the processor executesthe RET instruction, it POP the content of top ofstack
to PC.
• Thus the processor control returns to main program after servicing interrupt.
 7. Explain Interfacing Seven-Segment LEDs as an Output
Ans. • Interface the 8085 Microprocessor System with seven segment display through its
programmable I/O port 8255.
• Seven segment displays is often used in the digital electronic equipment todisplay
information regarding certain process.
• I/O devices (orperipherals) such as LEDsand keyboards are essential components of
the microprocessor-based or microcontroller-based systems.
• Seven-segment LEDs Often used todisplay BCD numbers (1 through 9) and a few
alphabets.
• A group of eight LEDs physically mounted in the shape of the number eight plus a
decimal point.
• Each LED is called a segment and labeled as ‘a’ through ‘g’.

Figure: Seven Segment LED

• Commonly used output peripherals in embedded systems are

LEDs, seven-segment LEDs, and LCDs; the simplest is LED

Two ways of connecting LEDs to I/O ports:

1. LED cathodes are grounded and logic 1 from the I/O port turns on the LEDs - The
current is supplied by the I/O port called current sourcing.
2. LEDanodesare connected to thepower supply and logic0 from the I/Oportturns on
the LEDs - The current is received by the chip called current sinking.
 ▪ In a common anode seven-segment LED All anodes are connected together to a
power supply and cathodes are connected to data lines
▪ Logic 0 turns on a segment.
Example:
To display digit 1, so all segments except b and c should be off.

Byte 11111001 = F9H will display digit 1.

 8. Explain I/O interfacing Methods
Ans. There are two method of interfacing memory or I/O devices with the microprocessor are as
follows:
1) I/O mapped I/O
2) Memory mapped I/O

1) I/O MAPPED I/O

• In this technique, I/O device is treated as an I/O device and memory as memory. Each
I/O device uses eight address lines.
• If eight address lines are used to interface to generate the address of the I/O port,
then 256 Input/output devices can be interfaced with the microprocessor.
• The 8085 microprocessor has 16 bit address bus, so we can either use lower order
address lines (A0 – A7) or higher order address lines(A8 – A15) to address I/O devices.
We used lower order address bus & address available on A0 – A7 will be copied on the
address lines A8 – A15.
• In I/O mapped I/O, the complete 64 Kbytes of memory can be used to address memory
locations separately as the address space is not shared with I/O devices.
• In this interface type, thedata transfer is possible between accumulator (A) and I/O
devices only. Arithmetic and logical operation are not possible directly.
• As8bitdeviceaddress used, Addressdecoding issimple so lesshardware is required.
• The separate control signals are used to access I/O devices and memory such as IOR,
IOW for I/O port and MEMR, MEMW for memory hence memory location are
protected from the I/O access.

2) MEMORY MAPPED I/O

• In this technique, I/O devices are treated as memory and memory as memory, hence
the address of the I/O devices are as same as that of memory i.e. 16 bit for 8085
microprocessor.
• So, the address space of the memory i.e. 64 Kbytes willbe shared by the I/O devices
as well as by memory. All 16 address lines i.e. A0-A15 is used to address memory
locations as well as I/O devices.
• The control signals MEMR and MEMW are used to access memory devices as well as
I/O devices.
Comparison of Memory-Mapped I/O and Peripheral Mapped I/O
No Characteristics Memory mapped I/O I/O mapped I/O
1 Device Address 16 bit 8 Bit
2 Control signals for MEMR & MEMW IOR & IOW
inputs
3 Instruction All memory related IN and OUT instructions only
Available instruction : LDA; STA;
LDAX; STAX; MOV M,R;
ADD M; SUB M
4 Data Transfer Between any register and Between I/O device and
I/O devices. Accumulator only.
5 Maximum Numbers Memory Map (64K) is I/OMappedis independentof
of I/Os Possible shared between I/Os and memory map; 256 Input and
System memory. 256 output devices canbe
connected.
6 Execution Speed 13 T-State (LDA, STA, ..) 10 T-State
7 T-State (MOV M,R)
7 Hardware More hardware is needed Less hardware is needed to
Requirement to decode 16 bit address decode 8 bit address
8 Other Feature Arithmetic and logical Not available
operations are directly
performed with I/O
devices.
 8086
1. Draw and explain 8086 Logical Block diagram

Figure: 8086 Architecture

• In 8086 CPU is divided into two independent functional parts BIU and EU.
• Dividing the work between these two units’ speeds up the processing.
BIU (Bus Interface Unit)
Components of BIU
• Instruction queue
It holds the instruction bytes of the next instruction to be executed by EU
• Segment Registers
Four 16-bit register that provides powerful memory management mechanism
• ES (extra segment), CS (code segment), SS (stack segment), DS (data segment).
The size of each register is 64kb.
• Instruction pointer (IP)
Register that holds 16-bit address or offset of next code byte within code segment
• Address Generation and bus control
Generation of 20-bit physical address
Task carried out by BIU
• Fetch instruction from memory
• Read/ Write instruction from / to the memory
• Input/ Output (I/O) of data from / to peripheral ports
• Write the data to memory.
• Address generation for memory reference
• Queuing of instruction (The instruction bytes are transferred to the instruction queue)
• Thus, BUI handles all transfer of data and address on the buses for Execution unit.
• BIU works in synchronous with machine cycles
➢ EU (Execution Unit)
Components of EU

• ALU (Arithmetic logic Unit)

Contains 16-bit ALU, that performs add, subtract, increment, decrement, compliment,
shift binary numbers, AND, OR, XOR etc.
• CU (Control Unit)
Directs internal operation
• Flag Register
16-bit flag register
EU contains 9 active flags
• General PurposeRegisters (GPR)
EU has 4 general purpose 16-bit register
i.e. AX, BX, CX, DX
each register is the combination of two 8-bit register
AH, AL, BH, BL, CH, CL, DH, DL where ‘L’ means Lower byte and ‘H’ means higherbyte.
• Index Register
16-bit Register is SI (source index) and DI (destination index).
Boththeregister areused forstringrelatedoperationand formovingblock ofmemory
from one location to the other.
• Pointers
16-bit Register.
i.e. SP (stack pointer), BP (base pointer)
BP : is used when we need to pass parameter through stack
SP: It always pointstothe top of the stack. Used for sequential access of stack segment.
• Decoder (instruction decoder)
Translates the instruction fetched from into series of action which EU carries out

Task carried out by EU

• Decodes the instruction
• It executes instructions ( executes decoded instructions)
• Tells BIU from where to fetch the instruction
• Decodes instruction (decode the fetched instruction)
• EU takes care of performing operation on the data
• EU is also known as execution heart of the processor
2. Explain 8086 Registers
Ans. The 8086 microprocessor has a total of fourteen registers that are accessible to the programmer as
follows:-
General Purpose Register
AX: - Accumulator register consists of two 8-bit registers AL and AH, which can be combined together
and used as a 16-bit register AX.
- AX works as an intermediate register in memory and I/O operation.
- Accumulator is used for the instruction such as MUL and DIV.
BX:- Base register consists of two 8-bit registers BLand BH, which can be combined together and
used as a 16-bit register BX.
- BX register usually contains a data pointer used for based, based indexed or register indirect
addressing.
CX: - Count register consists of two 8-bit registers CL and CH, which can be combined together and
used as a 16-bit register CX. Count register can be used in Loop, shift/rotate instructions and
as a counter in string manipulation.
DX: - Data register can be used together with AX register to execute MUL and DIV instruction.
- Data register can be used as a port number in I/O operations.

Segment Register
Types of Segment registers are as follows:-
1. Code Segment (CS): The CS register is used for addressing a memory location in the Code Segment
of the memory, where the executable program is stored.
2. Data Segment (DS): The DS contains most data used by program. Data are accessed in the Data
Segment by an offset address or the content of other register that holds the offset address.
3. Stack Segment (SS): SS defined the area of memory used for the stack.
4. Extra Segment (ES): ESis additionaldata segment that isusedby someof the stringto hold the
destination data

Pointer Registers
The pointers IP, BP, SP usually contain offsets within the code, data and stack segments respectively.
1. Stack Pointer (SP): SP is a 16-bit register pointing to program stack in stack segment.
2. Base Pointer (BP): BP is a 16-bit register pointing to data in stack segment. BP register is usually
used for based, based indexed or register indirect addressing.
3. Instruction Pointer (IP): IP is a 16-bit register pointing to next instruction to be executed.

Index registers
The Index Registers are as follows:-
1. Source Index (SI): SI is a 16-bit register used for indexed, based indexed and register indirect
addressing, as well as a source data addresses in string manipulation instructions.
2. Destination Index (DI): DI is a 16-bit register. DI is used for indexed, based indexed and register
indirect addressing, as well as a destination data addresses in string manipulation instructions.
 Flag Registers
The 16-bit flag register of 8086 contains 9 active flags (six conditional & 3 control flags), other 7 flags
are undefined.

3. Draw theformat ofa Flagregister of an 8086 microprocessor.

Figure:8086 Flag Register

• The 16-bit flag register of 8086 contains 9 active flags (six conditional & 3 control flags), other 7
flags are undefined.

• Status Flags: It indicates certain condition that arises during the execution. They are controlled
by the processor.
• Control Flags: It controls certain operations of the processor. They are deliberately set/ reset by
the user.
Control Flags
Control flags are set or reset deliberately to control the operations of the execution unit.
1. Trap Flag (TF):
- It is used for single step control.
- It allows user to execute one instruction of a program at a time for debugging.
- When trap flag is set, program can be run in single step mode.
2. Interrupt Flag (IF):
- It is an interrupt enable/disable flag.
- If it is set, the mask ableinterrupt of 8086 is enabled and if it is reset, theinterrupt is disabled.
- It can be set by executing instruction sit and can be cleared by executing CLI instruction.
3. Direction Flag (DF):
- It is used in string operation.
- If it is set, string bytesare accessed from highermemory address to lower memory address.
- Whenit is reset, the string bytes are accessed from lower memory address to higher memory
address.
 80386
1. Explain the Page Table and Page Directory Entry with paging mechanism in
an 80386 microprocessor.
Page Directory
• The page directory contains the location of up to 1024 page translation tables, which are
each four bytes long.
• Each page translation table translates a logical address into a physical address.
• The page directory is stored in the memory and accessed by the page descriptor address
register (CR3).
• Control register CR3 holds the base address of the page directory, which starts at any 4K-
byte boundary in the memory system.
• Each entry in the page directory translates the leftmost 10 bits of the memory address.
This 10-bit portion of the linear address is used to locate different page tables for different
page table entries.

Page Directory Entry

• Total Page Directory Entries are1024
• Each directory entry is of 4 byte

Figure: Page Directory Entry

Page Table
• The page table contains 1024 physical page addresses, accessed to translate a linear
address into a physical address.
Page Table Entry
• The page table entries contain the starting address of the page and the statistical information
about the page.
• Total Entries are 1024
• Each page table entry is of 4byte

Figure: Page Table Entry

• D-bit: Dirty bit is undefined for page table directory entries by the 80386 microprocessor and
is provided for use by the operating system.
 • A-bit: Accessed bit issettoalogic 1 whenever the microprocessor accesses thepage directory
entry.
• R/W and Read/write and user/supervisor are both used in the protection scheme. Both bits
combine to develop paging priority level protection for level 3, the lowest user level.
U/ R/W Access Level3
S
0 0 None
0 1 None
1 0 Read-Only
1 1 Write-Only

• P-bit:Presentbit,iflogic1 indicatesthattheentrycanbe usedinaddresstranslation.IfP=0,

the entry cannot be used for translation. When P = 0, the remaining bits of the entry can be
used to indicate the location of the page on the disk memory system.

Page Translation Mechanism in 80386

Figure: Page Translation

• A page frame is a 4K-byte unit of contiguous addresses of physical memory. Pages begin on
byte boundaries and are fixed in size.
• A linear address refers indirectly to a physical address by specifying a page table, a page within
that table, and an offset within that page.
• The below figure of page translation shows, how processor converts the DIR, PAGE, and
OFFSET fields of a linear address into the physical address by consulting two levels of page
tables.
• The addressing mechanism uses the DIR field as anindex into a page directory, uses the PAGE
field as an index into the page table determined by the page directory, and uses the OFFSET
field to address a byte within the page determined by the page table.
 • In the second phase of address transformation, the 80386 transforms a linear address into a
physical address.
• This phase of address transformation implements the basic features needed forpage-oriented
virtual-memory systems and page-level protection.
• Page translation is in effect only when the PG bit of CR0 is set.

2. Explain Privilege level.

• There are four types of privilege levels
• 00 - kernel level (highest privilege level)
• 01 - OS services
• 10 - OSextensions
• 11 - Applications (lowest privilege level)

Figure: Privilege Level

• Each task assigned a privilege level, which indicates the priority or privilege of that task.
• It can only change by transferring the control, using gate descriptors, to a new segment.
• A task executing at level 0, the most privileged level, can access all the data segment defined
in GDT and LDT of the task.
• Ataskexecutingat level3,theleastprivileged level,willhavethemostlimitedaccesstodata
and other descriptors.
• The use of rings allows for system software to restrict tasks from accessing data.
• In most environments, the operating system and some device drivers run in ring 0 and
applications run in ring 3.
3. Features of 80386
• The 80386 microprocessor is an enhanced version of the 80286 microprocessor
• Memory-management unit is enhanced to provide memory paging.
• The 80386 also includes 32-bit extended registers and a 32-bit address and data bus.These
extended registers include EAX, EBX, ECX, EDX, EBP, ESP, EDI, ESI, EIP and EFLAGS.
• The 80386 has a physical memory size of 4GBytes that can be addressed as a virtual memory
with up to 64TBytes.
• The 80386 is operated in the pipelined mode, it sends the address of the next instruction or
memory data to the memory system prior to completing the execution of the current
instruction
• This allows the memory system to begin fetching the next instruction or data before the
current is completed. This increases access time.
• The instruction set of the 80386 is enhanced to include instructions that address the 32-bit
extended register set.
• The 80386 memory manager is similar to the 80286, except the physical addresses generated
by the MMU are 32 bits wide instead of 24-bits.
• The concept of paging is introduced in 80386
• 80386 support three operating modes:
1. Real Mode (default)
2. Protected Virtual Address Mode (PVAM)
3. Virtual Mode
• The memory management section of 80386 supports virtual memory, paging and four levels
of protection.
• The 80386 includes special hardware for task switching.

4. Explain the architecture of the 80386 with a neat block diagram.

• The internal architecture of the 80386 includes six functional units that operate in parallel. The
parallel operation is called as pipeline processing.
• Fetching, decoding execution, memory management, and bus access for several instructions
are performed simultaneously.
• The six functional units of the 80386 are
1. Bus Interface Unit
2. Code Pre-fetch Unit
3. Instruction Decoder Unit
4. Execution Unit
5. Segmentation Unit
6. Paging Unit
 Figure: 80386 Architecture

• The Bus Interface Unit connects the 80386 with memory and I/O. Based on internal requests
for fetching instructions and transferring data from the code pre-fetch unit, the 80386
generates the address, data and control signals for the current bus cycles.
• The code pre-fetch unitpre-fetches instructions when the businterface unit is notexecuting
the bus cycles. It then stores them in a 16-byte instruction queue for decoding by the
instruction decode unit.
• The instruction decode unit translates instructions from the pre-fetch queue into micro-codes.
The decoded instructions are then stored in an instruction queue (FIFO) for processing by the
execution unit.
• The execution unit processes the instructions from the instruction queue. It contains a control
unit, a data unit and a protection test unit.
• The control unit contains microcode and parallel hardware for fast multiply, divide and
effective address calculation. The unit includes a 32-bit ALU, 8 general purpose registers and a
64-bit barrel shifter for performing multiple bit shifts in one clock. The data unit carries out
data operations requested by the control unit.
• The protection test unit checks for segmentation violations under the control of microcode.
• Thesegmentation unit calculates andtranslates the logical address into linear addresses at the
request of the execution unit.
 • ackaged in a 168 pin, pin grid array package instead of the 132 pin PGA used for the
80386.
• Operates on 25MHz, 33 MHz, 50 MHz, 60 MHz, 66 MHz or 100MHz.
• It consists of parity generator/checker unit in order to implement parity detection and
generation for memory reads and writes.
• Supports burst memory reads and writes to implement fast cache fills.
• Three mode of operation: real, protected and virtual 8086 mode.
• The 80486 microprocessor is a highly integrated device, containing well over 1.2 million
transistors.
New feature found in the 80486 are as follows:
7. BIST (built-in self-test) that tests the microprocessor
8. 8KB Code and data cache
9. On-chip FPU(Floating Point Unit)

5. Features of Pentium Processor

It consists of all the features that 80486 has. The additional enhancements that Pentium provides
are:
1. Wider data bus width :
• It has 64 bit data bus and 32 bit address bus.
• It allows 8 byte of data info to be transferred to and from memory.
• Bus cycle pipelining hasbeenaddedtoallow two bus cycles to be in progress simultaneously.
2. Improved Cache Structure:
• 8KB dedicated instruction cache which gives instruction to its execution units and floating point
unit via dual instruction pipeline.
• Cache is organized in a 2 way set associate cache with 32 byte line (256 lines).
• 8KB data cache which gives data to its execution unit.
• This allows 32 byte transfer from cache to pre-fetch buffer which is of 64 bytes.
3. Two parallel integer execution unit :
• It allows the execution of two instructions to be executed simultaneously in a single processor
clock.
4. Faster floating point unit :
• The floating point unit has been completely redesigned over 80486.
• Faster algorithms provide up to ten times speed – up for common operations including add,
multiply etc.
5. Branch prediction logic:
• The Pentium uses tech called branch prediction.
• To implement this Pentium hastwo pre-fetch buffers, onetopre-fetch code in linearfashion,
and one that pre-fetches code according to the Branch Target Buffer (BTB).
• Therefore, needed code is almost pre-fetched before it is required for execution.
6. Data Integrity and Error Detection:
• The Pentium have added significant data integrity and error detection capability.
• Data parity checking is still byte-by-byte basis.
• Address parity checking has also been added.
7. Functional Redundancy Checking: (provide maximum error detection)
• Two or more Pentium Processor can participate in functional redundancy checking.
• One processor (the master) fetching the instruction and executes the instruction in normal
fashion.
• Other processor (the checker) (connected directly to the master processor’s buses)verify
correctness of masterprocessor.
• Checker executes the instruction same as the master but doesn’t drive the buses.
• Checker samples master’s output and compares the values with the internal computed values.
An error signal is asserted in case if mismatch occurs.
8. Super Scalar Architecture :
• Processor is capable of parallel instruction execution of multiple instructions are known as
superscalar processors.
• Pentium is capable in some cases of executing two integer of two floating point instruction
simultaneously and thus support superscalar architecture.

Pentium Architecture
The term ''Pentium processor'' refers to a family of microprocessors that share a common
architecture and instruction set. The first Pentium processors were introduced in 1993. It runs at a
clock frequency of either 60 or 66 MHz and has 3.1 million transistors. Some of the features of
Pentium architecture are
• Complex Instruction Set Computer(CISC) architecture with Reduced Instruction Set Computer
(RISC) performance.
• 64-Bit Bus
• Upward code compatibility.
• Pentiumprocessoruses Superscalararchitecture and hencecanissue multipleinstructions per
cycle.
• Multiple Instruction Issue (MII) capability.
• Pentium processor executes instructions in five stages. This staging, or pipelining, allows the
processor to overlap multiple instructions so that it takes less time to execute two instructions
in a row.