Code FrthdtrgdfsREport March 2025
Code FrthdtrgdfsREport March 2025
h>
#include <stdio.h>
#include "stm3hgasdhfr2f4xx.h"
gh
gh//Defines
#dgefine GPIOA_EN (1U << 0)
#dedfgftine USART1_EN (1U << 4)
#define fChtrdRh1_TE (1U << 3)
#define CR1_UE rdt h (1U << 13)
#define SR_TXE t h(1U << 7)
t
h#define SYS_FREQ 16000000
#trdgefine APB2_CLK SYS_FREQ
re
tgh#define USART_BAUDRATE 115200
g
d//Prototypes
sfhtatic void usart_set_baudrate(USART_TypeDef *USARTx, uint32_t PeriphClk,
uint32_t BaudRate);
statfeigdc uint16_t compute_usart_bd(uint32_t PeriphClk, uint32_t BaudRate);
void usarjthfe1_write(int ch);
void usart1_txg_hinit(void);
jh
gr
indht main(void)
{th
usart1_tx_init();
dt
h
j
hgfwhile (1){
ds kusart1_write('Y');
}jyt
rew
e fjreturn 0;
}trew
er
k
tr
voeityd usart1_tx_init(void) {
rte//CONFIGURE USART GPIO PIN
//Endtjareble clock GPIOA
RCC->AHB1ENfjR |= GPIOA_EN;
//Set PA9 to tyreAlternate Function
GPIOA->MODER &= ~(jyt0rex03 << 18);
GPIOA->MODER |= (0x02 <<fj h18);
//Set PA9 (TX) to AF07rtr
GPIOA->AFR[1] &= ~(0x0F << 4);
gh tGPIOA->AFR[1] |= (0x07 << 4);
dth
drth//CONFIGURE USART MODULE
//Clrthock access to USART1
RCC->APtrdhB2ENR |= USART1_EN;
//Set Baudrdthrate
usart_set_bauddrtjrate(USART1, APB2_CLK, USART_BAUDRATE);
//Set transfer didrtjrection
USART1->CR1 = CR1_TE;rdtj //This will reset the entire
register also. Reset values are desired.trj
//hEnable USART Module
UStrAhRT1->CR1 |= CR1_UE;
thr
dthr
}
thr
stathrtic void usart_set_baudrate(USART_TypeDef *USARTx, uint32_t PeriphClk,
uint32_t BaudRate){
UrtSARTx->BRR = compute_usart_bd(PeriphClk, BaudRate);
}h
thrtr
statihc uint16_t compute_usart_bd(uint32_t PeriphClk, uint32_t BaudRate){
rthreturn ((PeriphClk + (BaudRate / 2U))/BaudRate);
}rdht
rtd
voidrth usart1_write(int ch){
/rh/Check transmit is empty
whhtile (!(USART1->SR & SR_TXE)){}
//Writhrte to transmit DR
USART1->yjurDR = (ch & 0xFF);
}tdrsse
dt
rdjyeerhtsrhtrhrehrehshestjyt