Unit-4 ARM Cortex

➢ Draw and explain the architecture of ARM Cortex- M3

Cortex-M3 is a low-power processor that features low gate count, low interrupt latency, and low-cost debug. It is intended
for deeply embedded applications that require FIQ interrupt response features. The Cortex-M3 processor includes:

• A processor core
• A Nested Vectored Interrupt Controller (NVIC) closely integrated with the processor core to achieve low latency
interrupt processing
• Multiple high-performance bus interfaces
• A low-cost debug solution with the optional ability to:
— Implement breakpoints and code patches
— Implement watchpoints, tracing, and system profiling
— Support printf style debugging
— Bridge to a Trace Port Analyzer (TPA)
• An optional Memory Protection Unit (MPU)
• An optional Embedded Trace Macrocell (ETM) that enables reconstruction of program execution.

Interfaces

The processor has the following external interfaces:

• Multiple memory and device bus interfaces

• ETM interface
• Trace port interface
• Debug port interface
• If the implementation includes an ETM, a Cross Trigger Interface (CTI)

Cortex-M3 Components

• Processor
• Nested Vectored Interrupt Controller
• Memory Protection Unit (MPU)
• Cross Trigger Interface Unit
• Debug and Trace
• Debug and Trace
• bus interfaces

The Contex-M3 is 32-bit Microprocessor. It has 32-bit data path, 32-bit register bank and 32-bit memory interfaces.
The Cortex-M3 offers many new features including Thumb-2 Instruction Set and very low power consumption, low
interrupt latency etc. The LPC1768 is microcontroller belongs to Cortex-M3 core. The processor consists of Harvard
Architecture, which means it has separate instruction bus and data bus. This allows instruction and data access take
place at the same time which results in higher performance. However instruction and data buses share same
memory for complex application where more memory is primary need.
 ➢ General Purpose Registers

The Cortex-M3 processor has registers R0 through R15 and a number of special registers. R0 through R12 are general
purpose, but some of the 16-bit Thumb instructions can only access R0 through R7 (low registers), whereas 32-bit Thumb-2
instructions can access all these registers. Special registers have predefined functions and can only be accessed by special
register access instructions.

General Purpose Registers R0 through R7:

The R0 through R7 general purpose registers are also called low registers. They can be accessed by all 16-bit Thumb
instructions and all 32-bit Thumb-2 instructions. They are all 32 bits; the reset value is unpredictable.

General Purpose Registers R8 through R12:

The R8 through R12 registers are also called high registers. They are accessible by all Thumb-2 instructions but not by all 16-
bit Thumb instructions. These registers are all 32 bits; the reset value is unpredictable.

➢ Stack Pointer R13:

R13 is the stack pointer (SP). In the Cortex-M3 processor, there are two SPs. This duality allows two separate stack
memories to be set up.When using the register name R13, you can only access the current SP; the other one is inaccessible
unless one uses special instructions to move to special register from general-purpose register (MSR) and move special
register to general-purpose register (MRS). The two SPs are as follows:

Main Stack Pointer (MSP) or SP_main in ARM documentation:

This is the default SP; it is used by the operating system (OS) kernel, exception handlers, and all application codes that
require privileged access.

Process Stack Pointer (PSP) or SP_ process in ARM documentation:

This is used by the base-level application code (while not running an exception handler).

It is not necessary to use both SPs. Simple applications can rely purely on the MSP. The SPs are used for accessing stack
memory processes such as PUSH and POP.

➢ R14 The link register :

Inside an assembly program, you can write it as either R14 or LR. LR is used to store the return program counter
(PC) when a subroutine or function is called.

R15 The program counter: It has the current program address. This register can be written to control the program flow.

➢ Special Registers:

The Cortex-M3 processor also has a number of special registers. They are as follows: Program Status registers (PSRs)
Interrupt Mask registers (PRIMASK, FAULTMASK,and BASEPRI) Control register (CONTROL) These registers have special
functions and can be accessed only by special instructions. They cannot be used for normal data processing.

The PSRs are subdivided into three status registers:

Application Program Status register (APSR)

Interrupt Program Status register (IPSR)

Execution Program Status register (EPSR)

The three PSRs can be accessed together or separately using the special register access instructions MSR and MRS. When
they are accessed as a collective item, the name xPSR is used one can read the PSRs using the MRS instruction. One can
also change the APSR using the MSR instruction, but EPSR and IPSR are read-only. For example:

MRS r0, APSR ; Read Flag state into R0

MRS r0, IPSR ; Read Exception/Interrupt state.

MRS r0, EPSR ; Read Execution state

MSR APSR, r0 ; Write Flag state

PROGRAM COUNTER

On an ARM Cortex-M3 processor, the program counter (PC) is stored in register R15, meaning this register holds the
memory address of the next instruction to be executed by the processor; essentially, it points to where the program is
currently running.

Key points about the Cortex-M3 program counter:

• Register designation: R15

• Function: Stores the memory address of the next instruction to be executed

• Accessing the PC: Developers can access the program counter directly through register R15 when programming in
assembly language.

In an ARM Cortex-M3 processor, the Program Counter (PC) is a 32-bit register that holds the address of the next instruction
to be executed. Here are key details about the PC in Cortex-M3:

1. Role of Program Counter (PC)

• It stores the address of the next instruction in the instruction memory.

• During normal execution, it increments automatically to fetch sequential instructions.

• When a branch or interrupt occurs, the PC is updated with the target address.

2. Accessing the PC

• The PC is register R15 in the Cortex-M3 architecture.

• You can access it using assembly instructions or C code.

3.Initialization & Reset Behavior

• At reset, the PC is loaded with the value from address 0x00000004 (Vector Table).

• The first instruction to execute is fetched from this location.

4. Program Counter Manipulation

• Direct modification of the PC (R15) causes a jump to a new instruction address.

5. Special Cases

• Interrupt Handling: When an interrupt occurs, the PC is pushed onto the stack, and execution jumps to the ISR
(Interrupt Service Routine).

• Return from Exception: Uses BX LR or POP {PC} to restore execution.

Nested Vectored Interrupt Controller (NVIC)

The Nested Vectored Interrupt Controller (NVIC) in the ARM Cortex-M3 is a crucial component for managing interrupts
efficiently. It provides hardware acceleration for handling exceptions, ensuring low-latency and predictable interrupt
behavior.

Key Features of NVIC in Cortex-M3:

1. Nested Interrupts: Supports prioritized nested interrupts, allowing higher-priority interrupts to preempt lower-
priority ones.
 2. Up to 240 Interrupts: The Cortex-M3 NVIC can handle up to 240 external interrupts with individual
enable/disable and priority settings.

3. Interrupt Prioritization: Supports 256 priority levels (configurable from 8-bit priority fields, typically 3 or 4 bits
used).

4. Vector Table: Uses a vector table to store interrupt service routine (ISR) addresses, enabling direct branching for
fast response.

5. Tail-Chaining: Reduces latency by immediately switching to a pending higher-priority interrupt after executing an
ISR.

6. Late Arrival Handling: If a higher-priority interrupt arrives while handling a lower-priority one, NVIC minimizes
delay in switching.

7. Dynamic Priority Adjustment: Priorities can be changed at runtime using SCB (System Control Block) registers.

8. System Exceptions Handling: Manages faults like HardFault, BusFault, MemManage, and UsageFault.

NVIC Registers:

1. ISER (Interrupt Set-Enable Registers): Enable specific interrupts.

2. ICER (Interrupt Clear-Enable Registers): Disable interrupts.

3. ISPR (Interrupt Set-Pending Registers): Set an interrupt as pending.

4. ICPR (Interrupt Clear-Pending Registers): Clear a pending interrupt.

5. IABR (Interrupt Active Bit Registers): Show active interrupts.

6. IPR (Interrupt Priority Registers): Configure priority levels.

Conclusion:

The NVIC in Cortex-M3 significantly enhances real-time performance by allowing efficient nested interrupts with
minimal latency. This makes it ideal for embedded systems that require fast and deterministic interrupt handling.

Interrupt behavioiur of arm cortex m3

The ARM Cortex-M3 processor has advanced interrupt handling that reduces latency. It has configurable and
unconfigurable interrupts, and an interrupt vector table that stores the entry points of interrupt service routines.

Interrupt behavior

• The processor automatically clears the pending bit when it starts executing an interrupt.
• The processor cannot process the same interrupt again until the interrupt service routine ends.
• If an interrupt source keeps the interrupt request signal active, the interrupt will be pended again.
• If an interrupt is pulsed multiple times before the processor starts processing it, it will be treated as one interrupt
request.

Interrupt types

• Reset: Invoked on power up or a warm reset.

• NMI: A NonMaskable Interrupt that can be triggered by software or a peripheral.
• HardFault: An exception that occurs when there is an error during exception processing.
• SVC: A System Service Call that generates system function calls.
• PendSV: A Pended System Call that is typically used to perform context switching.
Interrupt vector table

The interrupt vector table is stored in a predefined area in memory. It holds an array of memory addresses.

The Cortex-M3 is used in microcontrollers, automotive body systems, and wireless networking and sensors.

Exception programming of arm cortex m3

Exception programming on the ARM Cortex-M3 processor involves configuring exceptions, handling exceptions, and
returning from exceptions.

Configuring exceptions

• Use the System Control Space (SCS) registers to configure exceptions

• Use the Interrupt Control and State Register (ICSR) to control PendSV, NMI, and SysTick exceptions
• Use the Application Interrupt and Reset Control Register (AIRCR) to split exception priorities
• Use the System Handler Priority Register (SHPR1-SHPR3) to update the priority of system faults

Handling exceptions

• The exception model traps illegal memory accesses and incorrect program conditions
• The exception priority and exception mask registers determine if the processor enters the fault handler

Returning from exceptions

• The exception return mechanism is triggered using a special return address called EXC_RETURN
• This value is generated at exception entrance and is stored in the Link Register (LR)
• When the exception return mechanism is triggered, the processor accesses the previously stacked register values
in the stack memory

Advanced programming of the ARM Cortex-M3 processor

The ARM Cortex-M3 has several advanced programming features, including a 32-bit data path, a Harvard architecture, and
Thumb-2 instruction set. It also has a configurable NVIC and supports two modes and two privilege levels.

Features

• Non-maskable interrupts: The Cortex-M3 has non-maskable interrupts and 1 to 240 physical interrupts.
• Sleep modes: The Cortex-M3 has integrated software-controlled sleep modes, including WFI and WFE
instructions, and Sleep On Exit capability.
• Hardware multiply and divide: The Cortex-M3 has hardware single-cycle (32x32) multiply and hardware divide
(2-12 cycles).
• Saturated adjustment: The Cortex-M3 supports saturated adjustment.
• Wake-up interrupt controller: The Cortex-M3 has a wake-up interrupt controller.
• Optional retention mode: The Cortex-M3 has an optional retention mode with the Arm Power Management Kit.

Applications

The Cortex-M3 is used in many applications, including industrial instrument control systems, wireless networking sensors,
and automotive body systems. It's optimized for low-cost microcontroller applications that require low power
consumption.

ARM architecture

The Cortex-M3 is based on the ARMv7-M architecture. ARM is an architecture based on Reduced Instruction Set
Computing (RISC).
Memory Protection Unit (MPU)

The ARM Cortex-M3 processor has an optional Memory Protection Unit (MPU) that protects memory regions. The MPU
can be used to define access permissions for different privilege levels.

The ARM Cortex-M3 processor has a Memory Protection Unit (MPU) that enhances the security and stability of embedded
systems. The MPU helps to protect memory regions by controlling access permissions and preventing tasks from accessing
unauthorized memory areas

How does the MPU work?

• The MPU sets up access rules for privileged access and user program access.
• If a program accesses a memory location that is prohibited by the MPU, the processor generates a fault.
• The fault exception handler can analyze the problem and correct it, if possible.

How can the MPU be used?

• To protect data used by the OS kernel and other privileged processes from untrusted user programs.
• To make memory regions read-only to prevent accidental corruption.
• To make a portion of RAM/SRAM space at the bottom of the stack inaccessible to detect stack overflow.
• To set a RAM/SRAM region to be XN to mitigate code injection attacks.

MPU configuration

• The MPU configuration is based on memory types.

• The MPU can protect up to 16 memory regions.
• The regions can overlap, and can be nested.

In summary, the Memory Protection Unit (MPU) in the ARM Cortex-M3 provides vital protection mechanisms for memory
access in embedded systems. It improves the system's security, stability, and reliability by enforcing strict access controls,
preventing illegal memory accesses, and allowing tasks to run in isolated regions. This ensures that both the hardware and
software work efficiently and safely, particularly in complex, real-time, and safety-critical applications.

Debug architecture

The debug architecture of an ARM Cortex-M3 processor is based on the "CoreSight" architecture, which provides a
standardized way to access and control the processor's debug features through a dedicated interface called the Debug
Access Port (DAP), typically utilizing a low-cost JTAG or SWD (Serial Wire Debug) connection for debugging with external
tools like an IDE; this allows for features like setting breakpoints, reading/writing registers, and accessing memory during
execution.

Key points about the Cortex-M3 debug architecture:

• CoreSight:

The overarching debug technology implemented on the Cortex-M3, enabling comprehensive debug capabilities like
instruction tracing and advanced breakpoint options.

• DAP (Debug Access Port):

The primary interface used to access the debug logic on the processor, allowing communication between the external
debugger and the on-chip debug unit.

• SWJ-DP (Serial Wire JTAG Debug Port):

A common implementation of the DAP interface, providing a simple two-pin connection for debugging (clock and data).
 • Debug Features:
• Breakpoints: Halt execution at specific memory locations to examine code flow.
• Watchpoints: Monitor memory locations for changes in value
• Register Access: Read and write to the processor's internal registers
• Instruction Trace: Capture a sequence of executed instructions for detailed analysis
How it works:
• Debugger connection:
The external debugger (like an IDE) communicates with the Cortex-M3 through the DAP interface using a dedicated debug
probe.
• Control signals:
The debugger sends commands via the DAP to control the debug functionality on the processor, such as setting
breakpoints, reading register values, or initiating a trace session.
• Data transfer:
The processor responds to debug commands by sending data back through the DAP to the debugger.
Benefits of the Cortex-M3 debug architecture:
• Low cost:
The simple SWD interface allows for affordable debugging with readily available debug probes.
• Ease of use:
The standardized CoreSight architecture simplifies the debug process across different Cortex-M3 based microcontrollers.
• Powerful debugging features:
Advanced debugging capabilities like instruction tracing and watchpoints are accessible for in-depth analysis.