[AK7604]

AK7604
Audio DSP with 2chADC + 6chDAC + 8chSRC
1. General Description
The AK7604 is a highly integrated digital signal processor, including a 24-bit stereo ADC with input
selector, three 24-bit stereo DACs, four stereo sampling rate convertors supporting the sampling
frequency up to 192kHz and an Audio DSP. The Audio DSP has 2560step/fs (when fs=48kHz) parallel
processing power and freely programmable for user requirements. The AK7604 is available in a 48-pin
LQFP package.

2. Features

□ Audio DSP:
- Word length: 28-bit (Simple floating point supported)
- Instruction cycle: Max. 8.1ns (2560fs at fs=48kHz)
- Multiplier: 24 x 24 → 48-bit (Double precision arithmetic available)
- Divider: 24 / 24 → 24-bit (Floating point normalization function)
- ALU: 64-bit Arithmetic Operation (with 16bits overflow margin)
- Program RAM: 1024-word x 36-bit
- Coefficient RAM: 1024-word x 24-bit
- Data RAM: 6144-word x 28-bit
□ ADC: 24-bit Stereo ADC with Input Selector
- Sampling Frequency: fs = 8kHz ~ 96kHz
- Input Selector: Differential Stereo Input or Single-end Input or Pseudo Differential Input
with Analog Gain Amplifiers x 1, Single-ended Stereo Input x 2
- Channel Independent Analog Gain Amplifiers (0~18dB(2dB Step), 18~36dB(3dB Step))
- ADC Characteristics S/N: 106dB (fs=48kHz, Differential Input, Analog Gain=0dB)
- Channel Independent Digital Volume Control (24dB ~ -103dB, 0.5dB Step, Mute)
- Digital HPF for DC Offset Cancelling
- 1Vrms Input Full Scale
- Low Noise MIC Power Output x 2
□ DAC: 24-bit DAC
- 2ch x 3
- Sampling Frequency: fs = 8kHz ~ 96kHz
- Single-ended Output
- 1Vrms Output
- DAC Characteristics S/N: 108dB (fs=48kHz)
- Channel Independent Digital Volume Control (12dB ~ -115dB, 0.5dB Step, Mute)
□ SRC:
- 2ch x 4
- FSI = 8kHz ~ 192kHz, FSO = 8kHz ~ 192kHz (FSO/FSI = 0.167 ~ 6.0)
□ Digital Interfaces
- Digital Input Port x 4 (TDM Support: 1 Port)
- Digital Output Port x 3 (TDM Support: 1 Port)
- Independent LRCK/BICK port x 3
- Data Format: MSB 32, 24bit / LSB 24, 20, 16bit / I2S / PCM Short Frame / PCM Long Frame
- TDM Input/Output Mode (Max: 8ch/256fs, fs=96kHz)

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□ PLL Circuit
□ μP Interface: SPI(Max.6MHz) / I2C(400kHz Fast Mode)
□ Power Supply:
Analog: AVDD: 3.0V ~ 3.6V (Typ. 3.3V)
Digital: LVDD: 3.0V ~ 3.6V (Typ. 3.3V) (3.3V → 1.2V Internal Regulator)
I/F VDD33: 3.0V ~ 3.6V (Typ. 3.3V)
TVDD: 1.7V ~ 3.6V (Typ. 3.3V)
□Operating Temperature Range: -40 ~ 85C
□Package: 48-pin LQFP (7mm x 7mm, 0.5mm pitch)

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3. Table of Contents

1. General Description .......................................................................................................................... 1

2. Features ............................................................................................................................................ 1
3. Table of Contents .............................................................................................................................. 3
4. Block Diagrams ................................................................................................................................. 4
■ Block Diagram ..................................................................................................................................... 4
5. Pin Configurations and Functions ..................................................................................................... 5
■ Pin Configurations ............................................................................................................................... 5
■ Pin Functions ....................................................................................................................................... 6
■ Handling of Unused Pins ..................................................................................................................... 8
■ Internal Pulled-down Pins Status ........................................................................................................ 8
■ Power-down Status of Output Pins ..................................................................................................... 9
6. Absolute Maximum Ratings ............................................................................................................ 10
7. Recommended Operating Conditions ............................................................................................ 10
8. Electrical Characteristics..................................................................................................................11
■ Analog Characteristics ........................................................................................................................11
■ Power Consumption .......................................................................................................................... 15
9. Digital Filter Characteristics ............................................................................................................ 16
■ ADC Block.......................................................................................................................................... 16
■ DAC Block ......................................................................................................................................... 17
■ SRC Block ......................................................................................................................................... 21
10. DC Characteristics .......................................................................................................................... 23
11. Switching Characateristics .............................................................................................................. 24
■ System Clock ..................................................................................................................................... 24
■ Power Down ...................................................................................................................................... 24
■ Serial Data Interface (SDIN1 ~ SDIN4, SDOUT1 ~ SDOUT3) ......................................................... 25
■ SPI Interface ...................................................................................................................................... 28
■ I2C Interface ....................................................................................................................................... 30
12. Recommended External Circuits .................................................................................................... 31
■ Connection Diagram .......................................................................................................................... 31
■ Peripheral Circuit ............................................................................................................................... 32
13. Package .......................................................................................................................................... 34
■ Outline Dimensions ........................................................................................................................... 34
■ Material and Lead Finish ................................................................................................................... 34
■ Marking .............................................................................................................................................. 35
14. Ordering Guide................................................................................................................................ 36
15. Revision History .............................................................................................................................. 36
IMPORTANT NOTICE .......................................................................................................................... 37

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4. Block Diagrams

■ Block Diagram

Figure 1. Block Diagram

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5. Pin Configurations and Functions

■ Pin Configurations

LRCK3/JX0/SDIN4

BICK3/JX1

SDIN3/JX2
LRCK1

LRCK2

BICK1

BICK2

SDIN1

SDIN2

TVDD
XTO

XTI

-
36

35

34

33

32

31

30

29

28

27

26

25
VDD33 - 37 24 - VSS2

VSS3 - 38 VDD33 23 SDOUT1

LVDD - 39 22 STO/SDOUT3/GPO

REF12 40 LVDD TVDD 21 TESTI

VSS4 - 41 20 CAD/CSN
AK7604
INN1/GNDINL1 42 19 SI
（Top View）
INP1/AINL1 43 18 SCL/SCLK

INN2/GNDINR1 44 17 SDA/SO

INP2/AINR1 45 16 PDN
AVDD
MPWR1 46 15 DZF/SDOUT2/RDY

MPWR2 47 14 AOUT3R

MPREF 48 13 AOUT3L
10

11

12
1

9
-

-
AVDD
AINL2

AINL3
AINR2

AINR3

VSS1

AOUT1L

AOUT2L
VREFH

AOUT1R

AOUT2R
VCOM

input
output
in/out
- power

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■ Pin Functions
No. Pin Name I/O Function Power Supply
1 AINL2 I Lch Single-ended Input 2 Pin AVDD
2 AINR2 I Rch Single-ended Input 2 Pin AVDD
3 AINL3 I Lch Single-ended Input 3 Pin AVDD
4 AINR3 I Rch Single-ended Input 3 Pin AVDD
Analog Common Voltage Output Pin
Connect a 2.2µF ceramic capacitor between this pin and VSS1.
5 VCOM O AVDD
This pin outputs “L” during power-down state. Do not connect
this pin to an external circuit.
6 AVDD - Analog Power Supply Pin 3.0~3.6V (typ.3.3V) -
7 VSS1 - Ground Pin, 0V -
Analog High-level Reference Voltage Input Pin
8 VREFH - AVDD
Connect this pin to AVDD.
DAC1 Lch Analog Output Pin
9 AOUT1L O AVDD
This pin outputs “Hi-Z” during power-down state.
DAC1 Rch Analog Output Pin
10 AOUT1R O AVDD
This pin outputs “Hi-Z” during power-down state.
DAC2 Lch Analog Output Pin
11 AOUT2L O AVDD
This pin outputs “Hi-Z” during power-down state.
DAC2 Rch Analog Output Pin
12 AOUT2R O AVDD
This pin outputs “Hi-Z” during power-down state.
DAC3 Lch Analog Output Pin
13 AOUT3L O AVDD
This pin outputs “Hi-Z” during power-down state.
DAC3 Rch Analog Output Pin
14 AOUT3R O AVDD
This pin outputs “Hi-Z” during power-down state.
DZF O Soft Defined Zero Detect Pin (GPO0 Output of DSP)
15 SDOUT2 O Serial Data Output 2 Pin TVDD
RDY O RDY Signal Output Pin
Power-Down & Reset Pin
When “L”, the AK7604 is powered-down and the control
16 PDN I registers are reset to default state. TVDD
The PDN pin should be “L” until all power supplies are ON, then
put the PDN pin to “H”.
Serial Data In/Output Pin for I2C I/F
SDA I/O TVDD
This pin outputs “Hi-Z” during power-down state.
17 Serial Data Output Pin for SPI I/F
SO O This pin outputs “Hi-Z” during power-down state. TVDD
This pin must be pulled up or pulled down.
SCL I Serial Data Clock Input Pin for I2C I/F
18 TVDD
SCLK I Serial Data Clock Input Pin for SPI I/F
19 SI I Serial Data Input Pin for SPI I/F TVDD
I2C I/F Chip Address Pin
CAD I
This pin must be pulled up or pulled down.
20 SPI I/F Chip Select Pin TVDD
CSN I During power-down state or when SPI I/F is not in use, leave
this pin “H” level.
Test Input Pin
21 TESTI I TVDD
It must be tied “L”.
Status Output Pin
STO O
This pin outputs “L” during power-down state.
22 TVDD
SDOUT3 O Serial Data Output 3 Pin
GPO O DSP GPO Output Pin (GPO1 Output of DSP)

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No. Pin Name I/O Function Power Supply

23 SDOUT1 O Serial Data Output 1 Pin TVDD
24 VSS2 - Ground Pin, 0V -
25 TVDD - Digital I/F Power Supply Pin 1.7~3.6V (typ.3.3V) -
SDIN3 I Serial Data Input 3 Pin TVDD
26
JX2 I External Conditional Jump Input 2 Pin TVDD
27 SDIN2 I Serial Data Input 2 Pin TVDD
28 SDIN1 I Serial Data Input 1 Pin TVDD
BICK3 I/O Serial Bit Clock 3 Pin TVDD
29
JX1 I External Conditional Jump Input 1 Pin TVDD
30 BICK2 I/O Serial Bit Clock 2 Pin TVDD
31 BICK1 I/O Serial Bit Clock 1 Pin TVDD
LRCK3 I/O LR Channel Select Clock 3 Pin
32 JX0 I External Conditional Jump Input 0 Pin TVDD
SDIN4 I Serial Data Input 4 Pin
33 LRCK2 I/O LR Channel Select Clock 2 Pin TVDD
34 LRCK1 I/O LR Channel Select Clock 1 Pin TVDD
Crystal Oscillator Input Pin
When using a X’tal oscillator, connect it between the XTI and
35 XTI I VDD33
XTO pin.
When not using XTI pin, leave this pin open.
Crystal Oscillator Output Pin
When using a X’tal oscillator, connect it between the XTI and
36 XTO O VDD33
XTO pin.
When not using XTO pin, leave this pin open.
37 VDD33 - Digital Power Supply Pin 3.0~3.6V (typ.3.3V) -
38 VSS3 - Ground Pin 0V -

39 LVDD - Digital Power Supply Pin 3.0~3.6V (typ.3.3V) -

Internal regulator 1.2V Output pin

40 REF12 O Connect a 2.2µF(±30%) ceramic capacitor between this pin LVDD
and VSS4. Do not connect this pin to an external circuit.
41 VSS4 - Ground Pin, 0V -
INN1 I ADC Lch Inverted Differential Input 1 Pin
42 AVDD
GNDINL1 I ADC Lch Pseudo Differential Ground Input 1 Pin
INP1 I ADC Lch Non-inverted Differential Input 1 Pin
43 AVDD
AINL1 I ADC Lch Single-ended Input 1 Pin
INN2 I ADC Rch Inverted Differential Input 2 Pin
44 AVDD
GNDINR1 I ADC Rch Pseudo Differential Ground Input 1 Pin
INP2 I ADC Rch Non-inverted Differential Input 2 Pin
45 AVDD
AINR1 I ADC Rch Single-ended Input 1 Pin
Power Supply Output 1 Pin for Microphone
46 MPWR1 O AVDD
This pin outputs “Hi-Z” during power-down state.
Power Supply Output 2 Pin for Microphone
47 MPWR2 O AVDD
This pin outputs “Hi-Z” during power-down state.
Ripple Filter Pin for Microphone Power Supply
48 MPREF O Connect a 1µF ceramic capacitor between this pin and VSS1. AVDD
Do not connect this pin to an external circuit.

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■ Handling of Unused Pins

Unused I/O pins must be connected appropriately.

Table 1. Handling of Unused Pins

Classification Pin Name Setting
Analog MPREF, MPWR1, MPWR2, INP1/AINL1, Open
INN1/GNDINL1, INP2/AINR1, INN2/GNDINR1, AINL2,
AINR2, AINL3, AINR3, AOUT1L, AOUT1R, AOUT2L,
AOUT2R, AOUT3L, AOUT3R
XTI, XTO, SDOUT1, DZF/SDOUT2/RDY, Open
STO/SDOUT3/GPO
Digital
SDIN3/JX2, SDIN2, SDIN1, LRCK3/JX0/SDIN4, LRCK2, Connect to VSS2/VSS3
LRCK1, BICK3/JX1, BICK2, BICK1, TESTI

■ Internal Pulled-down Pins Status

Table 2. Internal Pulled-down Pins Status

Power Down Status Power Down Release Power Down Release
No. Pin Name PDN pin = “L” PDN pin = “H” PDN pin = “H”
(Slave mode) (Master mode)
21 TESTI Pulled-down (25kΩ) Pulled-down (25kΩ) Pulled-down (25kΩ)
34 LRCK1 Pulled-down (50kΩ) Input (Pulled-down) (46 kΩ) Output
31 BICK1 Pulled-down (50kΩ) Input (Pulled-down) (46 kΩ) Output
33 LRCK2 Pulled-down (50kΩ) Input (Pulled-down) (46 kΩ) Output
30 BICK2 Pulled-down (50kΩ) Input (Pulled-down) (46 kΩ) Output
32 LRCK3/JX0/SDIN4 Pulled-down (50kΩ) Input (Pulled-down) (46 kΩ) Output
29 BICK3/JX1 Pulled-down (50kΩ) Input (Pulled-down) (46 kΩ) Output
23 SDOUT1 Pulled-down (50kΩ) Output Output
15 DZF/SDOUT2/RDY Pulled-down (50kΩ) Output Output
22 STO/SDOUT3/GPO Pulled-down (50kΩ) Output Output
40 REF12 Pulled-down (70Ω) Output Output
Note
* 1. Typical resistance value when LVDD=TVDD=VDD33=3.3V.

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■ Power-down Status of Output Pins

Table 3. Power-down Status of Output Pins

No Pin Name I/O Power-down Status No Pin Name I/O Power-down Status
5 VCOM O “L” Output 31 BICK1 I/O Input
48 MPREF O “L” Output 33 LRCK2 I/O Input
46 MPWR1 O “Hi-Z” Output 30 BICK2 I/O Input
47 MPWR2 O “Hi-Z” Output 32 LRCK3/JX0/SDIN4 I/O Input
9 AOUT1L O “Hi-Z” Output 29 BICK3/JX1 I/O Input
10 AOUT1R O “Hi-Z” Output 17 SDA/SO I/O “Hi-Z” Output
11 AOUT2L O “Hi-Z” Output 23 SDOUT1 O “L” Output (Pulled-down)
12 AOUT2R O “Hi-Z” Output 15 DZF/SDOUT2/RDY O “L” Output (Pulled-down)
13 AOUT3L O “Hi-Z” Output 22 STO/SDOUT3/GPO O “L” Output (Pulled-down)
14 AOUT3R O “Hi-Z” Output 36 XTO O “H” Output
34 LRCK1 I/O Input 40 REF12 O “L” Output (Pulled-down)

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6. Absolute Maximum Ratings

(VSS1=VSS2=VSS3=VSS4=0V * 2)
Parameter Symbol Min. Max. Unit
Power Supplies
Analog AVDD -0.3 4.3 V
Digital1(Core) LVDD -0.3 4.3 V
Digital2(I/F) TVDD -0.3 4.3 V
Digital3(I/F) VDD33 -0.3 4.3 V
Input Current (except power supply pins) IIN － ±10 mA
Analog Input Voltage * 3 VINA -0.3 (AVDD+0.3) or 4.3 V
Digital Input Voltage * 4 VIND1 -0.3 (TVDD+0.3) or 4.3 V
Digital Input Voltage * 5 VIND2 -0.3 (VDD33+0.3) or 4.3 V
Ambient Temperature Ta -40 85 C
Storage Temperature Tstg -65 150 C
Notes
* 2. All voltages are with respect to ground. VSS1-4 must be connected to the same ground.
* 3. The maximum analog input voltage is smaller value between (AVDD+0.3)V and 4.3V.
* 4. The maximum digital input voltage of SDIN1, SDIN2, SDIN3/JX2, LRCK1, BICK1, LRCK2, BICK2,
LRCK3/JX0/SDIN4, BICK3/JX1, PDN, SCL/SCLK, CAD/CSN, SI a、nd TESTI pins is smaller value
between (TVDD+0.3)V and 4.3V.
* 5. The maximum digital input voltage of XTI pin is smaller value between (VDD33+0.3)V and 4.3V.

WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal
operation is not guaranteed at these extremes.

7. Recommended Operating Conditions

(VSS1=VSS2=VSS3=VSS4=0V * 2)
Parameter Symbol Min. Typ. Max. Unit
Power Supplies
Analog AVDD 3.0 3.3 3.6 V
Digital1(Core) LVDD 3.0 3.3 3.6 V
Digital2(I/F) TVDD 1.7 3.3 3.6 V
Digital3(I/F) VDD33 3.0 3.3 3.6 V
Difference1 AVDD – LVDD -0.1 0 0.1 V
Difference2 AVDD – VDD33 -0.1 0 0.1 V
Difference3 LVDD – VDD33 -0.1 0 0.1 V
Difference4 LVDD – TVDD -0.1 - - V
Notes
* 6. The power-up sequence with AVDD, DVDD, TVDD and VDD33 is not critical. The PDN pin should
be held “L” when power is supplied. The PDN pin is allowed to be “H” after all power supplies are
applied and settled.
* 7. Do not turn off the power supply of the AK7604 with the power supply of the peripheral device turned
on. When using the I2C interface, pull-up resistors of SDA and SCL pins should be connected to
TVDD or less voltage.

WARNING: AKM assumes no responsibility for the usage beyond the conditions in the datasheet.

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8. Electrical Characteristics

■ Analog Characteristics

1. MIC AMP
(Ta=25C; AVDD=LVDD=TVDD=VDD33=3.3V; VSS1=VSS2=VSS3=VSS4=0V)
Parameter Min. Typ. Max. Unit
Input Impedance (Full-differential) 17 25 33 kΩ
Input Impedance (Pseudo, Single) 18 26 34 kΩ
MGNL[3:0]bits=0H, MGNR[3:0]bits=0H -1 0 1
MGNL[3:0]bits=1H, MGNR[3:0]bits=1H 1 2 3
MGNL[3:0]bits=2H, MGNR[3:0]bits=2H 3 4 5
MGNL[3:0]bits=3H, MGNR[3:0]bits=3H 5 6 7
MGNL[3:0]bits=4H, MGNR[3:0]bits=4H 7 8 9
MGNL[3:0]bits=5H, MGNR[3:0]bits=5H 9 10 11
MIC
AMP MGNL[3:0]bits=6H, MGNR[3:0]bits=6H 11 12 13
MGNL[3:0]bits=7H, MGNR[3:0]bits=7H 13 14 15
Gain dB
MGNL[3:0]bits=8H, MGNR[3:0]bits=8H 15 16 17
MGNL[3:0]bits=9H, MGNR[3:0]bits=9H 17 18 19
MGNL[3:0]bits=AH, MGNR[3:0]bits=AH 20 21 22
MGNL[3:0]bits=BH, MGNR[3:0]bits=BH 23 24 25
MGNL[3:0]bits=CH, MGNR[3:0]bits=CH 26 27 28
MGNL[3:0]bits=DH, MGNR[3:0]bits=DH 29 30 31
MGNL[3:0]bits=EH, MGNR[3:0]bits=EH 32 33 34
MGNL[3:0]bits=FH, MGNR[3:0]bits=FH 35 36 37

2. MIC Bias Output

(Ta=25C; AVDD=LVDD=TVDD=VDD33=3.3V; VSS1=VSS2=VSS3=VSS4=0V;
Measurement Frequency =20Hz~20kHz)
Parameter Min. Typ. Max. Unit
Output Voltage 2.3 2.5 2.7 V
MIC Bias Load Resistance 2 kΩ
Load Capacitance 30 pF
Output Noise (A-weighted) -114 -108 dBV

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3. MIC AMP + ADC

(Ta=25C; AVDD=LVDD=TVDD=VDD33=3.3V; VSS1=VSS2=VSS3=VSS4=0V; Signal Frequency
=1kHz; 24bit Data; BICK=64fs; @fs=48kHz, Measurement Frequency BW=20Hz ~ 20kHz; @fs=96kHz,
BW=20Hz ~ 40kHz; MGNL/R[3:0] bits=0h (0dB); Differential Input, Unless otherwise specified.)

Parameter Min. Typ. Max. Unit

Resolution 24 Bit
Input Full Scale Differential Input * 12 ±2.55 ±2.83 ±3.11
Vpp
Voltage * 8 Differential Input * 13 ±0.321 ±0.356 ±0.391
Single-ended / Pseudo
2.55 2.83 3.11
Input Full Scale Input * 12
Vpp
Voltage * 9 Single-ended / Pseudo
0.321 0.356 0.391
Input * 13
Input Full Scale
Single-ended Input 2.55 2.83 3.11 Vpp
Voltage * 10
fs=48kHz * 12 85 95
S/(N+D) fs=48kHz * 13 87
MIC AMP dB
(-1dBFS) fs=96kHz * 12 92
+ ADC
fs=96kHz * 13 84
fs=48kHz (A-weighted) * 12 98 106
Dynamic Range fs=48kHz (A-weighted) * 13 95
dB
(-60dBFS) fs=96kHz * 12 99
fs=96kHz * 13 89
fs=48kHz (A-weighted) * 12 98 106
fs=48kHz (A-weighted) * 13 95
S/N dB
fs=96kHz * 12 99
fs=96kHz * 13 89
Inter-Channel Isolation * 11 90 105 dB
Channel Gain Mismatch 0.0 0.3 dB
CMRR * 14 60 80 dB
Notes
* 8. INP1, INN1, INP2 and INN2 pins
* 9. AIN1L and AIN1R pins
* 10. AINL2, AINR2, AINL3, AINR3 pins.
* 11. Inter-channel Isolation with -1dBFS signal input.
* 12. Input full-scale voltage is proportional to AVDD (0.86 x AVDD) when MIC AMP Gain = 0dB.
* 13. Input full-scale voltage is proportional to AVDD (0.108 x AVDD) when MIC AMP Gain = +18dB.
* 14. Common mode rejection ratio when inputting 1kHz, 100mVpp sine wave to both differential inputs.
The value refers to the case when input a 1kHz, ±100mVpp sine wave as differential input.

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4. DAC
(Ta=25C; AVDD=LVDD=TVDD=VDD33=3.3V; VSS1=VSS2=VSS3=VSS4=0V; Signal Frequency
=1kHz; 24bit Data; BICK=64fs; @fs=48kHz, Measurement Frequency BW=20Hz ~ 20kHz; @fs=96kHz,
Measurement Frequency BW=20Hz ~ 40kHz)
Parameter Min. Typ. Max. Unit
Resolution 24 bit
Output Voltage * 15 2.55 2.83 3.11 Vpp
S/(N+D) fs=48kHz 80 91
dB
(0dBFS) fs=96kHz 89
DAC1 Dynamic Range fs=48kHz (A-weighted) 100 108
dB
DAC2 (-60dBFS) fs=96kHz 101
DAC3 fs=48kHz (A-weighted) 100 108
S/N dB
fs=96kHz 101
Inter-Channel Isolation (fin=1kHz) * 16 90 110 dB
Channel Gain Mismatch 0.0 0.7 dB
Load Resistance * 17 10 kΩ
Load Capacitance 30 pF
Notes
* 15. The output voltage when 0dBFS signal input. The output voltage is proportional to AVDD (0.86 x
AVDD).
* 16. Inter-channel isolation between Lch and Rch of each DAC when 0dBFS signal input. (AOUT1L and
AOUT1R, AOUT2L and AOUT2R, and AOUT3L and AOUT3R)
* 17. to AC load

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5. SRC
(Ta=25C; AVDD=LVDD=TVDD=VDD33=3.3V; VSS1=VSS2=VSS3=VSS4=0V; Signal Frequency
=1kHz; 24bit Data; Measurement Frequency BW=20Hz ~ FSO/2)
Parameter Symbol Min. Typ. Max. Unit
Resolution 24 bit
Input Sample Rate FSI 8 192 kHz
(* 18)
Output Sample Rate FSO 8 192 kHz
THD+N (Input=1kHz, 0dBFS)

Audio Mode
(SRCAUDx bit = “1”, x=1~4)
FSO/FSI=192kHz/48kHz -122 dB
FSO/FSI=44.1kHz/48kHz -125 dB
FSO/FSI=48kHz/88.2kHz -122 dB
FSO/FSI=48kHz/96kHz -133 dB
FSO/FSI=44.1kHz/96kHz -116 dB
FSO/FSI=48kHz/192kHz -133 dB
FSO/FSI=8kHz/48kHz -130 dB
Voice Mode
(SRCAUDx bit = “0”, x=1~4)
FSO/FSI=24kHz/32kHz -95 dB
FSO/FSI=16kHz/24kHz -98 dB
FSO/FSI=24kHz/44.1kHz -78 dB
FSO/FSI=16kHz/44.1kHz -69 dB
SRC FSO/FSI=8kHz/32kHz -130 dB
Dynamic Range (Input=1kHz, -60dBFS)

Audio Mode
(SRCAUDx bit = “1” , x=1~4)
FSO/FSI=192kHz/48kHz 132 dB
FSO/FSI=44.1kHz/48kHz 136 dB
FSO/FSI=48kHz/88.2kHz 135 dB
FSO/FSI=48kHz/96kHz 136 dB
FSO/FSI=44.1kHz/96kHz 136 dB
FSO/FSI=48kHz/192kHz 136 dB
FSO/FSI=8kHz/48kHz 130 dB
Voice Mode
(SRCAUDx bit = “0” , x=1~4)
FSO/FSI=24kHz/32kHz 134 dB
FSO/FSI=16kHz/24kHz 137 dB
FSO/FSI=24kHz/44.1kHz 132 dB
FSO/FSI=16kHz/44.1kHz 128 dB
FSO/FSI=8kHz/32kHz 130 dB
Dynamic Range
(Input=1kHz, -60dBFS, A-weighted)
FSO/FSI=44.1kHz/48kHz - 137 - dB
Ratio between Input and Output Sample Rate FSO/FSI 0.167 6 -
Note
* 18. Set FSI Frequency of each operating SRC as the sum of the frequencies is below 384kHz. For
example, if the frequency of FSI is 96kHz, four SRCs can operate at the same time, if the
frequency of FSI is 192kHz, only two SRCs are allowed to operate at the same time.

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■ Power Consumption
(Ta=25C; AVDD=LVDD=VDD33=3.0~3.6V (Typ=3.3V, Max=3.6V); TVDD=1.7~3.6V (Typ=3.3V,
Max=3.6V); VSS1=VSS2=VSS3=VSS4=0V; fs=96kHz; BICK=64fs; Master Mode;
SDOUT1~3/LRCK1~3/BICK1~3=Output; CL=20pF)
Parameter Symbol Min. Typ. Max. Unit
AVDD 28 42 mA
Power-Up * 19 LVDD 14.6 68 mA
(PDN pin = “H”) TVDD 4.5 7 mA
VDD33 2 4 mA
AVDD 1 uA
Power-Down LVDD 10 uA
(PDN pin = “L”) TVDD 1 uA
VDD33 1 uA
Note
* 19. The current of LVDD changes depending on the system frequency and contents of DSP program.

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9. Digital Filter Characteristics

■ ADC Block
(Ta=-40 ~ 85C; AVDD=3.0~3.6V; LVDD=3.0~3.6V; TVDD=1.7~3.6V; VDD33=3.0~3.6V;
VSS1=VSS2=VSS3=VSS4=0V)

fs=48kHz
Parameter Symbol Min. Typ. Max. Unit
SHARP ROLL-OFF
0dB ~ -0.06dB PB 0 22.1 kHz
Passband * 20
-3.0dB PB 23.7 kHz
Stopband * 20 SB 27.8 kHz
Stopband Attenuation SA 85.0 dB
Group Delay Distortion : 0Hz~20kHz GD 0 1/fs
Group Delay * 21 GD 20.0 1/fs
ADC Digital Filter(HPF)
Frequency Response -3.0dB FR 0.9 Hz

fs=96kHz
Parameter Symbol Min. Typ. Max. Unit
SHARP ROLL-OFF
0dB ~ -0.06dB PB 0 44.2 kHz
Passband * 20
-3.0dB PB 47.5 kHz
Stopband * 20 SB 55.6 kHz
Stopband Attenuation SA 85.0 dB
Group Delay Distortion : 0Hz~40kHz GD 0 1/fs
Group Delay * 21 GD 20.0 1/fs
ADC Digital Filter(HPF)
Frequency Response -3.0dB FR 1.9 Hz
Notes
* 20. The passband and stopband frequencies are proportional to fs (sampling rate). High-pass filter
characteristics are not included. A reference value of each gain amplitude is the maximum value of
frequency response.
* 21. Delay time caused by the digital filter calculation. This time is measured from an analog signal input
until 24-bit data of both channels are set into the output register. It includes group delay by HPF.

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■ DAC Block

(Ta=-40 ~ 85C; AVDD=3.0~3.6V; LVDD=3.0~3.6V; TVDD=1.7~3.6V; VDD33=3.0~3.6V;

VSS1=VSS2=VSS3=VSS4=0V)

1. Sharp Roll-Off Filter (DASD bit = “0”, DASL bit = “0”)

fs=48kHz
Parameter Symbol Min. Typ. Max. Unit
SHARP ROLL-OFF
0.05dB PB 0 21.7 kHz
Passband * 22
3.0dB PB 23.4 kHz
Passband Ripple * 23 PR -0.0032 0.0032 dB
Stopband * 22 SB 26.3 kHz
Stopband Attenuation * 25, * 26 SA 80.0 dB
Group Delay * 24 GD 27.3 1/fs
Digital Filter + SCF + SMF * 25
Frequency Response : 0  20.0kHz -0.3 0.1 dB

fs=96kHz
Parameter Symbol Min. Typ. Max. Unit
SHARP ROLL-OFF
0.05dB PB 0 43.5 kHz
Passband * 22
3.0dB PB 46.8 kHz
Passband Ripple * 23 PR -0.0032 0.0032 dB
Stopband * 22 SB 52.5 kHz
Stopband Attenuation * 25, * 26 SA 80.0 dB
Group Delay * 24 GD 27.3 1/fs
Digital Filter + SCF + SMF * 25
Frequency Response : 0  40.0kHz -0.5 0.1 dB
Notes
* 22. The passband and stopband frequencies are proportional to fs (sampling rate).
“PB = 0.4535  fs, SB = 0.546  fs”
* 23. Pass-band gain amplitude of double over sampling filter at the first step of Interpolator.
* 24. Delay time caused by the digital filter calculation. This time is measured from setting of the
16/20/24 impulse data to the input registers to output of the analog peak signal.
* 25. The output level with a 1kHz, 0dB sine wave input is defined as 0dB.
* 26. Band width of Stopband Attenuation ranges from 0Hz to fs.

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2. Slow Roll-Off Filter (DASD bit = “0”, DASL bit = “1”)

fs=48kHz
Parameter Symbol Min. Typ. Max. Unit
SLOW ROLL-OFF
0.05dB PB 0 8.8 kHz
Passband * 27
3.0dB PB 19.8 kHz
Passband Ripple * 23 PR -0.043 0.043 dB
Stopband * 27 SB 42.7 kHz
Stopband Attenuation * 25, * 26 SA 73.0 dB
Group Delay * 24 GD 6.8 1/fs
Digital Filter + SCF + SMF * 25
Frequency Response : 0  20.0kHz -5.0 0.1 dB

fs=96kHz
Parameter Symbol Min. Typ. Max. Unit
SLOW ROLL-OFF
0.05dB PB 0 17.7 kHz
Passband * 27
3.0dB PB 39.5 kHz
Passband Ripple * 23 PR -0.043 0.043 dB
Stopband * 27 SB 85.3 kHz
Stopband Attenuation * 25, * 26 SA 73.0 dB
Group Delay * 24 GD 6.8 1/fs
Digital Filter + SCF + SMF * 25
Frequency Response : 0  40.0kHz -5.2 0.1 dB
Note
* 27. The passband and stopband frequencies are proportional to fs (sampling rate).
“PB = 0.185  fs, SB = 0.888  fs”

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3. Short Delay Sharp Roll-Off Filter (DASD bit = “1”, DASL bit = “0”)

fs=48kHz
Parameter Symbol Min. Typ. Max. Unit
SHORT DELAY SHARP ROLL-OFF
0.05dB PB 0 21.7 kHz
Passband * 22
3.0dB PB 23.4 kHz
Passband Ripple * 23 PR -0.0031 0.0031 dB
Stopband * 22 SB 26.3 kHz
Stopband Attenuation * 25, * 26 SA 80.0 dB
Group Delay * 24 GD 6.3 1/fs
Digital Filter + SCF + SMF * 25
Frequency Response : 0  20.0kHz -0.3 0.1 dB

fs=96kHz
Parameter Symbol Min. Typ. Max. Unit
SHORT DELAY SHARP ROLL-OFF
0.05dB PB 0 43.5 kHz
Passband * 22
3.0dB PB 46.8 kHz
Passband Ripple * 23 PR -0.0031 0.0031 dB
Stopband * 22 SB 52.5 kHz
Stopband Attenuation * 25, * 26 SA 80.0 dB
Group Delay * 24 GD 6.3 1/fs
Digital Filter + SCF + SMF * 25
Frequency Response : 0  40.0kHz -0.5 0.1 dB

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4. Short Delay Slow Roll-Off Filter (DASD bit = “1”, DASL bit = “1”)

fs=48kHz
Parameter Symbol Min. Typ. Max. Unit
SHORT DELAY SLOW ROLL-OFF
0.05dB PB 0 12.0 kHz
Passband * 28
3.0dB PB 21.1 kHz
Passband Ripple * 23 PR -0.05 0.05 dB
Stopband * 28 SB 41.5 kHz
Stopband Attenuation * 25, * 26 SA 82.0 dB
Group Delay * 24 GD 5.3 1/fs
Digital Filter + SCF + SMF * 25
Frequency Response : 0  20.0kHz -4.8 0.1 dB

fs=96kHz
Parameter Symbol Min. Typ. Max. Unit
SHORT DELAY SLOW ROLL-OFF
0.05dB PB 0 24.2 kHz
Passband * 28
3.0dB PB 42.1 kHz
Passband Ripple * 23 PR -0.05 0.05 dB
Stopband * 28 SB 83.0 kHz
Stopband Attenuation * 25, * 26 SA 82.0 dB
Group Delay * 24 GD 5.3 1/fs
Digital Filter + SCF + SMF * 25
Frequency Response : 0  40.0kHz -5.0 0.1 dB
Note
* 28. The passband and stopband frequencies are proportional to fs (sampling rate).
“PB = 0.252  fs, SB = 0.864  fs”

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■ SRC Block
(Ta=-40 ~ 85C; AVDD=3.0~3.6V; LVDD=3.0~3.6V; TVDD=1.7~3.6V; VDD33=3.0~3.6V;
VSS1=VSS2=VSS3=VSS4=0V )

1. Audio Mode (SRCFAUDx bit = “1”, x=1~4)

Parameter Symbol Min. Typ. Max. Unit

-0.01dB 0.980 ≤ FSO/FSI ≤ 6.000 PB 0 0.4583FSI kHz
-0.01dB 0.900 ≤ FSO/FSI < 0.990 PB 0 0.4167FSI kHz
-0.01dB 0.533 ≤ FSO/FSI < 0.909 PB 0 0.2182FSI kHz
Passband -0.01dB 0.490 ≤ FSO/FSI < 0.539 PB 0 0.2177FSI kHz
-0.01dB 0.450 ≤ FSO/FSI < 0.495 PB 0 0.1948FSI kHz
-0.01dB 0.225 ≤ FSO/FSI < 0.455 PB 0 0.1312FSI kHz
-0.50dB 0.167 ≤ FSO/FSI < 0.227 PB 0 0.0658FSI kHz
0.980 ≤ FSO/FSI ≤ 6.000 SB 0.5417FSI kHz
0.900 ≤ FSO/FSI < 0.990 SB 0.5021FSI kHz
0.533 ≤ FSO/FSI < 0.909 SB 0.2974FSI kHz
Stopband 0.490 ≤ FSO/FSI < 0.539 SB 0.2812FSI kHz
0.450 ≤ FSO/FSI < 0.495 SB 0.2604FSI kHz
0.225 ≤ FSO/FSI < 0.455 SB 0.1802FSI kHz
0.167 ≤ FSO/FSI < 0.227 SB 0.0970FSI kHz
0.225 ≤ FSO/FSI ≤ 6.000 PR ±0.01 dB
Passband Ripple
0.167 ≤ FSO/FSI < 0.227 PR ±0.50 dB
Stopband 0.450 ≤ FSO/FSI ≤ 6.000 SA 95.2 dB
Attenuation 0.167 ≤ FSO/FSI < 0.455 SA 85.0 dB
Group Delay * 29 67
GD Ts
(Ts=1/fs) (55/FSI+12/FSO)
Note
* 29. This value is SRC block only. It is the time from a rising edge of input LRCK after data is input to a
rising edge of output LRCK just before the data is output when there is no phase difference
between input and output LRCK.

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2. Voice Mode (SRCFAUDx bit = “0”, x =1~4)

Parameter Symbol Min. Typ. Max. Unit

-0.01dB 0.980 ≤ FSO/FSI ≤ 6.000 PB 0 0.4583FSI kHz
-0.01dB 0.900 ≤ FSO/FSI < 0.990 PB 0 0.4167FSI kHz
-0.50dB 0.711 ≤ FSO/FSI < 0.910 PB 0 0.3420FSI kHz
-0.50dB 0.653 ≤ FSO/FSI < 0.718 PB 0 0.3007FSI kHz
Passband
-0.50dB 0.450 ≤ FSO/FSI < 0.660 PB 0 0.2230FSI kHz
-0.50dB 0.327 ≤ FSO/FSI < 0.455 PB 0 0.1417FSI kHz
-0.50dB 0.225 ≤ FSO/FSI < 0.330 PB 0 0.1018FSI kHz
-0.50dB 0.167 ≤ FSO/FSI < 0.227 PB 0 0.0658FSI kHz
0.980 ≤ FSO/FSI ≤ 6.000 SB 0.5417FSI kHz
0.900 ≤ FSO/FSI < 0.990 SB 0.5021FSI kHz
0.711 ≤ FSO/FSI < 0.910 SB 0.3735FSI kHz
0.653 ≤ FSO/FSI < 0.718 SB 0.3320FSI kHz
Stopband
0.450 ≤ FSO/FSI < 0.660 SB 0.2490FSI kHz
0.327 ≤ FSO/FSI < 0.455 SB 0.1660FSI kHz
0.225 ≤ FSO/FSI < 0.330 SB 0.1248FSI kHz
0.167 ≤ FSO/FSI < 0.227 SB 0.0970FSI kHz
0.900 ≤ FSO/FSI ≤ 6.000 PR ±0.01 dB
Passband Ripple
0.167 ≤ FSO/FSI ≤ 0.910 PR ±0.50 dB
0.900 ≤ FSO/FSI ≤ 6.000 SA 95.2 dB
Stopband 0.653 ≤ FSO/FSI < 0.909 SA 90.0 dB
Attenuation 0.450 ≤ FSO/FSI ≤ 0.660 SA 70.0 dB
0.167 ≤ FSO/FSI < 0.455 SA 60.0 dB
Group Delay * 29 67
GD Ts
(Ts=1/fs) (55/FSI+12/FSO)

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10. DC Characteristics
(Ta=-40 ~ 85C; AVDD=3.0~3.6V; LVDD=3.0~3.6V; TVDD=1.7~3.6V; VDD33=3.0~3.6V;
VSS1=VSS2=VSS3=VSS4=0V)
Parameter Symbol Min. Typ. Max. Unit
High-Level Input Voltage 1 * 30 VIH1 75%TVDD V
Low-Level Input Voltage 1 * 30 VIL1 25%TVDD V
High-Level Input Voltage 2 * 31 VIH2 75%VDD33 V
Low-Level Input Voltage 2 * 31 VIL2 25%VDD33 V
SCL, SDA High-Level Input Voltage VIH3 70%TVDD V
SCL, SDA Low-Level Input Voltage VIL3 30%TVDD V
High-Level Output Voltage Iout= -100A * 32 VOH1 TVDD-0.3 V
Low-Level Output Voltage Iout=100A * 32 VOL1 0.3 V
SDA Low-Level TVDD ≥ 2.0V (Iout=3mA) VOL2 0.4 V
Output Voltage TVDD < 2.0V (Iout=3mA) VOL2 20%TVDD V
Input Leak Current * 33 Iin ±10 A
Input Leak Current, Pulled down pins
Iid 66 A
Power Down * 34, * 36
Input Leak Current, Pulled down pins
Iid 72 A
Power Down Release * 35, * 36
Input Leak Current, TESTI pin Iid 132 A
Input Leak Current, XTI pin lix 17 A
Notes
* 30. SDIN1, SDIN2, SDIN3/JX2, LRCK1, BICK1, LRCK2, BICK2, LRCK3/JX0/SDIN4, BICK3/JX1, PDN,
SCL/SCLK, CAD/CSN, TESTI and SI pins. The SCL pin is not included.
* 31. XTI pin.
* 32. SDOUT1, DZF/SDOUT2/RDY,STO/SDOUT3/GPO and SDA/SO pins. The SDA pin is not included.
* 33. Except internal pulled-down pins and the XTI pin.
* 34. When the AK7604 is powered down (PDN pin = “L”), the pull down resistors of LRCK1, BICK1,
LRCK2, BICK2, LRCK3/JX0/SDIN4 and BICK3/JX1 pins is 50kΩ (Typ. @3.3V).
* 35. When the AK7604 is powered up (PDN pin = “H”), the pull down resistors of LRCK1, BICK1,
LRCK2, BICK2, LRCK3/JX0/SDIN4 and BICK3/JX1 pins is 46kΩ (Typ. @3.3V).
* 36. Leak current in case of inputting 3.3V when LVDD=TVDD=VDD33=3.3V.

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11. Switching Characateristics

■ System Clock
(Ta=-40 ~ 85C; AVDD=3.0~3.6V; LVDD=3.0~3.6V; TVDD=1.7~3.6V; VDD33=3.0~3.6V;
VSS1=VSS2=VSS3=VSS4=0V; CL=20pF)
Parameter Symbol Min. Typ. Max. Unit
XTI Input Timing
a) X’tal Oscillator
Input Frequency fXTI 11.2896 18.432 MHz
b) XTI Clock Input
Duty Cycle 40 50 60 %
Input Frequency fXTI 0.256 24.576 MHz
LRCK/BICK Input Timing (Slave Mode)
LRCK Input Timing
Frequency fs 8 192 kHz
BICK Input Timing
Frequency * 37 fBCLK 0.256 24.576 MHz
Pulse Width Low tBCLKL 0.4 / fBCLK ns
Pulse Width High tBCLKH 0.4 / fBCLK ns
LRCK/BICK Output Timing (PLL Master Mode)
LRCK Output Timing
Frequency fs 8 192 kHz
Pulse Width High
PCM Mode tLRCKH 1/fBCLK ns
Except PCM Mode tLRCKH 50 %
BICK Output Timing
Frequency * 37 fBCLK 0.256 24.576 MHz
Duty dBCLK 50 %
Note
* 37. Required to meet the following expression: fBCLK ≥ 2 x fs x (Input/Output Data Length).

■ Power Down

(Ta=-40 ~ 85C; AVDD=3.0~3.6V; LVDD=3.0~3.6V; TVDD=1.7~3.6V; VDD33=3.0~3.6V;

VSS1=VSS2=VSS3=VSS4=0V)
Parameter Symbol Min. Typ. Max. Unit
PDN Pulse Width * 38 tRST 600 ns
Note
* 38. The PDN pin must be “L” when power up the AK7604.

PDN
tRST

VIL1

Figure 2. Reset Timing

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■ Serial Data Interface (SDIN1 ~ SDIN4, SDOUT1 ~ SDOUT3)

(Ta=-40 ~ 85C; AVDD=3.0~3.6V; LVDD=3.0~3.6V; TVDD=1.7~3.6V; VDD33=3.0~3.6V;
VSS1=VSS2=VSS3=VSS4=0V; CL=20pF)
Parameter Symbol Min. Typ. Max. Unit
Slave Mode
Delay Time from BICK “↑” to LRCK * 39 tBLRD 10 ns
Delay Time from LRCK to BICK “↑” * 39 tLRBD 10 ns
Serial Data Input Latch Setup Time tBSIDS 10 ns
Serial Data Input Latch Hold Time tBSIDH 5 ns
Delay Time from BICK “↓” to Serial Data Output * 40 tBSOD1 20 ns
Delay Time from BICK “↑”to Serial Data Output * 39, * 41 tBSOD2 5 30 ns
Master Mode
32, 48, 64,
BICK Frequency fBCLK fs
128, 256
BICK Duty Cycle 50 %
Delay Time from BICK “↓” to LRCK * 40 tMBL -10 10 ns
Serial Data Input Latch Setup Time tBSIDS 10 ns
Serial Data Input Latch Hold Time tBSIDH 10 ns
Delay Time from BICK “↓” to Serial Data Output * 40, * 41 tBSOD 10 ns
Notes
* 39. It is measured from BICK “↓” when the BICK polarity is inverted by setting BCKPx bit = “1”.
* 40. It is measured from BICK “↑” when the BICK polarity is inverted by setting BCKPx bit = “1”.
* 41. Set SDOPHx bit to “1” and the data from SDOUTx pin is output based on BICK “↑” when BICK
speed is more than 12.288MHz such as when using TDM256 mode with 96kHz sampling
frequency or TDM128 mode with 192kHz sampling frequency in slave mode. SDOPHx bit must be
set to “0” in master mode.

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1. Slave Mode

VIH1
LRCK(I)
D VIL1
tBLRD tLRBD D

D VIH1
BICK(I)
D VIL1
tBSIDS tBSIDH D
VIH1
SDIN1~4
D VIL1
D
Figure 3. Serial Interface Input Timing in Slave Mode

VIH1
LRCK(I)
VIL1

tBLRD tLRBD
D VIH1
BICK(I) VIL1
tBSOD1 tBSOD1
D D
SDOUT1~3 50%TVDD

Figure 4. Serial Interface Output Timing in Slave Mode (SDOPHx bit = “0”)

VIH1
LRCK(I)
VIL1

tBLRD tLRBD
D VIH1
BICK(I) VIL1
tBSOD2 tBSOD2
D D
SDOUT1~3 50%TVDD

Figure 5. Serial Interface Output Timing in Slave Mode (SDOPHx bit = “1”)

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2. Master Mode

50%TVDD
LRCK(O)

tMBL
tMBL
50%TVDD
BICK(O) D

tBSIDS tBSIDH

VIH1
SDIN1~4
D VIL1

Figure 6. Serial Interface Input Timing in Master Mode

50%TVDD
LRCK(O)

50%TVDD
BICK(O)
tBSOD tBSOD
D D
50%TVDD
SDOUT1~3

Figure 7. Serial Interface Output Timing in Master Mode (SDOPHx bit = “0”)

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■ SPI Interface
(Ta=-40 ~ 85C; AVDD=3.0~3.6V; LVDD=3.0~3.6V; TVDD=1.7~3.6V; VDD33=3.0~3.6V;
VSS1=VSS2=VSS3=VSS4=0V; CL=20pF)

1. SPI Low Speed Mode

Parameter Symbol Min. Typ. Max. Unit
μP Interface Signal
SCLK Frequency * 43 fSCLK 3.0 MHz
SCLK Low-level Width tSCLKL 160 ns
SCLK High-level Width tSCLKH 160 ns
Microcontroller → AK7604
CSN High-level Width tWRQH 300 ns
From CSN “↑” to PDN “↑” tRST 360 ns
From PDN “↑” to CSN “↓” tIRRQ 1 ms
From CSN “↓” to SCLK “↓” tWSC 300 ns
From SCLK “↑” to CSN “↑” tSCW 480 ns
SI Latch Setup Time tSIS 120 ns
SI Latch Hold Time tSIH 120 ns
AK7604 → Microcontroller
Delay Time from SCLK “↓” to SO Output tSOS 120 ns
SO Output Hold Time from SCLK “↑” * 42 tSOH 120 ns

2. SPI High Speed Mode

Parameter Symbol Min. Typ. Max. Unit
μP Interface Signal
SCLK Frequency * 43 fSCLK 6 MHz
SCLK Low-level Width tSCLKL 72 ns
SCLK High-level Width tSCLKH 72 ns
Microcontroller → AK7604
CSN High-level Width tWRQH 150 ns
From CSN “↑” to PDN “↑” tRST 180 ns
From PDN “↑” to CSN “↓” tIRRQ 1 ms
From CSN “↓” to SCLK “↓” tWSC 150 ns
From SCLK “↑” to CSN “↑” tSCW 240 ns
SI Latch Setup Time tSIS 60 ns
SI Latch Hold Time tSIH 60 ns
AK7604 → Microcontroller
Delay Time from SCLK “↓” to SO Output tSOS 60 ns
SO Output Hold Time from SCLK “↑” * 42 tSOH 60 ns
Notes
* 42. Except when writing the 24th bit (8 bits command + 16 bits address) of the command code. This will
be the 8th bit (8 bits command) with “write preparation data read command (24H)”.
* 43. Dummy command writing for switching to SPI interface from I2C interface and control register
access can always be made in SPI high speed mode (Max. 6MHz). DSP RAM area can be
accessed in SPI low speed mode (Max. 3MHz) in clock reset state (CKRESETN bit = “0”) and can
also be accessed in SPI high speed mode (Max. 6MHz) when PLL is locked (CKRESETN bit = “1”
and PLL is locked). It is necessary to set DLRDY bit to “1” when accessing to the DSP RAM area
while PLL is unlocked.

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VIH1
VIL1
SCLK

tSCLKL tSCLKH

1/fSCLK

1/fSCLK

VIH1
PDN
VIL1

VIH1
CSN
VIL1

tRST tIRRQ

Figure 8. SPI Interface Timing 1

VIH1
CSN tWRQH VIL1

VIH1
SI
VIL1

tSIS tSIH
VIH1
SCLK
VIL1
tWSC tSCW tWSC tSCW

Figure 9. SPI Interface Timing 2 (Microcontroller → AK7604)

VIH1
SCLK
VIL1

50%TVDD
SO

tSOS tSOH

Figure 10. SPI Interface Timing 3 (AK7604 → Microcontroller)

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■ I2C Interface
(Ta=-40 ~ 85C; AVDD=3.0~3.6V; LVDD=3.0~3.6V; TVDD=1.7~3.6V; VDD33=3.0~3.6V;
VSS1=VSS2=VSS3=VSS4=0V)

I2C: Fast Mode

Parameter Symbol Min. Typ. Max. Unit
I2C Timing
SCL clock frequency fSCL - - 400 kHz
Bus Free Time Between Transmissions tBUF 1.3 - - s
Start Condition Hold Time (prior to first Clock pulse) tHD:STA 0.6 - - s
Clock Low Time tLOW 1.3 - - s
Clock High Time tHIGH 0.6 - - s
Setup Time for Repeated Start Condition tSU:STA 0.6 - - s
SDA Hold Time from SCL Falling tHD:DAT 0 - - s
SDA Setup Time from SCL Rising tSU:DAT 0.1 - - s
Rise Time of Both SDA and SCL Lines tR - - 0.3 s
Fall Time of Both SDA and SCL Lines tF - - 0.3 s
Setup Time for Stop Condition tSU:STO 0.6 - - s
Pulse Width of Spike Noise Suppressed By Input Filter tSP 0 - 50 ns
Capacitive load on bus Cb - - 400 pF

VIH3
SDA
VIL3
tBUF tLOW tR tHIGH tF
tSP
VIH3
SCL
VIL3
tHD:STA tHD:DAT tSU:DAT tSU:STA tSU:STO
Stop Start Start Stop
Figure 11. I2C Interface Timing

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12. Recommended External Circuits

■ Connection Diagram

I2C Interface

TVDD

28
SDIN1
27 4.7kΩ 4.7kΩ
SDIN2
23
SDOUT1 17
34 SDA
CLOCK LRCK1
31 18
BICK1 SCL
33
LRCK2
15 μP
& DZF/SDOUT2/RDY
30
BICK2 22
26 STO/SDOUT3/GPO
Audio I/F SDIN3/JX2
32
LRCK3/JX0/SDIN4
29
BICK3/JX1 16 RESET
PDN
CONTROL
24
CAD “H” or “L”
19
SI “L”

48
MPREF
1
47
MPWR2
21
“L” TESTI 46
MPWR1
2kΩ
43 100n
INP1/AINL1
42 100n
INN1/GNDINL1
35 2kΩ
XTI 2kΩ
45 100n
INP2/AINR1
Rd 36 44 100n
XTO INN2/GNDINR1
2kΩ

1 1
AINL2
2
AK7604 AINR2 1
3 1
AINL3
4 1
AINR3

Digital IO 1.8～3.3V 25
TVDD 9 1
AOUT1L
10 0.1
10 1
AOUT1R
Digital IO 3.3V 37 11 1
AOUT2L
VDD33
12 1
10 0.1 AOUT2R
13 1
AOUT3L
Digital Core 3.3V 14 1
39 AOUT3R
LVDD
10 0.1 Analog +3.3V
6
AVDD
40 REF12
0.1 10
VSS1 7
2.2
0.1

24, 38, 41 8 10

VSS2/VSS3/VSS4 VREFH

5
VCOM
2.2

Figure 12. I2C Interface Connection Example

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■ Peripheral Circuit

1. Ground

VSS1, VSS2, VSS3 and VSS4 should be connected to the same ground. Decoupling capacitors,
particularly ceramic capacitors of small capacity, should be placed at positions as close as possible to
the AK7604.

2. Reference Voltage

VCOM is a common voltage of this chip and the VCOM pin outputs AVDD/2. A 2.2µF ceramic capacitor
should be connected between the VCOM pin and VSS1.

Do not connect the VCOM pin to any external devices. Digital signal lines, especially clock signal line
should be kept away as far as possible from this pin in order to avoid unwanted coupling into the
AK7604.

3. Analog Input

The analog input signal is input to the analog modulator of the AK7604. The maximum input voltage at
differential input pins is ±2.83Vpp (Typ.). The maximum input voltage at single-ended input pins is
2.83Vpp (Typ.). The output code format is 2's complements. The internal HPF removes the DC offset.

After power-down is released, the internal operating point level AVDD/2 occurs on analog input pins of
the AK7604. Concerning the internal operating point formation circuit, each input pin has impedance of
25k (Typ.). The pins that are connected to AC coupling capacitors require start-up time (time constant).

The AK7604 samples the analog inputs at 6.144MHz when fs=48kHz, 96kHz. The AK7604 includes an
anti-aliasing filter (RC filter), and no external low-pass filter is necessary in front of the ADC. However, an
external low-pass filter should be connected before the ADC for the signal which has large out-of-band
noise such as D/A converted signals.

The analog power supply to the AK7604 is +3.3V (Typ.). Voltage of AVDD + 0.3V or larger, voltage of
AVSS - 0.3V or smaller, and current of 10mA or larger must not be applied to analog input pins.
Excessive current will damage the internal protection circuit and will cause latch-up, damaging the IC.
Accordingly, if the external analog circuit voltage is ±15V, the analog input pins must be protected from
signals which are equal or larger than absolute maximum ratings.

When using differential input mode, it is prohibited to input signal to only one side like pseudo differential
input.

4. Analog Output

The analog output is single-ended and the output signal range is typically 0.86 x AVDD Vpp centered on
VCOM. The digital input data format is two’s compliment. Positive full-scale output corresponds to
7FFFFFH (@24bit) input code, Negative full scale is 800000H (@24bit) and VCOM voltage ideally is
000000H (@24bit). The Out-of-Band noise (shaping noise) generated by the internal delta-sigma
modulator is attenuated by an integrated switched capacitor filter (SCF) and a continuous time filter
(CTF).

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5. Crystal Oscillator

The resistor and capacitor values for the oscillator RC circuit are shown blow.

Table 4. Recommended Resistance and Capacitance with Crystal Oscillator

XTI, XTO pin
Oscillator R1 (Max) C0 (Max)
Capacity
12.288MHz 120Ω 2.5pF 22pF
18.432MHz 80Ω 2.5pF 15pF

XTI XTO

20 21 L1 C1 R1

C0
CL CL

Figure 13. Electric Equivalent Circuit of Crystal Oscillator

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13. Package

■ Outline Dimensions

■ Material and Lead Finish

Package: Epoxy, Halogen (Br and CI) free

Lead frame: Copper
Lead-finish: Soldering (Pb free) plate

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■ Marking

AKM
AK7604VQ
XXXXXXX

1
1) Pin #1 indication
2) Date Code: XXXXXXX (7 digits)
3) Marking Code: AK7604VQ
4) Asahi Kasei Logo

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14. Ordering Guide

AK7604VQ -40  +85C 48-pin LQFP (0.5mm pitch)

AKD7604 Evaluation Board for AK7604

15. Revision History

Date (Y/M/D) Revision Reason Page Contents

2018/09/27 0 First Edtion

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IMPORTANT NOTICE
0. Asahi Kasei Microdevices Corporation (“AKM”) reserves the right to make changes to the
information contained in this document without notice. When you consider any use or
application of AKM product stipulated in this document (“Product”), please make inquiries the
sales office of AKM or authorized distributors as to current status of the Products.
1. All information included in this document are provided only to illustrate the operation and
application examples of AKM Products. AKM neither makes warranties or representations with
respect to the accuracy or completeness of the information contained in this document nor
grants any license to any intellectual property rights or any other rights of AKM or any third party
with respect to the information in this document. You are fully responsible for use of such
information contained in this document in your product design or applications. AKM ASSUMES
NO LIABILITY FOR ANY LOSSES INCURRED BY YOU OR THIRD PARTIES ARISING FROM
THE USE OF SUCH INFORMATION IN YOUR PRODUCT DESIGN OR APPLICATIONS.
2. The Product is neither intended nor warranted for use in equipment or systems that require
extraordinarily high levels of quality and/or reliability and/or a malfunction or failure of which
may cause loss of human life, bodily injury, serious property damage or serious public impact,
including but not limited to, equipment used in nuclear facilities, equipment used in the
aerospace industry, medical equipment, equipment used for automobiles, trains, ships and
other transportation, traffic signaling equipment, equipment used to control combustions or
explosions, safety devices, elevators and escalators, devices related to electric power, and
equipment used in finance-related fields. Do not use Product for the above use unless
specifically agreed by AKM in writing.
3. Though AKM works continually to improve the Product’s quality and reliability, you are
responsible for complying with safety standards and for providing adequate designs and
safeguards for your hardware, software and systems which minimize risk and avoid situations
in which a malfunction or failure of the Product could cause loss of human life, bodily injury or
damage to property, including data loss or corruption.
4. Do not use or otherwise make available the Product or related technology or any information
contained in this document for any military purposes, including without limitation, for the design,
development, use, stockpiling or manufacturing of nuclear, chemical, or biological weapons or
missile technology products (mass destruction weapons). When exporting the Products or
related technology or any information contained in this document, you should comply with the
applicable export control laws and regulations and follow the procedures required by such laws
and regulations. The Products and related technology may not be used for or incorporated into
any products or systems whose manufacture, use, or sale is prohibited under any applicable
domestic or foreign laws or regulations.
5. Please contact AKM sales representative for details as to environmental matters such as the
RoHS compatibility of the Product. Please use the Product in compliance with all applicable
laws and regulations that regulate the inclusion or use of controlled substances, including
without limitation, the EU RoHS Directive. AKM assumes no liability for damages or losses
occurring as a result of noncompliance with applicable laws and regulations.
6. Resale of the Product with provisions different from the statement and/or technical features set
forth in this document shall immediately void any warranty granted by AKM for the Product and
shall not create or extend in any manner whatsoever, any liability of AKM.
7. This document may not be reproduced or duplicated, in any form, in whole or in part, without
prior written consent of AKM.

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