Reliable Computing of ReRAM Based

Compute-in-Memory Circuits for AI Edge Devices

Invited paper

Meng-Fan Chang Je-Ming Hung Ping-Cheng Chen Tai-Hao Wen

National Tsing Hua National Tsing Hua I-Shou University National Tsing Hua
University University Kaohsiung, Taiwan University
Hsinchu, Taiwan Hsinchu, Taiwan Hsinchu, Taiwan

Abstract— Compute-in-memory macros based on non-volatile density, high resistance on-off ratio, and ease of manufacture
memory (nvCIM) are a promising approach to break through the using existing technology nodes.
memory bottleneck for artificial intelligence (AI) edge devices; Researchers have demonstrated the efficacy of
however, the development of these devices involves unavoidable
ReRAM-based CIM macros in performing MAC operations
tradeoffs between reliability, energy efficiency, computing latency,
and readout accuracy. This paper outlines the background of from binary to 8-bit precision. Note that a reliable nvCIM
ReRAM-based nvCIM as well as the major challenges in its macro should also support high bit-precision output with short
further development, including process variation in ReRAM computing latency, low energy consumption, and sufficient
devices and transistors and the small signal margins associated readout accuracy against process variation. These factors are
with variation in input-weight patterns. This paper also particularly important when dealing with complex datasets
investigates the error model of a nvCIM macro, and the
(CIFAR-10, CIFAR-100, and ImageNet) and advanced neural
correspondent degradation of inference accuracy as a function of
error model when using nvCIM macros. Finally, we summarize network models.
recent trends and advances in the development of reliable The remainder of the paper is organized as follows. Section
ReRAM-based nvCIM macro. II introduces the background of nvCIM based on near-memory
and in-memory computing architectures for MAC operations.
Index Terms—Artificial intelligence, CNN edge processors, Section III outlines the challenges inherent in the design of
ReRAM, Computing-in-memory, Multiply-and-accumulate. normal nvCIM. Section IV introduces the challenges in
developing a reliable nvCIM. Section V summarizes recent
I. INTRODUCTION trends in silicon-verified nvCIM macros. Section VI concludes

A rtificial intelligence (AI) edge devices

Internet-of-Things (AIoT) applications that involve
and this work.

convolutional neural networks (CNNs) perform a massive II. NVCIM FOR MAC OPERATIONS: BACKGROUND
number of multiply-and-accumulate (MAC) operations, which MAC operations involve multiplying inputs and weights
generate an enormous amount of intermediate data. When using (stored in the NVM cell array) and then accumulating the
the conventional von Neumann computing architecture, this results. Most nvCIM macros possess mega-bit (Mb) memory
data must be transferred frequently between the processing capacity, which is generally sufficient for the storage of all
element (PE) and memory. When applied to complex neural weight data required by the neural network models
network models with high bit-precision and complex datasets, implemented in tiny AI edge devices. As shown in Fig. 1, MAC
the transfer of intermediate data can result in long computing operations can be performed using near-memory computing
latency and high energy consumption. Non-volatile ((NMC)) or in-memory y computing
p g ((IMC).
)
compute-in-memory (nvCIM) [1]-[34] is a promising approach
to overcome the so-called von Neumann bottleneck by
combining computing functions with nonvolatile storage
functions within a single macro. Implementing parallel analog
MAC operations within memory cell arrays can greatly reduce
latency and energy consumption associated with computation
as well as system wake-up. Nonvolatile memory (NVM) can
also be used for power-off data storage to reduce power
consumption in standby mode.
One of the most promising advances for NVM is
one-transistor one-resistor (1T1R)-based resistive
random-access memory (ReRAM), due to its high storage Fig. 1. Concepts underlying near-memory and in-memory NVM computation
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A. MAC Operations using Near-Memory Computing (NMC) with weight data stored in the ReRAM cell (RMC). Thus, a
As with typical memory devices, NMC arrays [32]-[34] multiplication result of “1” indicates a current in low resistance
perform data storage, while an adjacent computing circuit block state (ILRS), whereas a multiplication result of “0” indicates a
performs MAC operations (see Fig. 2(a)). Weight data is current in high resistance state (IHRS). The sum of the current
readout by sense amplifiers (SA) from memory array and values in a given column indicates the current of the bitline (IBL)
generates a digital output, whereas data readout by an analog accessed during that MAC operation. Finally, a readout circuit
readout circuit generates an analog output, either of which can converts IBL into a digital output. In-memory computing can
be used as an input for the computing block. This means that also be applied to multi-level cell (MLC) memory devices. The
the computing circuit block can be implemented using digital or fact that the 2N-level resistance state of an MLC device can also
analog circuits. be used as N-bit weight data. However, the design of
When performing multi-bit MAC operations, an NMC corresponding circuitry poses numerous challenges. By using
device is able to extract weight data (W) from the memory cell the in-memory-array computing technique, the energy
array, multiply it with the digital input (IN), and perform efficiency of IMC could potentially exceed that of NMC;
accumulation and/or place value computation within one In the following, we examine the challenges involved in
memory cycle. The von Neumann architecture requires one designing IMC-based nvCIM and recent advances in this area.
cycle for memory access/movement and a second cycle for
MAC computing/accumulation. III. DEVELOPING NVCIM MACROS: CHALLENGES
A. Signal Margin due to read disturb voltage, cell-resistance
variation, and resistance drift
Most NVM devices require high-precision low-voltage
biasing to prevent read disturbance. Note that any read voltage
or current stress across an NVM cell can lead to data corruption.
Thus, the clamping voltage applied to the selected BL within a
1T1R cell array should not exceed the read disturb voltage.
Note however that the use of low bias voltage results in a small
sensing margin and limited signal swing on the BL, which can
degrade the accuracy of the readout circuit when performing
(a) MAC operations.
Note also that emerging NVM devices vary considerably in
terms of cell-resistance, due to process variation during mass
production (see Fig. 3). The resistance variation in NVM cells
constrains the signal margin between neighboring MAC values
in the analog domain and limits the number of operations that
can be performed within an NVM cell array [1], [36].
Resistance drift can also can also degrade readout accuracy
over time, particularly in multi-level-cell (MLC) devices.
When performing large MAC operations, devices in a moderate
resistance state are more susceptible to resistance drift than are
devices in high resistance state (HRS) or low resistance state
(b) (LRS).
Fig. 2. Architectures used for nonvolatile computing-in-memory (nvCIM): (a)
NMC; and (b) IMC

B. MAC Operations using In-Memory Computing (IMC)

The memory cell array in an IMC structure performs data
storage as well as analog computation [1]-[31]. When
performing MAC operations, each NVM memory cell is tasked
with multiplying an input with a stored weight value, after
which the bitline (BL) is tasked with accumulating the result
from memory cells in the same column. The resulting analog
voltage or current is then converted by a readout circuit (e.g., a Fig.3. Resistance distribution and summary table of foundry provided ReRAM
voltage-mode analog-to-digital converter or current-mode cell.
readout circuit) into a digital MAC value for output.
Fig. 2(b) illustrates the structure of an IMC-based nvCIM B. Influence of pattern dependent variation on signal margins
equipped with a single-level-cell (SLC) ReRAM device. This Most existing NVM technologies are limited in terms of
example has binary inputs applied to the wordlines (WLs), cell-resistance ratio; i.e., a narrow difference in memory cell
wherein high and low wordline voltages are respectively used current between LRS (ILRS) and HRS (IHRS). Therefore, unlike
to represent input values of 1 or 0. The current of the accessed those memory devices with large cell-resistance ratio, the IHRS
memory cell (IMC) is derived by multiplying the input value
is non-negligible during MAC operation for ReRAM-based Note that the more complicated dataset results in more
nvCIM macro. degradation in inference accuracy. Also, a precise
The effect of variations in IHRS on the bitline current (IBL) programming algorithm [38], [40], [41] is required when
depends on the input x weight configuration and the number seeking to develop a reliable CIM macro based on non-volatile
(NWL) of activated wordlines. As shown in Fig. 4., this issue memory. Inference accuracy can be affected by mis-program
(referred to as pattern-dependent variation) can lead to a errors in the place-value of weight data; however, the severity
decrease in signal margin. As an example, let us consider an of those effects depends on where it occurs. For example, errors
nvCIM macro with 9 accumulations per MAC operation. A pertaining to the LSB readout channel are not as severe as those
situation where the IBL for MACV = 6 could be associated with in pertaining to the MSB readout channel.
six WLs switched on, involving six LRS and zero HRS cells.
Likewise, a situation where the IBL for MACV = 6 could be
associated with nine WLs are switched on, involving six LRS
cells and three HRS cells. This means that when the MACV is
small, variations in bitline current are dominated by
pattern-dependent variation; however, when MACV is large,
variations in bitline current are dominated by cell-resistance. If
the MACV were at a moderate level, then the bitline current
would be susceptible to influence by both cell-resistance and
pattern-dependent variation.

((a))

Fig. 4. MAC current distribution resulting from pattern-dependent variation

IV. DEVELOPING RELIABLE NVCIM MACROS: CHALLENGES

A. Computing Error versus System-level Inference Accuracy
Computing error can have a profound impact on the overall
inference accuracy of neural network models. In [2], the
authors proposed an 8Mb nvCIM macro that enables MAC (b)
Fig. 5 (a). Readout accuracy and (b) readout distribution of an output channel of
operations with 8b-input, 8b-weight, 8-channel accumulation, [2]
and 19-bit output. Note that the 19-bit output was achieved by
combining partial MAC values (pMACV) from eight output
channels through 8 cycles. Figs. 5(a) and (b) show the readout
accuracy and readout distribution (error model) of an output
channel in their system. Readout distribution of a readout path
was measured under real-world variations, including process
variation in transistors and ReRAM cell resistance. The
measured readout yield ranged from 96.2% to 100% for lower
partial MAC values (0 to 4), and ranged from 92.70% to 95.3%
for higher partial MAC values (5 to 7). Note that lower partial
MAC values frequently occur in neural network models, and
higher partial MAC values less frequently occur in neural Fig. 6. Inference accuracy degradation when applying [2] to various neural
network models. Fig. 6 shows the degradation of system level network models and datasets.
inference accuracy when that system was applied to various B. Readout Quantization versus System-level Inference
neural network models and datasets. When applied to classify Accuracy
the CIFAR-10 dataset using ResNet-50, VGG-16, and The inference accuracy can be impacted by the exploited
ResNet-20 models, the degradation in inference accuracy as CIM architecture and its readout quantization method. Fig. 7
follows: -0.79%, -0.63%, and -0.46% compared to respective shows the readout accuracy of a readout channel in a CIM
software baseline. When applied to classify the CIFAR-100 macro example that performs 8b-input, 8b-weight, 16-channel
dataset using ResNet-50, VGG-16, and ResNet-20 models, the accumulation, and 20-bit output. Each readout channel
degradation in inference accuracy was as follows: -1.11%, performs 2b-input, 1b-weight and 16-channel accumulation.
-1.1%, and -0.92% compared to respective software baseline.
The 20-bit output was achieved by combining partial MAC A number of nvCIM schemes using hybrid analog-digital
values (pMACV) from eight output channels through 4 cycles. CIM (blue-symbols) have achieved a high output-ratio without
Note that each output channel exploits clipped quantization, signal margin degradation. The partial MAC operations are
which merges the analog pMAC values exceeding a selected conducted in the analog domain and readout by
threshold into a single digital value, while those analog pMAC analog-to-digital converters (ADCs). The digital circuits then
values below the threshold are read out without quantization merging these partial MAC values generated from ADCs into
loss. The output levels on a readout channel are 48 and the final MAC value. A sufficient output ratio and input precision x
threshold is set at 31 due to those pMAC values lower than 31 weight precision enables those works applied to complicated
are frequently occur in neural network models, as shown in Fig. dataset for advanced applications.
8. In the case of low pMACV (<15), the analog readout circuit
achieved readout accuracy of 100%~98%. In cases of moderate
to high pMACV, readout accuracy ranges from 97% to 98%.
When applied this CIM macro to ResNet-20 neural network
model trained for CIFAR-100 dataset, the inference accuracy
was 0.78% lower than software baseline. The behavior of
quantization in a CIM macro and the readout accuracy
degradation can impact the overall inference accuracy.

Fig. 9. Input precision x weight precision versus output ratio of recent nvCIM
works.

Fig. 7. Readout accuracy

y of partial
p MAC values on a readout channel.

Fig. 10. Figure-of-the-merit (FoM) of recent nvCIM works in which the FoM is
the product of input precision (IN), weight precision (W), output-ratio
(OUT-ratio), and energy efficiency (EF).
In assessing the performance of nvCIM macros, it is
necessary to consider their energy efficiency as well as the
inference accuracy of the AI edge devices to which they are
Fig. 8. Distribution of partial MAC values on a readout channel when applied to applied. The inference accuracy required for most practical
the CIFAR-100 dataset using the ResNet20 model. applications is achievable only under high input, weight, and
output bit-precision; however, tradeoffs are inevitable. In this
V. NVCIM FOR MAC OPERATIONS: RECENT TRENDS paper, we sought to account for the various strengths and
Fig. 9. illustrates the relationship between input precision x weaknesses of existing nvCIMs by comparing them based on a
weight precision versus the output ratio of recent nvCIM works figure of merit (FoM) derived as the product of input precision,
based on pure analog (current/voltage) and hybrid readout weight precision, output-ratio, and energy efficiency. As shown
(current/voltage + digital) schemes. Note that the output ratio is in Fig. 10, nvCIMs developed before 2020 achieved high
obtained by dividing the actual readout precision by the full energy efficiency; however, low input-weight-output precision
output precision (ideal MACV precision). when applied to simple datasets (e.g., MNIST or CIFAR-10)
Most analog-CIM-based nvCIM devices with high resulted in low FoMs. The higher bit precision of recent works
full-output-precision (red-symbols) have been unable to has been shown to reduce data loss when dealing with complex
achieve a high output-ratio, due to difficulties in designing datasets. We expect that the corresponding increase in FoM
high-resolution readout circuits with high output precision. scores will continue steadily with further advances in energy
Devices with limited output ratio are unable to deal with efficiency as well as bit precision.
complex datasets, such as ImageNet or CIFAR-100. Their
applicability to complex datasets is also hindered by inference VI. CONCLUSIONS
accuracy degradation due to limited input precision x weight nvCIM is a promising candidate to improve the energy
precision. efficiency of AI edge devices by eliminating the memory
bottleneck. This review article examined recent silicon-verified (2018).
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