Basic Electrical Properties of MOS and Bi CMOS circuits

IdS-Vds Characteristics of MOS Transistor :

The graph below shows the Ids Vs Vds characteristics of an n- MOS transistor for several values of Vgs. It is
clear that there are two conduction states when the device is ON. The saturated state and the non-saturated
state. The saturated curve is the flat portion and defines the saturation region.
For Vds > Vgs - Vth, the nMOS device is conducting and ID is independent of Vds.
For Vds < Vgs - Vth, the transistor is in the non-saturation region and the curve is a half parabola.
When the transistor is OFF (Vgs < Vth), then ID is zero for any Vds value.

The boundary of the saturation/non-saturation bias states is a point seen for each curve in the graph as the
intersection of the straight line of the saturated region with the quadratic curve of the non- saturated region.
This intersection point occurs at the channel pinch off voltage called VDSAT. The diamond symbol marks the
pinch-off voltage VDSAT for each value of Vgs. VDSAT is defined as the minimum drain-source voltage that is
required to keep the transistor in saturation for a given Vgs.
The drain current in saturation is virtually independent of VDS and the transistor acts as a current source.
This is because there is no carrier inversion at the drain region of the channel. Carriers are pulled into the high
electric field of the drain/substrate pn junction and ejected out of the drain terminal.
Drain-to-Source Current IDS Versus Voltage VDS Relationships :

The working of a MOS transistor is based on the principle that the use of a voltage on the gate induce a
charge in the channel between source and drain, which may then be caused to move from source to drain
under the influence of an electric field created by voltage Vds applied between drain and source. Since
the charge induced is dependent on the gate to source voltage Vgs then Ids is dependent on both Vgs and Vds.
Let us consider the diagram below in which electrons will flow source to drain.

So,the drain current is given by

𝐶ℎ𝑎𝑟𝑔𝑒 𝑖𝑛𝑑𝑢𝑐𝑒𝑑 𝑖𝑛 𝑐ℎ𝑎𝑛𝑛𝑒𝑙 (𝑄𝑐)
𝐼𝑑𝑠 = −𝐼𝑠𝑑 =
𝐸𝑙𝑒𝑐𝑡𝑟𝑜𝑛 𝑡𝑟𝑎𝑛𝑠𝑖𝑡 𝑡𝑖𝑚𝑒(𝜏𝑠𝑑 )
Where the transit time is given by

𝐿𝑒𝑛𝑔𝑡ℎ 𝑜𝑓 𝑡ℎ𝑒 𝑐ℎ𝑎𝑛𝑛𝑒𝑙 (𝐿)

𝜏𝑠𝑑 =
𝑉𝑒𝑙𝑜𝑐𝑖𝑡𝑦 (𝑣)

But velocity v= µEds

Where µ =electron or hole mobility and

Eds = Electric field also , Eds = Vds/L

so, v = µ.Vds/L and

τsd = L2 / µ.Vds

The typical values of µ at room temperature are given below.

n 650 cm 2 / V − sec
p 240 cm 2 / V − sec
 Non-saturated Region:
Let us consider the Id vs Vds relationships in the non-saturated region. The charge induced in the channel due
to the voltage difference between the gate and the channel, Vgs (assuming substrate connected to source).
The voltage along the channel varies linearly with distance X from the source due to the IR drop in the
channel. In the non-saturated state the average value is Vds/2. Also the effective gate voltageVds = Vgs – Vt
where Vt, is the threshold voltage needed to invert the charge under the gate and establish the channel.

Hence the induced charge is Qc = Eg εins εoW.L Where

Eg = average electric field gate to channel
εins = relative permittivity of insulation between gate and channel εo=permittivity
 V − V − Vds 
 gs 2 

t
Eg =
D

Here D is the thickness of the oxide layer. Thus So, by combining the above two equations, we get or the
above equation can be written as
WL ins 0  Vds 
Qc = −
 gs t −
2 
V V
D 
In the non-saturated or resistive region where Vds < Vgs – Vt and

WL ins  0 
Vgs − Vt − ds 
V

I ds
Q
= c = D  2
2
tsd L / µ.Vds
µ ins  0 W  V 
=  Vgs − Vt − ds 2  Vds
D L  
 ins 0 W V 2 ds 
K= I ds = K  (Vgs − Vt )Vds −
Conductivity factor
D L 2 
Generally, a constant β is defined as

 =K
W
 V 2ds 
I ds =   (Vgs − Vt )Vds −
2 
L

 ins oW .L
The gate /channel capacitance is Cg =
D
Cg   V 2ds 
I ds = 2  (Vgs − Vt )Vds −
L  2 
Some time it is also convenient to use gate –capacitance per unit area ,C0 So,the drain current is
 W
 = Cox W  V 2 ds 
L
I ds = C0   (Vgs − Vt )Vds −
L  2 

This is the relation between drain current and drain-source voltage in non-saturated region.

Pinch-off Voltage: The voltage at which Ids becomes Constant. i.e rate of change of Ids is zero.

 V2 
I ds =   (Vgs − Vt )Vds − ds 
 2 
I ds
= 0 = (Vgs − Vt ) − Vds
Vds
Vds = Vgs − Vt

Saturated Region
Saturation begins when Vds = Vgs - Vt, since at this point the IR drop in the channel equals the effective gate to
channel voltage at the drain and we may assume that the current remains fairly constant as Vds increases
further. Thus

W (V − Vt )
2

=K
gs
I ds
L 2

(V − Vt )
2

=
gs
or we can also write that I ds
2
Cg 
(Vgs − Vt )
2
or it can also be written as
I ds =
2 L2

W
( gs t )
2
or
I ds = C0  V − V
2L
The expressions derived above for Ids hold for both enhancement and depletion mode devices. Here the
threshold voltage for the nMOS depletion mode device (denoted as Vtd) is negative


 0 Vgs  Vt cutoff


I ds =   Vgs − Vt − ds  V V  V ,V  V − V
V
 ds linear
  
2 gs t ds gs t

 
( )
2
 V gs − Vt Vgs  Vt ,Vds  Vgs − Vt saturation
2
 Ids Depends on
• Gate to Source Voltage
• Drain to Source Voltage
• Length & width of the channel
• Dielectric constant of SiO2
• Thickness of the oxide layer
• Threshold Voltage

MOS Transistor Threshold Voltage Vt:

The minimum amount of gate to source voltage Vgs required to produce surface inversion in order to form the
conducting channel between the source and drain is known as Threshold Voltage Vt
• The gate structure of a MOS transistor consists, of charges stored in the dielectric layers and in the surface
to surface interfaces as well as in the substrate itself.
• Switching an enhancement mode MOS transistor from the off to the on state consists in applying sufficient
gate voltage to neutralize these charges and enable the underlying silicon to undergo an inversion due to the
electric field from the gate.
• Switching a depletion mode nMOS transistor from the on to the off state consists in applying enough
voltage to the gate to add to the stored charge and invert the 'n' implant region to 'p'.
The threshold voltage Vt may be expressed as:
QB − Qss
Vt = ms + + 2 fN
C0
where QB = the charge per unit area in the depletion layer below the oxide
Qss = charge density at Si: SiO2 interface
C0 =Capacitance per unit area.
Φms = work function difference between gate and Si
ΦfN = Fermi level potential between inverted surface and bulk Si
For polysilicon gate and silicon substrate, the value of Φms is negative but negligible and the
magnitude and sign of Vt are thus determined by balancing the other terms in the equation. To evaluate the Vt
the other terms are determined as below.

Qss=(1.5 to 8)x 10-8 coulombs/m2

VSB =Substrate bias voltage(-ve for nmos & +ve for pmos )
k = Boltzmann's constant (eV/K, J/K)
q = Electronic charge (coulombs)
T = temperature (°K)
N = carrier density in doped semiconductor(N=NA- nmos & ND-pmos)
ηi = intrinsic carrier concentration in Silicon
εsi = permittivity of Silicon = εr . εo
εr =11.7 (relative Silicon permittivity)
εo= (permittivity of free space)
Body Effect :
Generally while studying the MOS transistors it is treated as a three terminal device. But, the body of the
transistor is also an implicit terminal which helps to understand the characteristics of the transistor.

Body effect - nMOS device

Increasing VSB (Substrate bias voltage) causes the channel to be depleted of charge carriers and thus the
threshold voltage is raised is called body effect.
Change in Vt is given by ΔVt = γ.(VSB)1/2 where γ is a constant which depends on substrate doping so that
the more lightly doped the substrate, the smaller will be the body effect
The threshold voltage can be written as
 D 
Vt = Vt (0) +   2 si 0 QN .(VSB )
1/2

 ins 0 
Where Vt(0) is the threshold voltage for VSB = 0

Enhancement mode(nmos) Depletion mode (nmos)

Vte=0.2VDD(=1V for VDD=5V) when VSB=0V Vtd= -0.7VDD (=-3.5V for VDD=5V) when VSB=0V
Vte=0.3VDD(=1.5V for VDD=5V) when VSB=5V Vtd= -0.6VDD (= -3V for VDD=5V) when VSB=5V

Vt is a function of
Gate conducting material, Gate insulating material, Gate insulator thickness, Impurities at the silicon-
insulator interface, Voltage between the source and the substrate VSB
MOS TRANSISTOR TRANSCONDUCTANCE gm, AND OUTPUT CONDUCTANCE gds,.

Tran conductance expresses the relationship between output current Ids and the input voltage Vgs and is defined
as
 I ds
gm = | Vds = constant
Vgs
To find an expression for gm in terms of circuit and transistor parameters,
In Linear-region
W V 2 ds 
I ds = K −
 gs t ds −
2 
(V V )V
L
W Cg Vds
gm = K Vds or gm =
L L2

In Saturation region Vds =Vgs – Vt then

C
gm = K
W
L
(Vgs − Vt ) or gm =  (Vgs − Vt ) or gm = g2 (Vgs − Vt )
L
It is possible to increase the gm, of a MOS device by increasing its width. However, this will also increase the
input capacitance and area occupied.
A reduction in the channel length results in an increase in .ω0 owing to the higher gm. However, the gain of the
MOS device decreases owing to the strong degradation of the output resistance = 1/gds·
The output conductance gds can be expressed by

gds =
 I ds
 Vds ( )
=  I ds  1 2
L λ = channel-length modulation parameter

Here the strong dependence on the channel length is demonstrated as

1
    and I ds  1
 L L ( ) for the MOS Device

Figure of Merit (ω0)

An indication of frequency response may be obtained from the parameter ω0 where

gm 
= 2 (Vgs − Vt ) =
1
0 =
cg L  sd
This shows that switching speed depends on the gate voltage above threshold and on carrier mobility and
inversely as the square of the channel length. A fast circuit requires that gm be as high as possible.
Pass Transistors

Unlike bipolar transistors, the isolated nature of the gate allows MOS transistors to be used as switches in series
with lines carrying logic levels in a way that is similar to the use of relay contacts. This application of the MOS
device is called the pass transistor and switching logic arrays can be formed

NMOS Pass Transistors

NMOS pass transistor outputs only strong zero, but only a weak one

PMOS Pass Transistor Logic

PMOS pass transistor outputs a strong one, but only a weak zero
Transmission gate

How are both a strong "1" and a strong "0" passed?

Transmission gate pass transistor configuration
When I = 1, B = strong 1, if A = 1;
B = strong 0, if A = 0
When I = 0, non-conducting

NMOS Inverter
An inverter circuit is a very important circuit for producing a complete range of logic circuits. This is needed for
restoring logic levels, for NAND and NOR gates, and for sequential and memory circuits of various forms.

General Circuit of Inverter

NMOS Inverter:
An nMOS inverter circuit can be constructed by
• Replacing Pull Down Network by an enhancement mode transistor with source connected to ground and
• a PUN of connected from the drain to the positive supply rail VDD.
• The output is taken from the drain and the input applied between gate and ground.

Types of NMOS Inverters

NMOS Inverters are classified based on PUN;
1) Resistive Load
2) Enhancement load
3) Depletion Load
4) PMOS Load
NMOS Inverter with Resistive Load

Basic Inverter: Transistor with source connected to ground and a load resistor connected from the drain to the
positive Supply rail
Output is taken from the drain and control input connected between gate and ground
Resistors are not easily formed in silicon - they occupy too much area
ii) NMOS Enhancement Mode Transistor Pull - Up

This arrangement consists of a n-MOS enhancement mode transistor as pull-up. The arrangement and the
transfer characteristic are shown below.

nMOS enhancement mode pull-up and transfer characteristic

The important features of this arrangement are
(a) Dissipation is high since current flows when Vin =logical 1 (VGG is returned to VDD) .
(b) Vout can never reach VDD (logical I) if VGG = VDD as is normally the case.
(c) VGG may be derived from a switching source, for example, one phase of a clock; so that dissipation can be
greatly reduced.
(d) If VGG is higher than VDD then an extra supply rail is required.

nMOS depletion mode transistor pull-up:

 The salient features of the n-MOS inverter are
For the depletion mode transistor, the gate is connected to the source so it is always on .
In this configuration the depletion mode device is called the pull-up (P.U) and the enhancement mode
device the pull-down (P.D) transistor.
With no current drawn from the output, the currents Ids for both transistors must be equal.

Observations:
a) Dissipation is high , since rail to rail current flows when Vin = logical 1.
b) Switching of output from 1 to 0 begins when Vin exceeds Vt, of pull-down device.
c) When switching the output from 1 to 0, the pull-up device is non-saturated initially and this
presents lower resistance through which to charge capacitive loads .

nMOS depletion mode transistor pull-up and transfer characteristic

nMOS Inverter transfer characteristics.

The transfer characteristic is drawn by taking Vds on x-axis and Ids on Y-axis for both enhancement and
depletion mode transistors. So,to obtain the inverter transfer characteristic for Vgs = 0 depletion mode
characteristic curve is superimposed on the family of curves for the enhancement mode device and from the
graph it can be seen that , maximum voltage across the enhancement mode device corresponds to minimum
voltage across the depletion mode transistor.
From the graph it is clear that as Vin(=Vgs p.d. transistor) exceeds the Pulldown threshold voltage current
begins to flow. The output voltage Vout thus decreases and the subsequent increases in Vin will cause the Pull
down transistor to come out of saturation and become resistive.
CMOS Inverter:
The salient features of this arrangement are
(a) No current flows either for logical 0 or for logical 1 inputs.
(b) Full logical 1 and 0 levels are presented at the output.
(c) For devices of similar dimensions the p-channel is slower than the n-channel device.
The CMOS Inverter is designed using p-MOS and n-MOS transistors.

In the inverter circuit ,if the input is high .the lower n-MOS device closes to discharge the capacitive load
.Similarly ,if the input is low, the top p-MOS device is turned on to charge the capacitive load. At no time
both the devices are on, which prevents the DC current flowing from positive power supply to ground.
Qualitatively this circuit acts like the switching circuit, since the p-channel transistor has exactly the
opposite characteristics of the n-channel transistor. In the transition region both transistors are saturated and the
circuit operates with a large voltage gain. The C-MOS transfer characteristic is shown in the below graph.
Considering the static conditions first, it may be Seen that
In region 1 for which Vi,. = logic 0, we have the p-transistor fully turned on while the n-transistor is fully
turned off. Thus no current flows through the inverter and the output is directly connected to VDD through the p-
transistor. Hence the output voltage is logic 1.
In region 5, Vin = logic 1 and the n-transistor is fully on while the p-transistor is fully off. So, no current flows
and logic 0 appears at the output.

In region 2 the input voltage has increased to a level which just exceeds the threshold voltage of the n-
transistor. The n-transistor conducts and has a large voltage between source and drain; so it is in saturation. The
p-transistor is also conducting but with only a small voltage across it, it operates in the unsaturated resistive
region. A small current now flows through the inverter from VDD to VSS. If we wish to analyze the behavior
in this region, we equate the p-device resistive region current with the n-device saturation current and thus
obtain the voltage and current relationships.
Region 4 is similar to region 2 but p-transistor operating in saturation and n-transistor operating in resistive
region.
Region 3 is the region in which the inverter exhibits gain and in which both transistors are in saturation.
The currents in each device must be the same ,since the transistors are in series. So,we can write that
Idsp=-Idsn
where
p
I dsp = (VDD − Vin − Vt p )2
2
and
n
I dsn = (Vin − Vtn ) 2
2

Since both transistors are in saturation, they act as current sources so that the equivalent circuit in this region is
two current sources in series between VDD and Vss with the output voltage coming from their common point.
The region is inherently unstable in consequence and the changeover from one logic level to the other is rapid.
 I dsp = I dsn
p n
(VDD − Vin − Vt p ) 2 = (Vin − Vtn ) 2
2 2
p (Vin − Vtn ) 2
=
n (VDD − Vin − Vt p ) 2

Vin=Vinv=0.5 VDD
Vtn=|Vtp|=0.2 VDD
p (0.5VDD − 0.2VDD ) 2
=
n (VDD − 0.5VDD − 0.2VDD ) 2
p
= 1 =  n =  p
n
Wn Wp
Kn = Kp
Ln Lp
Wn Wp
n = p
Ln Lp
but n =2.5p
Wn Wp
2.5 p n = p
Ln Lp
Wn Wp
2.5 =
Ln Lp
if we keep L n =L p
W p = 2.5Wn

i.e to have symmetric operating voltage the width of the p-transistor must have 2.5 times that of n-transistor

Determination of Pull-up to Pull –Down Ratio (Zp.u/Zp.d.)for an nMOS Inverter driven by another
nMOS Inverter :
Let us consider the arrangement shown in Fig.(a). in which an inverter is driven from the output of another
similar inverter. Consider the depletion mode transistor for which Vgs = 0 under all conditions, and also assume
that in order to cascade inverters without degradation the condition
Vin=Vout=Vinv

Fig.(a).Inverter driven by another inverter.

 For equal margins around the inverter threshold, we set Vinv = 0.5VDD· At this point both transistors
are in saturation and we can write that

W (Vgs − Vt )
2

I ds = K
L 2
In the depletion mode
Wpu ( −Vtd )2
I ds = K since Vgs =0
Lpu 2
and in the enhancement mode
W pd (Vinv − Vt ) 2
I ds = K since Vgs =Vinv
Lpd 2
equating( since currents are the same) we have
W pd Wpu
(Vinv − Vt ) 2 = ( −Vtd ) 2
Lpd Lpu

where Wp.d , Lp.d , Wp.u. and Lp.u are the widths and lengths of the pull-down and pull-up
transistors respectively.
So,we can write that

we have
The typical, values for Vt ,Vinv and Vtd are
Vt=0.2VDD ; Vtd= - 0.6VDD
Vinv= 0.5 VDD( for equal margins)

Substituting these values in the above equation ,we get

0.6
0.5 = 0.2 +
Z pu
Z pd

Here
Z pu
=2
Z pd

So,we get
Z pu
= 4
Z pd 1

This is the ratio for pull-up to pull down ratio for an inverter directly driven by another inverter.
Pull -Up to Pull-Down ratio for an nMOS Inverter driven through one or more Pass
Transistors
Let us consider an arrangement in which the input to inverter 2 comes from the output of inverter 1

but passes through one or more nMOS transistors as shown in Fig. below (These transistors are called pass
transistors).

The connection of pass transistors in series will degrade the logic 1 level / into inverter 2 so that the output will
not be a proper logic 0 level. The critical condition is , when point A is at 0 volts and B is thus at VDD. but the
voltage into inverter 2at point C is now reduced from VDD by the threshold voltage of the series pass
transistor. With all pass transistor gates connected to VDD there is a loss of Vtp, however many are connected
in series, since no static current flows through them and there can be no voltage drop in the channels.
Therefore, the input voltage to inverter 2 is
Vin2 = VDD- Vtp where Vtp = threshold voltage for a pass transistor.
Let us consider the inverter 1 shown in Fig.(a) with input = VDD· If the input is at VDD , then the pull-down
transistor T2 is conducting but with a low voltage across it; therefore, it is in its resistive region represented by
R1 in Fig.(a) below. Meanwhile, the pull up transistor T1 is in saturation and is represented as a current source.
For the pull down transistor
 
Vds1 1 Lpd 1  1 
R1 = = 
I ds K Wpd 1  Vds1 
Vdd − Vt − 
 2 
Wpd 1  V 2 ds1 
I ds = K  dd
(V − Vt )Vds1 − 
Lpd 1  2 

Since Vds is small, Vds/2 can be neglected in the above expression.

So,

Vds1 1  1 
R1 = = Z pd 1  
I ds K  Vdd − Vt 

Now, for depletion mode pull-up transistor in saturation with Vgs = 0

W pu1 ( −Vtd ) 2
I 1 = I ds =K
Lpu1 2
The product I1R1 = Vout1 So,
Z pd 1  1  (Vtd )2
Vout1 = I 1 R1 =  
Z pu1  Vdd − Vt  2

Let us now consider the inverter 2 Fig.b .when input = VDD- Vtp.
 1  1 
R2 = Z pd 2  
K  (Vdd − Vtp ) − Vt
 

1 ( −Vtd ) 2
I 2 == K
Z pu 2 2

hence,
Z pd 2  1  ( −Vtd )2
Vout 2 = I 2 R2 =  
Z pu 2  Vdd − Vt p − Vt  2

If inverter 2 is to have the same output voltage under these conditions then Vout1 = Vout2. That is I1R1=I2R2
,
therefore
Z pu 2 Z pu1  Vdd − Vt 
=  
Z pd 2 Z pd 1  Vdd − Vt p − Vt 

Considering the typical valuesVt=0.2VDD ; Vtp= 0.3VDD

Z pu 2 Z pu1  0.8 
=  
Z pd 2 Z pd 1  0.5 

Therefore

From the above theory it is clear that, for an n-MOS transistor

(i). An inverter driven directly from the output of another should have a Zp.u/ Zpd. ratio of ≥ 4/1.
(ii).An inverter driven through one or more pass transistors should have a Zp.u./Zp.d ratio of ≥8/1
BiCMOS INVERTER:
 BiCMOS- Bipolar CMOS
 Combination of BJT & CMOS
 CMOS- for ideal logic levels & High i/p Impedance(input side)
 BJT-High driving capability(output side)
 T1, T2-BJT
 T3, T4-NMOS & PMOS

 Vin=0V T3-OFF, T1-OFF T4-ON, T2-ON

The load cap. Charges towards VDD with a drop of VBE of T2 Vout=VDD-VBE(sat)
 Vin=VDD T3-ON, T1-ON T4-OFF, T2-OFF
The load cap. discharges towards 0V plus VCEsat of T1 Vout=VCE(sat)
T1 and T2 will present low impedances when turned on into saturation and the load CL will be charges or
discharged rapidly.
Features & Advantages:
 The output logic levels will be good and will be close to the rail voltages VCEsat is small and VBE is
approximately +0.7 V.
 The inverter has a high input impedance.
 The inverter has low output impedance.
 The inverter has a high drive capability but occupies a relatively small area.
 The inverter has high noise margins
Disadvantages:
 DC path from VDD to GND through T3 and T1 when Vin=logic ‘1’.
 No discharge path for current from base of either bipolar transistor when it is being turned off. This will
slow down the action of this circuit.
Alternative Bi-CMOS:
 Dc path through T3 and T1 is eliminated, but the output voltage swing is now reduced, since the output
cannot fall below the base to emitter voltage VBE of T1.

ComparisonofBiCMOSandC-MOStechnologies
The BiCMOS gates perform in the same manner as the CMOS inverter in terms of power consumption,
because both gates display almost no static power consumption.
When comparing BiCMOS and CMOS in driving small capacitive loads, their performance are
comparable, however, making BiCMOS consume more power than CMOS. On the other hand, driving larger
capacitive loads makes BiCMOS in the advantage of consuming less power than CMOS, because the
construction of CMOS inverter chains are needed to drive large capacitance loads, which is not needed in
BiCMOS.
The BiCMOS inverter exhibits a substantial speed advantage over CMOS inverters, especially when
driving large capacitive loads. This is due to the bipolar transistor’s capability of effectively multiplying
its current.
For very low capacitive loads, the CMOS gate is faster than its BiCMOS counterpart due to small
values of Cint. This makes BiCMOS ineffective when it comes to the implementation of internal gates for
logic structures such as ALUs, where associated load capacitances are small. BiCMOS devices have speed
degradation in the low supply voltage region and also BiCMOS is having greater manufacturing complexity
than CMOS.
AssignmentQuestions:

1. Define threshold voltage? Drive the Vt equation for MOS transistor.

2. Explain with neat diagrams the various NMOS fabrication technology.
3. Draw and explain BiCMOS inverter circuit.
4. Discuss the Basic Electrical Properties of MOS and BiCMOS Circuits.
5. Derive the expression for estimation of Pull-Up to Pull-Down ratio of an n-MOS inverter driven by
another n-MOS inverter.
6. Derive the relationship between Ids and Vds
7. Derive the expression for transfer characteristics of CMOS Inverter.
8. Write about BiCMOS fabrication in a n-well process with a diagram.
9. Distinguish between Bipolar and CMOS devices technologies in brief.
10. Mention about the BICMOS Inverters and alternative BICMOS Inverters.
11. Determine the pull-up to pull down ratio for NMOS inverter driven by another NMOS Inverter
12. Draw the fabrication steps of CMOS transistor and explain its operation in detail.
13. Draw the fabrication steps of NMOS transistor and explain its operation in detail.