I2C – Inter-Integrated Circuit

- Dhruv Satasiya
 Content
• Introduction
• Comparing I2C and SPI
• Pin Description
• I2C Modes
• Start & Stop Conditions
• Working of I2C
• I2C Generic Configuration
• All About I2C Serial Clock(SCL)
• Various I2C Errors
 Introduction
• I2C (Inter-integrated circuit) is a synchronous serial communication protocol, where the
sender and receiver act based on a shared clock signal.
• I2C is fundamentally used to transfer and receive data over shorter distances with only 2
wires and significant data transfer speed.
• I2C can communicate at a speed of 100K bits/second up to 3.4M bits/second, depending
on the different modes.
• I2C-based communication can be accomplished between a distance of less than 0.5 meters
up to 2-3 meters.
• The preliminary advantage of the I2C protocol is its multi-master capability with the help
of only 2-wires, one SDA line and another SCL line.
 Comparing I2C and SPI
I2C SPI
• Slower data transfer speed • Faster data transfer speed
• Longer communication distance (0.5 to 2-3 • Shorter communication distance (10 feet)
meters) • Requires a minimum of 4 wires (The more
• Requires only 2 wires slaves, the more wires)

• Efficient multi-master capability

• No multi-master mode (however,
implemented using a complicated structure)
• Auto acknowledgment system • No acknowledgement
• Addressing mechanism for slaves • No addressing mechanism for slave devices
 Pin Description
1. SCL Line: As the name suggests, it generates
the serial clock required for synchronous.
communication.
2. SDA Line: This is the data line where either
the master or the slave places data to send or
receive.

I2C serial communication where MCUs can

behave as masters and sensors, displays, and
EEPROM can act as the slaves.
 I2C Modes
1. Standard Mode: This mode provides up to 100 kbps data transfer speed and is usually
used for communications with sensors and other low-speed peripherals.
2. Fast Mode: This mode can transfer the data up to the speed of 400 kbps and is generally
used with higher speed devices such as EEPROM and display controller.
3. Fast Mode Plus: This mode gives up to 1 Mbps of data transfer capability and establishes
communication in industrial equipment.
4. High-Speed Mode: As its name suggests, it can send and receive data at a speed of up to
3.4 Mbps and can be quite useful for video processing and high-performance sensors.
 Start & Stop Conditions
• I2C communication is restricted to following certain data package standards where the first
bit is always the start bit and the last bit is always the stop bit.
• How does the master generate these conditions?
• The START condition is generated when the SCL line is high and SDA makes a transition from
HIGH to LOW.
• Similarly, the STOP condition is generated when the SCL line is high and SDA makes a transition
from LOW to HIGH.

The picture taken from the

STM32F4xxx reference manual
represents the conditions.
 Working of I2C
• When using the I2C protocol, data is transferred in packets between the master and slave
devices. The process begins with the master generating a Start condition on the SDA line.
Following the start signal, the communication flow is as follows:
1. Address Byte:
• The master sends an Address Byte, which is 8 or 10 bits long, depending on the configuration.
• For 8-bit addressing: The first 7 bits represent the slave device's address.
• The last 1 bit specifies the operation:
• 0 for Write (Master → Slave).
• 1 for Read (Slave → Master).
2. ACK/NACK Bit:
• After the Address Byte is sent, the slave device sends the 9th bit (ACK bit).
• The slave acknowledges (ACK) if it recognizes the address; otherwise, it does nothing or sends a
NACK. Remember, the internal SFRs of any hardware have special status registers where all their
activities are recorded continuously by setting specific flags.
• In the STM32F407xx MCU, the ADDR flag located in I2C_SR1 acknowledges the successful
transmission of the address.

The above exhibit shows the NAK received by the master as the slave of
the given address was not recognized.
3. Data Transfer:
• Next, 8 bits of data are transmitted either:
• From the master to the slave (in a write operation), or
• From the slave to the master (in a read operation).
• Once the data byte is sent, the slave sends an ACK bit to confirm receipt of the data.
4. Stop Condition:
• After the desired communication is complete, the master generates a Stop condition, signaling
the end of the communication.
 I2C Engine with
only shift register
and data register

I2C SFRs for

various
configurations

Fig. 3 I2C Block Diagram for STM32F407VGT6 Arm Cortex M4 MCU

 I2C Generic Configurations
1. Mode Configuration – Standard or Fast mode?
2. Serial Clock Speed Configuration – SCL Line
3. Device Address Configuration – Applicable when a device is a slave
4. Acknowledgement Mechanism Configuration
5. Rise Time Configuration
Various structures related to the I2C generic configurations and
handles are created using C programming.
 All About I2C Serial Clock(SCL)
• In the context of the STM32F407xxx MCU, two Special Functions Registers(SFRs) must be
configured to achieve the desired serial clock on the I2C line.
1. I2C_CR2 – I2C Control Register 2
2. I2C_CCR – I2C Clock Control Register
• Control Register-2 contains the FREQ field to configure the peripheral clock
frequency(PCLK). This frequency is the frequency of the APB bus where I2Cx (x = 1, 2, 3)
peripherals are hanging.
• Clock Control Register contains a total of 3 fields to be configured before making use of
I2Cx peripherals.
1. F/S bit field: This bit field allows running I2C on either Standard Mode(SM) or Fast
Mode(FM).
2. DUTY bit field: This bit field is specifically used to select the duty cycle option when F/S is
set to 1, which means I2C is configured to run in Fast Mode(FM).
• In STM32F407xxx MCU, there are a total of 2 types of duty cycle options are available:
a. 𝑻𝒍𝒐𝒘 = 2 𝑻𝒉𝒊𝒈𝒉 or
b. 𝑻𝒍𝒐𝒘 = 1.8 𝑻𝒉𝒊𝒈𝒉 (Where 1.8 Is ratio of 16/9)
3. CCR[11:0] bits field: This is a 12 bits long field, where final calculated value of CCR is
placed. It uses different mathematical formulas to derive the value.
1. Scenario – 1
• I2C is configured for Standard Mode(SM), so the duty cycle is set by default to 50% and the
maximum achievable SCL frequency will be 100KHz.
• 𝑻𝒉𝒊𝒈𝒉 = CCR * 𝑻𝒑𝒄𝒍𝒌
• 𝑻𝒍𝒐𝒘 = CCR * 𝑻𝒑𝒄𝒍𝒌
2. Scenario – 2
• I2C is configured for Fast Mode(FM), so there are a total of 2 options for Duty Cycle and the
maximum achievable SCL frequency will be 400KHz(when DUTY = 1).
• If DUTY field is set to 1 (DUTY = 1)
a. 𝑻𝒉𝒊𝒈𝒉 = CCR * 𝑻𝒑𝒄𝒍𝒌
b. 𝑻𝒍𝒐𝒘 = 2*CCR * 𝑻𝒑𝒄𝒍𝒌
• If DUTY field is set to 1 (DUTY = 1)
a. 𝑻𝒉𝒊𝒈𝒉 = 9*CCR * 𝑻𝒑𝒄𝒍𝒌
b. 𝑻𝒍𝒐𝒘 = 16*CCR * 𝑻𝒑𝒄𝒍𝒌
 Various I2C Errors

• 1. Bus Error: This error arises when an SDA line transition is non-valid during a byte
transfer. Such as the rising or falling of the SDA line while SCL is high.
• 2. Arbitration Loss Error: This error occurs when the interface loses the arbitration to
another master. This only happens in the multi-master mode of I2C.
• 3. ACK Failure Error: This error occurs when no ACK is returned for the byte transferred.
• 4. Overrun Error: This arises only during the reception process. When a new byte is
received and the data register has not been read yet and new byte received is lost.
• 5. Underrun Error: This is similar to overrun but occurs during the transmission. When a
new byte should be sent and the data register has not been written yet and the same byte
is sent twice.
• 6. PEC Error: This error happens when there is a CRC mismatch if the CRC feature is
enabled.
• 7. Time-Out Error: This happens when the master or slave stretches the clock, by holding
low for more than the specified amount of time.
Thank You…