Computer Organization Architecture Important Questions

Q.1 What are functional units? Discuss the basic functional units of a computer?
Q.2 With a neat diagram explains the basic operational concepts of computer?
Q.3 Explain various types of buses? Discuss the functions of system software?
Q.4 Define the term Computer architecture and Computer organization arbitration.
Q.5 What is mean by bus arbitration? List different types of bus arbitration.
Q.6 Explain bus and Memory Transfer.
Q.7 What do you mean by processor organization? Explain various types of processor
organization.
Q.8 Differentiate between daisy chaining and centralized parallel arbitration.
Q.9 What is addressing mode? Explain any four addressing mode.
Q.10 Draw and Explain General registers organization.
Q.11 A digital computer has a common bus system for 8 registers of 16 bit each. The
bus is constructed using multiplexers.
i. How many select input are there in each multiplexer?
ii. What is the size of multiplexers needed?
iii. How many multiplexers are there in the bus?
Q.12 Discuss and differentiate multi computers and multi processors.
Q.13 What is an instruction code? Explain in detail various addressing modes.
Q.14 Explain the instruction cycle with a neat flow chart.
Q.15 Explain the data transfer and manipulation instructions.
Q.16 Define interrupt? Explain the types of interrupts.
Q.17 Explain the design of control unit.
Q.18 Define and discuss the differences between hardwired control unit and micro
programmed control unit.
Q.19 Define the Static RAM (SRAM). Explain the working of SRAM cell with a neat
diagram.
Q.20 Define the Dynamic RAM (DRAM). Explain the working of DRAM with a neat
diagram.
Q.21 Define the Read Only Memory. Explain in detail the types of ROM’s.
Q.22 Define and discuss the types of replacement algorithms.
Q.23 Define Virtual Memory. Explain the process of converting virtual addresses to
physical addresses with a neat diagram.
Q.24 Explain the following secondary storage devices
o Magnetic disk.
o Magnetic tape.
Q.25 Explain the following mapping functions
o Associative mapping.
o Direct map
o Set Associative mapping.
Q.26 Explain about asynchronous data transfer and asynchronous communication
interface.
Q.27 Explain about modes of transfer.
Q.28 Explain about interrupt priorities
Q.29 Explain about DMA in detail.
Q.30 Define pipelining? Explain the structure of pipelining with an example.
Q.31 Explaining the implementation of four stage pipelining. List out the limitations
of instruction pipeline.
Q.32 Write a program to evaluate the arithmetic statement. P = ((X − 𝑌 + 𝑍) ∗ (A ^
B))/( C ^ D ∗ E) By using (i) Two address instructions (ii) One address
instructions (iii) Zero address instructions.
Q.33 Discuss the Memory Hierarchy in computer system with regard to Speed, Size
and Cost.
Q.34 Give characteristics of RISC and CISC.
Q.35 Explain Main Memory. OR How main memory is useful in computer system?
OR Explain RAM and ROM.
Q.36 Explain Cache Memory OR Write short note on Cache Memory
Q.37 List the difference between 2 D RAM and 2.5D RAM with suitable diagram.
Q.38 Explain 2 D RAM and 2.5D RAM with suitable diagram.
Q.39 What is the difference between programmed I/O, interrupt driven I/O
Q.40 Explain IEEE-754 standard for floating point representation. Express
(314.175)10 in all the IEEE-754 models.
Q.41 Explain Auxiliary Memory.
Q.42 Discuss the various types of address mapping used in cache memory.
Q.43 With a neat schematic diagram, explain about DMA controller and its mode of
data transfer.
Q.44 Calculate the page fault for a given string with the help of LRU & FIFO page
replacement algorithm, Size of frames = 4 and string 1 2 3 4 2 1 5 6 2 1 2 3 7 6 3 2
1 2 3 6.
Q.45 Discuss the various types of address mapping used in cache memory.
Q.46 Differentiate between hardwired and micro programmed control unit. Explain
each component of hardwired control unit organization.
Q.47 Consider a cache consisting of 256 blocks of 16 words each, for a total of 4096
words. Assume that the main memory is addressable by a 16-bit address and
consists of 4K blocks. How many bits are there in the tag, set, and word for a 2-
way set associative technique?
Ans. To determine the number of bits for the Tag, Index, Block, and Word fields in a 2-
way set associative cache, we can use the following formulas:
Total Cache Size = Number of Blocks * Block Size
Number of Blocks = Number of Sets * Ways
Block Size = Number of Words per Block
Number of Sets = Total Cache Size / (Block Size * Ways)
Given:
Total Cache Size = 4096 words
Block Size = 16 words
Number of Blocks = 256
Addressable main memory = 16 bits
Data accommodated = 12 bits
2-way set associative technique
First, let's calculate the number of sets: Number of Sets = Total Cache Size / (Block
Size * Ways) Number of Sets = 4096 / (16 * 2) = 128
 Now, we can calculate the number of bits for the Tag, Index, Block, and Word
fields:
Block offset (Word field) = log2(Block Size) = log2(16) = 4 bits
Index bits = log2(Number of Sets) = log2(128) = 7 bits
Tag bits = Addressable main memory - (Index bits + Block offset) = 16 - (7 + 4) =
5 bits
For a 2-way set associative cache, each set contains 2 blocks. Therefore, the valid
bit is 1 bit for each block.
So, the format of the address in the cache is:
Tag (5 bits) | Index (7 bits) | Block offset (4 bits) | Valid bit (1 bit)
The size of the cache memory can be calculated using the formula: Size of Cache
Memory = Total Cache Size = 4096 words
In summary, the number of bits for each field in the 2-way set associative cache is
as follows:
Tag: 5 bits
Index: 7 bits
Block: 4 bits
Word: 16 bits
Valid bit: 1 bit
Size of Cache Memory: 4096 words

Q.48 Differentiate between memory stack and register stack.

Q.49 The logical address space in a computer system consists of 128 segments. Each
[03] segment can have up to 32 pages of 4K words in each. Physical memory
consists of 4K blocks of 4K words in each. Formulate the logical and physical
address formats.
Q.50 Show step by step the multiplication process using Booth’s algorithm when (+ 15)
and (– 13) numbers are multiplied. Assume 5-bit registers that hold signed
numbers.
Q.51 Show the multiplication process using Booth’s algorithm when the following
numbers are multiplied: (– 13) by (+ 8).
Q.52 Differentiate between linear and non-linear pipeline.
Q.53 Describe I/O interface. Why they are needed? OR Why input-output interface is
required? Describe in detail.
Q.54 What is the difference between isolated I/O and memory mapped I/O? Explain
the advantages and disadvantages of each.
Q.55 What do you mean by Input-Output (I/O) processor?
Q.56 Draw a diagram of a Bus system in which it uses 3 state buffer and a decoder
instead of the multiplexer
Q.57 Explain in detail the principle of carry look ahead adder and design 4-bit CLA
adder
Q.58 Show the systemic multiplication process of (20) X (-19) using Booth’s algorithm.
Q.59 Represent (1460.125)10 in IEEE 754 format Floating point representation using
(a) single precision
(b) Double precision.
Q.60 A computer uses RAM chips of 1×1024 capacity. How many chips will be
required to obtain a memory capacity of 16 𝐾 bytes? How many chips will be
 required and how many address lines will be connected to provide a capacity of
1024 bytes?

Ans. Given:
The capacity of the chip is = (1024×1) =1024bits
We have to obtain a memory whose capacity is 16 K bytes or (16×1024×8) bits.

Hence:
The number of chips required to obtain a memory capacity of 16 K bytes are:
=16×1024×8/1024
128
Again:
We have to obtain a memory whose capacity is 1024bytes or (1024×8) bits

The number of chips required to obtain a memory capacity of 1024 bytes are:
=1024×8/1024
8
Now
10
Since 2 =1024 so a memory chip capacity of 1024 bytes connected with
10 address lines.