PRODUCT

BRIEF

CV5
8K AI Vision Processor

Key Features
High-Efficiency Video Encoding
• H.265 and H.264 video compression
• Flexible multi-streaming capability
• 8KP60 video performance
• Multiple constant bit rate (CBR) and variable bit rate
(VBR) control modes
• Smart H.264 and H.265 encoder algorithms
Overview
Computer Vision Engine CVflow ® Ambarella’s CV5 provides 8K image processing, video encoding / decoding, and CVflow ® computer
• Convolutional neural network (CNN) / deep neural vision processing in a single, low-power design. Fabricated in advanced 5 nm process technology, it
network (DNN)-based processing: detection, achieves power consumption below 2W for 8K video recording at 30 fps, and below 5W for 8K video
classification, and more recording at 60 fps. The CV5’s CVflow architecture provides the DNN processing required for the next
• Accelerators for conventional computer vision generation of intelligent cameras.
(CV) operations
• CNN toolkit for easy porting of neural networks CV5’s advanced image signal processor (ISP) provides outstanding imaging in low-light conditions,
implemented in Caffe, TensorFlow, PyTorch, or while HDR processing extracts maximum image detail in high-contrast scenes, further enhancing the
ONNX frameworks computer vision capabilities of the chip. CV5 includes efficient 8K encoding in both AVC and HEVC
video formats, delivering high-resolution video recording and streaming with very low bit rates. The
Advanced Image Processing CV5’s CVflow architecture provides computer vision processing at full 8K, enabling image recognition
• Multi-exposure line-interleaved high dynamic over long distances, with high accuracy.
range (HDR)
• Hardware dewarping engine The exceptionally low power consumption of the CV5 system on chip (SoC) makes it an ideal
• Electronic image stabilization (EIS) solution for the next generation of high-resolution and high frame-rate action / sports cameras,
• Multiple camera support robotic cameras, VR cameras, and consumer / industrial drones. In the video telematics space, CV5
• 3D motion-compensated temporal filtering (MCTF) provides image processing and both AVC and HEVC recording for video feeds from multiple cameras,
• Superior low-light processing employing CVflow ADAS algorithms to provide lane departure warning, forward collision warning,
• RGGB / RCCB / RCCC / RGB-IR / monochrome driver monitoring, and more. To help customers easily port their own neural networks onto the CV5
sensor support SoC, Ambarella’s software development kit offers a complete set of tools for software and artificial
intelligence (AI) implementation.
Target Applications
• Sports cameras
• Robotic cameras I2C SPI PCIe
GPIO
UART Ethernet
Timers
JTAG
• Drones WDT

• Virtual reality (VR) cameras

Video Input Video Codec Video Output
• Multi-channel drive recorders / data loggers Image Signal Dual Core H.264
Processor (ISP) Arm® Cortex®-A76 H.265
• Multi-camera aftermarket advanced driver assistance Sensor 1 MIPI D-PHY
MJPEG
MIPI CSI-2®

systems (ADAS) MIPI DSI® LCD

MIPI C-PHY Security Features
Enhanced Secure Boot with TrustZone®,
Ambarella Memory System TRNG, OTP, Arm TBSA Compliance,
SLVS HDMI
DRAM Scrambling and Virtualization

Sensor 14 SLVS-EC Analog

Computer Vision Processor

SD USB 3.2
Audio Input DDR SPI NAND Host / Device Audio Output
SDIO SPI NOR USB 2.0
(I2S) Interface (I²S)
SDXC Device

64-bit

LPDDR4x SD Card
LPDDR5 eMMC WiFi / BLE
LPDDR5x

CV5 Block Diagram

General Specifications
Processor Cores • RGGB / RCCB / RCCC / RGB-IR / monochrome Memory Interfaces
• Dual-core Arm® Cortex®-A76 up to 1.6 GHz sensor support • LPDDR4x up to 3.6 Gbits/s/pin, 64-bit data bus,
• 64 KB / 64 KB L1 cache and 256 KB L2 cache • Adjustable auto exposure (AE) / auto white up to 16 GB capacity for LPDDR4x
per Cortex-A76 balance (AWB) • LPDDR5(x) up to 5 Gbits/s/pin, 64-bit data bus,
• 1024 KB L3 cache per dual-core Cortex-A76 • Advanced dynamic range (WDR and up to 32 GB capacity for LPDDR5(x)
• NEON™ SIMD and FPU acceleration HDR) engine • Three SD controllers
• AES / SHA-2 / ED25519 crypto acceleration • Chromatic aberration correction • Single- / dual- / quad- / octal-SPI NOR and
• 180° and 360° fisheye lens and geometric single- / dual- / quad-SPI NAND
Computer Vision Processor distortion correction • Boot from SPI NAND / SPI NOR / USB / eMMC
• CVflow processor with parallel architecture to • On-screen (OSD) engine and overlays
boost performance of the low-level portion of • Gamma compensation and color enhancement Peripheral Interfaces
perception algorithms • Vignetting compensation • 10 / 100 / 1000 Ethernet with RMII / RGMII
• 3-axis electronic image stabilization (EIS) • 4-lane PCIe
Video Input • Crop, mirror, flip, and 90° / 270° rotation • 1x USB 3.2 host / device and 1x USB 2.0
• 12-lane SLVS-EC (1–8 lane single link, device only with PHY
1-6 lane * 2 dual link) Video Encoding / Decoding • 2x I2S input and output interfaces, 1x DMIC
• 2x MIPI DC-PHY® • H.265 (HEVC) MP L6.1, H.264 (AVC) MP / HP • 2x CAN FD interface
◦ Each DC-PHY supports C-PHY mode (1–3 L6.1, and MJPEG • Multiplexed 5x UART and 6 I/F of SSI / IDC
lanes) or D-PHY mode (1–4 lanes) • 8KP60 maximum encoding / decoding • Multiple GPIO ports, PWM, IR, and ADC
• 2x MIPI D-PHY (1–4 lanes each) performance • Watchdog timer, general purpose timers,
• 2x SLVS (1–4 lanes each) • Flexible group of pictures (GOP) configuration and JTAG
• Up to 14 cameras using MIPI virtual channels with I, P, and B frames
• Multiple CBR and VBR control modules Physical
Video Output • 5 nm low-power complimentary metal-oxide
• HDMI® 2.0 including PHY with customer Security Features semiconductor (CMOS) technology
electronic control (CEC) support • Enhanced secure boot with TrustZone® and • 16 mm x 16 mm FC TFBGA with 0.5 mm
• PAL / NTSC composite SD video secure memory, true random number generator ball pitch
• 2x MIPI DSI® / CSI-2® (TRNG), one-time programmable memory • Operating temperature -20°C to +85°C
(OTP), Arm trusted base system architecture (additional operational temperature options
CMOS Sensor / Image Processing (TBSA) compliance, DRAM scrambling, available)
• Processing up to 8KP60 (1920 MPixel/s) and virtualization
• Lens shading and fixed-pattern noise correction
• Multi-exposure HDR (line-interleavened Tools for Development
sensors) • CNN toolkit to ease the porting of CNNs trained
• 3D motion-compensated temporal using frameworks such as Caffe, PyTorch,
filtering (MCTF) TensorFlow, or ONNX
• Compiler, debugger, and profiler for both Arm
and microcode development

CV5 Camera Development Platform

The CV5 camera development platform contains the necessary tools, software, hardware, and documentation to develop a camera utilizing the
powerful CVflow processor while supporting the development of customized features.

Evaluation Kit Software Development Kit

• CV5 main board with connectors for sensor / lens board • Royalty-free libraries for ISP, dewarp, and
and peripherals video recording
• Sensor board: Sony, onsemi, Omnivision, and others • Image tuning and manufacturing calibration tools
• Datasheet, BOM, schematics, and layout • Detailed documentation, including a programmer’s
• SDK and reference application with C source code guide and more
available with additional licensing • CNN / DNN model preparation, porting, and profiling tools

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Copyright Ambarella International LP. All rights reserved. Ambarella and the Ambarella logo are trademarks of Ambarella International LP. All other brands, product names, and company names
are trademarks of their respective owners. The information in this document is believed to be reliable, but may project preliminary functionality not yet available. Ambarella makes no guarantee
or warranty concerning the accuracy and availability of said information and shall not be responsible for any loss or damage whatever nature resulting from the use of, or reliance upon it.
Ambarella does not guarantee that the use of any information contained herein will not infringe upon patent, trademark, copyright, or other rights of third parties. Ambarella reserves the right to
make changes in the product and / or its specifications presented in this publication at any time without notice.

November 2022